#define iowrite32 writel
#define ioread8 readb
#define iowrite8 writeb
- #define wmb()
- #define rmb()
#else
#endif
-#define INT_CONF 0x00000040 /* valeur de config du registre INTCSR du PLX */
+#define INT_CONF 0x00000040 /* value for register INTCSR of PLX */
#define NSI_VENDOR_ID 0x1637
#define NSI_CANPCI_DEVICE_ID 0x0001
enum PORT2 { P2_0=1, P2_1=1<<1, P2_2=1<<2, P2_3=1<<3, P2_4=1<<4, P2_5=1<<5, P2_6=1<<6, P2_7=1<<7 };
-/* Definition de tous les registres du PLX */
-#define PLX_CNTRL 0x50 /* Regitre de control */
-#define PLX_INTCSR 0x4C /* Registe pour les interruptions */
-
-/* Horloge en Hz du chip i82527 respecter le tableau suivant: */
-/* =========================================
- * | XTAL | SCLK (DSC bit) | MCLK (DMC bit) |
- * |======|================|================|
- * | 4MHz | 4MHz (0) | 4MHz (0) | NE PAS OUBLIER DE POSITIONNER LES BITS DSC et DMC EN FONTION
- * | 8MHz | 8MHz (0) | 8MHz (0) |
- * |10MHz | 10MHz (0) | 5MHz (1) |
- * |12MHz | 6MHZ (1) | 6MHZ (0) |
- * |16MHz | 8MHz (1) | 8MHz (0) |
- * ========================================== */
+/*PLX register definition */
+#define PLX_CNTRL 0x50 /* Controle register */
+#define PLX_INTCSR 0x4C /* Interruption controle register */
+
+/* This value define the i82527 clock frequency */
#define iCLOCK 16000000
-static CAN_DEFINE_SPINLOCK(nsicanpci_port_lock);
/* Il faut reserver 4 zones:
* BAR0: 128 octets memoire (32bits) pour les registres du PLX9052
*/
/* Variables globales contenant les @ des IO-Memory apres remap */
#define NB_VALID_BAR 4
-void* addr_BAR_remap[NB_VALID_BAR]={0,0,0,0};
+
+typedef struct {
+ void* addr_BAR_remap[NB_VALID_BAR];
+}t_CardArray;
void nsi_canpci_connect_irq(struct candevice_t *candev)
{
- /* Preparation du registre pour configurer les INT locales 1 et 2 du PLX, INT actif à l'etat Haut */
-// iowrite32(INT_CONF,(void*)(candev->dev_base_addr+PLX_INTCSR));
-// wmb();
-// DEBUGMSG("Interruptions du PLX configurees !!\n");
-
+//Not used
}
void nsi_canpci_disconnect_irq(struct candevice_t *candev)
{
-// Il faut aussi desactiver les interruption du PLX, sous peine de freeze au prochain init_module
-// tout en laissant le bit isa mis a 1
- iowrite32(0x0,(void*)(candev->dev_base_addr+PLX_INTCSR));
- wmb();
- DEBUGMSG("disable interruption du PLX\n");
+//on disconnecting interrupt we need to disable interruption form PLX
+ iowrite32(0x0,(void*)(candev->io_addr+PLX_INTCSR));
+ DEBUGMSG("PLX interrupt disabled\n");
}
int nsi_canpci_config_irqs(struct canchip_t *chip, short irqs)
unsigned long it_mask,it_reg;
struct candevice_t *candev;
it_mask=0;
- DEBUGMSG("NSI Interrupt configuration\n");
+ DEBUGMSG("Configuring NSI CANPCI interrupt\n");
can_write_reg(chip,irqs,iCTL);
if( (irqs&0x0E)!=0)
{//At least one interrupt source requested
it_mask=8;
}
candev=(struct candevice_t *)chip->chip_data;
- it_reg = ioread32( (void*)(candev->dev_base_addr+PLX_INTCSR));
- rmb();
+ it_reg = ioread32( (void*)(candev->io_addr+PLX_INTCSR));
it_reg|=it_mask|0x40;
- iowrite32(it_reg,(void*)(candev->dev_base_addr+PLX_INTCSR));
- wmb();
+ iowrite32(it_reg,(void*)(candev->io_addr+PLX_INTCSR));
}
else
{//No more interrupt source
it_mask=8;
}
candev=(struct candevice_t *)chip->chip_data;
- it_reg = ioread32( (void*)(candev->dev_base_addr+PLX_INTCSR));
- rmb();
+ it_reg = ioread32( (void*)(candev->io_addr+PLX_INTCSR));
it_reg&=~it_mask;
- iowrite32(it_reg,(void*)(candev->dev_base_addr+PLX_INTCSR));
- wmb();
+ iowrite32(it_reg,(void*)(candev->io_addr+PLX_INTCSR));
}
return 0;
}
int nsi_canpci_i82527_chip_config(struct canchip_t *chip)
{
- //Normale fonction
can_write_reg(chip,chip->int_cpu_reg,iCPU); // Configure cpu interface
can_write_reg(chip,(iCTL_CCE|iCTL_INI),iCTL); // Enable configuration
i82527_seg_write_reg(chip,chip->int_clk_reg,iCLK); // Set clock out slew rates
i82527_seg_write_reg(chip,chip->int_bus_reg,iBUS); /* Bus configuration */
- can_write_reg(chip,P2_2|P2_1,iP2C); // Configure P2_2,P2_1 en sortie
- can_write_reg(chip,P2_2|P2_1,iP2O); // Positionne P2_2 a 1
+ can_write_reg(chip,P2_2|P2_1,iP2C); // The pin P2_2,P2_1 of the 527 must be set as output
+ can_write_reg(chip,P2_2|P2_1,iP2O); // and P2_2 must be set to 1
can_write_reg(chip,0x00,iSTAT); /* Clear error status register */
it_mask=8;
}
candev=(struct candevice_t *)chip->chip_data;
- it_reg = ioread32( (void*)(candev->dev_base_addr+PLX_INTCSR));
+ it_reg = ioread32( (void*)(candev->io_addr+PLX_INTCSR));
rmb();
it_reg|=it_mask|0x40;
- iowrite32(it_reg,(void*)(candev->dev_base_addr+PLX_INTCSR));
+ iowrite32(it_reg,(void*)(candev->io_addr+PLX_INTCSR));
wmb();
i82527_start_chip(chip);
return 0;
it_mask=8;
}
candev=(struct candevice_t *)chip->chip_data;
- it_reg = ioread32( (void*)(candev->dev_base_addr+PLX_INTCSR));
+ it_reg = ioread32( (void*)(candev->io_addr+PLX_INTCSR));
rmb();
it_reg&=~it_mask;
- iowrite32(it_reg,(void*)(candev->dev_base_addr+PLX_INTCSR));
+ iowrite32(it_reg,(void*)(candev->io_addr+PLX_INTCSR));
wmb();
i82527_stop_chip(chip);
return 0;
struct candevice_t *candev;
candev=(struct candevice_t *)chip->chip_data;
retcode = CANCHIP_IRQ_NONE;
- it_reg = ioread32( (void*)(candev->dev_base_addr+PLX_INTCSR));
+ it_reg = ioread32( (void*)(candev->io_addr+PLX_INTCSR));
rmb();
if(chip->chip_idx==0)
{
if((it_reg &0x4)!=0) //interrupt active
{
if(i82527_irq_handler(irq,chip)==CANCHIP_IRQ_NONE)
- {//soucis avec les IT
+ {//some trouble with IT
it_reg&=~(0x01);
- CANMSG("IT du canal0 annulee pour cause de dysonctionnement\n");
+ CANMSG("Unexcepted interruption from canal0, interruption is canceled\n");
}else
{
}
else
{
- if((it_reg &0x20)!=0) //interrupt active
+ if((it_reg &0x20)!=0) //interrupt is set
{
if(i82527_irq_handler(irq,chip)==CANCHIP_IRQ_NONE)
{//soucis avec les IT
it_reg&=~(0x08);
- CANMSG("IT du canal1 annulee pour cause de dysonctionnement\n");
+ CANMSG("Unexcepted interruption from canal1, interruption is canceled\n");
}else
{
retcode=CANCHIP_IRQ_HANDLED;
int nsi_canpci_request_io(struct candevice_t *candev)
{
(void)candev;
- if(addr_BAR_remap[0]==NULL)
+ if(candev->dev_base_addr==0)
return -EIO;
return 0;
}
{
unsigned long reg_reset;
struct pci_dev *pcidev = candev->sysdevptr.pcidev;
- DEBUGMSG("Liberation des io de la carte \n");
+ DEBUGMSG("Releasing board io\n");
nsi_canpci_disconnect_irq(candev);
- // Recherche du registre de controle du PLX parmi les IO-port du PLX */
- reg_reset = ioread32( (void*)(candev->dev_base_addr+PLX_CNTRL));
+ // First, set RESET signal to 0
+ reg_reset = ioread32( (void*)(candev->io_addr+PLX_CNTRL));
reg_reset&=(~(0x40000000));
rmb();
- iowrite32( (reg_reset | 0x40000000 ),(void*)(candev->dev_base_addr+PLX_CNTRL)); /* Mise à '1' du bit reset */
+ //Then set it to '1' for reseting the board
+ iowrite32( (reg_reset | 0x40000000 ),(void*)(candev->io_addr+PLX_CNTRL));
wmb();
- udelay(2500); /* Reset supérieur a 1ms car necessaire aux i82527 */
- iowrite32( (reg_reset ),(void*)(candev->dev_base_addr+PLX_CNTRL)); /* Mise à '0' du bit reset */
+ udelay(2500); /* This delay must be greater than 1ms for i82527 */
+ iowrite32( (reg_reset ),(void*)(candev->io_addr+PLX_CNTRL)); //Releasing RESET signal
wmb();
- udelay(2500); /* Reset supérieur a 1ms car necessaire aux i82527 */
- iounmap(addr_BAR_remap[0]);
- iounmap(addr_BAR_remap[1]);
- iounmap(addr_BAR_remap[2]);
- iounmap(addr_BAR_remap[3]);
-
+ udelay(2500); // Waiting for some additionnal time before writing in the 82527
+ iounmap(((t_CardArray*)(candev->dev_base_addr))->addr_BAR_remap[0]);
+ iounmap(((t_CardArray*)(candev->dev_base_addr))->addr_BAR_remap[1]);
+ iounmap(((t_CardArray*)(candev->dev_base_addr))->addr_BAR_remap[2]);
+ iounmap(((t_CardArray*)(candev->dev_base_addr))->addr_BAR_remap[3]);
+ kfree((void*)(candev->dev_base_addr));
pci_release_region(pcidev,0);
pci_release_region(pcidev,1);
pci_release_region(pcidev,2);
{
unsigned long reg_reset;
- DEBUGMSG("Reset de la carte !!!\n");
- /* Il faut aussi desactiver les interruption du PLX, sous peine de freeze au prochain init_module */
+ DEBUGMSG("Board reset !!!\n");
+ // Before reset disconnet interrupt to avoir freeze
nsi_canpci_disconnect_irq(candev);
- // Recherche du registre de controle du PLX parmi les IO-port du PLX */
- reg_reset = ioread32( (void*)(candev->dev_base_addr+PLX_CNTRL));
+ // First, set RESET signal to 0
+ reg_reset = ioread32( (void*)(candev->io_addr+PLX_CNTRL));
reg_reset&=(~(0x40000000));
- iowrite32( (reg_reset | 0x40000000 ),(void*)(candev->dev_base_addr+PLX_CNTRL)); /* Mise à '1' du bit reset */
+ //Then set it to '1' for reseting the board
+ iowrite32( (reg_reset | 0x40000000 ),(void*)(candev->io_addr+PLX_CNTRL));
wmb();
- udelay(2500); /* Reset supérieur a 1ms car necessaire aux i82527 */
- iowrite32(reg_reset,(void*)(candev->dev_base_addr+PLX_CNTRL)); /* Mise à '0' du bit reset */
+ udelay(2500); /* This delay must be greater than 1ms for i82527 */
+ iowrite32(reg_reset,(void*)(candev->io_addr+PLX_CNTRL)); //Releasing RESET signal
wmb();
- udelay(2500); /* Attente, pour laisser les composants s'initialiser */
- DEBUGMSG("Reset termine !!!\n");
+ udelay(2500); // Waiting for some additionnal time before writing in the 82527
+ DEBUGMSG("Reset done !!!\n");
nsi_canpci_connect_irq(candev);
return 0;
{
struct pci_dev *pcidev = NULL;
- /* recherche de la carte NSI CANPCI sur le bus */
+ /* looking for NSI CANPCI ident on the pci bus*/
do
{
pcidev = pci_find_device(NSI_VENDOR_ID, NSI_CANPCI_DEVICE_ID, pcidev);
{
return -EIO;
}
+ candev->dev_base_addr=(unsigned long)(kmalloc(sizeof(t_CardArray),GFP_ATOMIC));
- addr_BAR_remap[0]=ioremap(pci_resource_start(pcidev,0),pci_resource_len(pcidev,0) );
- addr_BAR_remap[1]=ioremap(pci_resource_start(pcidev,1),pci_resource_len(pcidev,1) );
- addr_BAR_remap[2]=ioremap(pci_resource_start(pcidev,2),pci_resource_len(pcidev,2) );
- addr_BAR_remap[3]=ioremap(pci_resource_start(pcidev,3),pci_resource_len(pcidev,3) );
+ if((unsigned long)candev->dev_base_addr==0)
+ return -EIO;
+ //PLX register
+ ((t_CardArray*)(candev->dev_base_addr))->addr_BAR_remap[0]=ioremap(pci_resource_start(pcidev,0),pci_resource_len(pcidev,0) );
+ //PLX IO
+ ((t_CardArray*)(candev->dev_base_addr))->addr_BAR_remap[1]=ioremap(pci_resource_start(pcidev,1),pci_resource_len(pcidev,1) );
+ //Chip 0
+ ((t_CardArray*)(candev->dev_base_addr))->addr_BAR_remap[2]=ioremap(pci_resource_start(pcidev,2),pci_resource_len(pcidev,2) );
+ //Chip 1
+ ((t_CardArray*)(candev->dev_base_addr))->addr_BAR_remap[3]=ioremap(pci_resource_start(pcidev,3),pci_resource_len(pcidev,3) );
- candev->dev_base_addr=(unsigned long)(addr_BAR_remap[0]);
+ //Short acces to plx register
+ candev->io_addr=(unsigned long)(((t_CardArray*)(candev->dev_base_addr))->addr_BAR_remap[0]);
return 0;
}
candev->chip[chipnr]->chipspecops->irq_handler=nsi_canpci_irq_handler;
candev->chip[chipnr]->chip_data =candev;
- candev->chip[chipnr]->chip_base_addr= (unsigned long)addr_BAR_remap[chipnr+2];
- candev->chip[chipnr]->clock = 16000000;
+ candev->chip[chipnr]->chip_base_addr= (unsigned long) (((t_CardArray*)(candev->dev_base_addr))->addr_BAR_remap[chipnr+2]);
+ candev->chip[chipnr]->clock = iCLOCK;
candev->chip[chipnr]->chip_irq=candev->sysdevptr.pcidev->irq;
candev->chip[chipnr]->flags=CHIP_IRQ_PCI;
candev->chip[chipnr]->int_cpu_reg = iCPU_DSC+iCPU_CEN;
void nsi_canpci_write_register(unsigned data, unsigned long address)
{
iowrite8((u8)data,(void*)address);
- wmb(); /* Assure que la donnee a ete ecrite */
}
/* The function template_read_register is used to read from hardware registers
We use the two register, we write the address where we
want to read in a first time. In a second time we read the
data */
- unsigned char ret;
- can_spin_irqflags_t flags;
- can_spin_lock_irqsave(&nsicanpci_port_lock,flags);
- rmb();
- ret=ioread8((void*)address);
- can_spin_unlock_irqrestore(&nsicanpci_port_lock,flags);
- return ret;
+ return ioread8((void*)address);
}
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