Minor chages to setup and enable filter masks for C_CAN chip correctly.
authorppisa <ppisa>
Wed, 27 Jun 2007 00:32:35 +0000 (00:32 +0000)
committerppisa <ppisa>
Wed, 27 Jun 2007 00:32:35 +0000 (00:32 +0000)
lincan/src/c_can.c
lincan/src/c_can_irq.c
lincan/src/sysdep_lnx.c

index 9929467..cddac82 100644 (file)
@@ -96,10 +96,10 @@ int c_can_chip_config(struct canchip_t *pchip)
                return -1;
 
        if (pchip->baudrate == 0)
-               pchip->baudrate = 1000;
+               pchip->baudrate = 1000000;
 
        if (c_can_baud_rate
-           (pchip, pchip->baudrate * 1000, pchip->clock, 0, 75, 0)) {
+           (pchip, pchip->baudrate, pchip->clock, 0, 75, 0)) {
                CANMSG("Error configuring baud rate\n");
                return -ENODEV;
        }
@@ -143,8 +143,8 @@ int c_can_if1_busycheck(struct canchip_t *pchip)
        unsigned short comreg = 0;
 
        comreg = c_can_read_reg_w(pchip, CCIF1CR);
-       while ((comreg & IFXCR_BUSY) && (i <= 10)) {
-               udelay(100);    //100 microseconds
+       while ((comreg & IFXCR_BUSY) && (i <= 100)) {
+               udelay(1);      //1 microseconds
                i++;
                comreg = c_can_read_reg_w(pchip, CCIF1CR);
        }
@@ -167,8 +167,8 @@ int c_can_if2_busycheck(struct canchip_t *pchip)
        unsigned short comreg = 0;
 
        comreg = c_can_read_reg_w(pchip, CCIF2CR);
-       while ((comreg & IFXCR_BUSY) && (i <= 10)) {
-               udelay(100);    //100 microseconds
+       while ((comreg & IFXCR_BUSY) && (i <= 100)) {
+               udelay(1);      //1 microseconds
                i++;
                comreg = c_can_read_reg_w(pchip, CCIF2CR);
        }
@@ -296,6 +296,11 @@ int c_can_mask(struct msgobj_t *pmsgobj, u32 mask, u16 usedirbit)
        if (c_can_if1_busycheck(pmsgobj->hostchip))
                return -ENODEV;
 
+       //set indication, that mask is used
+       tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1DMC);
+       c_can_write_reg_w(pmsgobj->hostchip, tempreg | IFXMC_UMASK,
+               CCIF1DMC);
+
        //writing acceptance mask for extended or standart mode
        if (can_msgobj_test_fl(pmsgobj, RX_MODE_EXT)) {
                if (usedirbit)
@@ -317,6 +322,7 @@ int c_can_mask(struct msgobj_t *pmsgobj, u32 mask, u16 usedirbit)
                                          ((mask << 2) & 0x1FFC), CCIF1M2);
                c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF1M1);
        }
+
        //seting Message Valid Bit to one
        tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1A2);
        c_can_write_reg_w(pmsgobj->hostchip, tempreg | IFXARB2_MVAL, CCIF1A2);
index 4ba6042..8672b4e 100644 (file)
@@ -458,6 +458,7 @@ int c_can_irq_handler(int irq, struct canchip_t *pchip)
                                if (c_can_if1_busycheck(pchip)) ;
                                if (c_can_read_reg_w(pchip, CCIF1A2) &
                                    IFXARB2_DIR) {
+                                       DEBUGMSG("c_can_irq_write_handler idxobj=%d, msgid=%d\n",idxobj,msgid);
                                        spin_unlock(&c_can_if1lock);
                                        c_can_irq_write_handler(pchip, idxobj);
 
index 2161fee..d01105c 100644 (file)
@@ -20,6 +20,9 @@
  * components/comm/contrib directory. */
 #endif
 
+#ifndef IRQF_SHARED
+#define IRQF_SHARED SA_SHIRQ
+#endif  /*IRQF_SHARED*/
 
 /**
  * can_checked_malloc - memory allocation with registering of requested blocks
@@ -223,7 +226,7 @@ int can_chip_setup_irq(struct canchip_t *chip)
                return 1;
                        
        if ((chip->flags & CHIP_IRQ_VME) == 0) {
-               if (request_irq(chip->chip_irq,can_default_irq_dispatch,SA_SHIRQ,DEVICE_NAME,chip))
+               if (request_irq(chip->chip_irq,can_default_irq_dispatch,IRQF_SHARED,DEVICE_NAME,chip))
                        return -1;
                else {
                        DEBUGMSG("Registered interrupt %d\n",chip->chip_irq);