int aim104_init_hw_data(struct candevice_t *candev);
int aim104_init_chip_data(struct candevice_t *candev, int chipnr);
int aim104_init_obj_data(struct canchip_t *chip, int objnr);
-void aim104_write_register(unsigned data, unsigned long address);
-unsigned aim104_read_register(unsigned long address);
+void aim104_write_register(unsigned data, can_ioptr_t address);
+unsigned aim104_read_register(can_ioptr_t address);
int aim104_program_irq(struct candevice_t *candev);
*/
extern inline void c_can_write_reg_w(const struct canchip_t *pchip, u16 data, unsigned reg)
{
- u32 address = pchip->chip_base_addr + reg;
+ can_ioptr_t address = pchip->chip_base_addr + reg;
#ifndef CONFIG_OC_LINCAN_DYNAMICIO
writew(data,address);
#else /*CONFIG_OC_LINCAN_DYNAMICIO*/
extern inline u16 c_can_read_reg_w(const struct canchip_t *pchip, unsigned reg)
{
- u32 address = pchip->chip_base_addr + reg;
+ can_ioptr_t address = pchip->chip_base_addr + reg;
#ifndef CONFIG_OC_LINCAN_DYNAMICIO
return readw(address);
#else /*CONFIG_OC_LINCAN_DYNAMICIO*/
#define del_timer_sync del_timer
#endif /* <2.4.0 */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9))
+ typedef unsigned long can_ioptr_t;
+ #define can_ioptr2ulong(ioaddr) ((unsigned long)(ioaddr))
+ #define can_ulong2ioptr(addr) ((unsigned long)(addr))
+ #define can_inb(ioaddr) inb(ioaddr)
+ #define can_outb(data,ioaddr) outb(data,ioaddr)
+ #define can_inw(ioaddr) inb(ioaddr)
+ #define can_outw(data,ioaddr) outb(data,ioaddr)
+ #define can_inl(ioaddr) inb(ioaddr)
+ #define can_outl(data,ioaddr) outb(data,ioaddr)
+#else /* >=2.6.9 */
+ typedef void __iomem * can_ioptr_t;
+ #define can_ioptr2ulong(ioaddr) ((unsigned long __force)(ioaddr))
+ #define can_ulong2ioptr(addr) ((can_ioptr_t)(addr))
+ #define can_inb(ioaddr) inb(can_ioptr2ulong(ioaddr))
+ #define can_outb(data,ioaddr) outb(data,can_ioptr2ulong(ioaddr))
+ #define can_inw(ioaddr) inb(can_ioptr2ulong(ioaddr))
+ #define can_outw(data,ioaddr) outb(data,can_ioptr2ulong(ioaddr))
+ #define can_inl(ioaddr) inb(can_ioptr2ulong(ioaddr))
+ #define can_outl(data,ioaddr) outb(data,can_ioptr2ulong(ioaddr))
+#endif
+
+#define can_readb readb
+#define can_writeb writeb
+#define can_readw readw
+#define can_writew writew
+#define can_readl readl
+#define can_writel writel
+
+#define can_ioport2ioptr can_ulong2ioptr
+
#ifdef __HAVE_ARCH_CMPXCHG
#define CAN_HAVE_ARCH_CMPXCHG
#endif
int cc104_init_hw_data(struct candevice_t *candev);
int cc104_init_chip_data(struct candevice_t *candev, int chipnr);
int cc104_init_obj_data(struct canchip_t *chip, int objnr);
-void cc104_write_register(unsigned data, unsigned long address);
-unsigned cc104_read_register(unsigned long address);
+void cc104_write_register(unsigned data, can_ioptr_t address);
+unsigned cc104_read_register(can_ioptr_t address);
int cc104_program_irq(struct candevice_t *candev);
int eb8245_init_chip_data(struct candevice_t *candev, int chipnr);
int eb8245_init_obj_data(struct canchip_t *chip, int objnr);
int eb8245_program_irq(struct candevice_t *candev);
-void eb8245_write_register(unsigned data, unsigned long address);
-unsigned eb8245_read_register(unsigned long address);
+void eb8245_write_register(unsigned data, can_ioptr_t address);
+unsigned eb8245_read_register(can_ioptr_t address);
int gensja1000io_init_chip_data(struct candevice_t *candev, int chipnr);
int gensja1000io_init_obj_data(struct canchip_t *chip, int objnr);
int gensja1000io_program_irq(struct candevice_t *candev);
-void gensja1000io_write_register(unsigned data, unsigned long address);
-unsigned gensja1000io_read_register(unsigned long address);
+void gensja1000io_write_register(unsigned data, can_ioptr_t address);
+unsigned gensja1000io_read_register(can_ioptr_t address);
int hms30c7202_request_io(struct candevice_t *candev);\r
int hms30c7202_release_io(struct candevice_t *candev);\r
int hms30c7202_reset( struct candevice_t *candev);\r
-void hms30c7202_write_register(unsigned data, unsigned long address);\r
-unsigned hms30c7202_read_register(unsigned long address);\r
+void hms30c7202_write_register(unsigned data, can_ioptr_t address);\r
+unsigned hms30c7202_read_register(can_ioptr_t address);\r
\r
\r
\r
* Version lincan-0.3 17 Jun 2004
*/
+#include "../include/can_sysdep.h"
#include "../include/kthread.h"
/* PCI device identification */
/* BCI queue info */
struct bci_queue_t {
- int idx; /* points to the active record in buffer */
- unsigned long addr; /* start address of the message queue */
+ int idx; /* points to the active record in buffer */
+ can_ioptr_t addr; /* start address of the message queue */
};
/* ipci165 chip data */
#ifndef _KTHREAD_H
#define _KTHREAD_H
-#include <linux/config.h>
#include <linux/version.h>
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,17))
+#include <linux/config.h>
+#endif
#include <linux/kernel.h>
#include <linux/sched.h>
int m437_init_hw_data(struct candevice_t *candev);
int m437_init_chip_data(struct candevice_t *candev, int chipnr);
int m437_init_obj_data(struct canchip_t *chip, int objnr);
-void m437_write_register(unsigned data, unsigned long address);
-unsigned m437_read_register(unsigned long address);
+void m437_write_register(unsigned data, can_ioptr_t address);
+unsigned m437_read_register(can_ioptr_t address);
int m437_program_irq(struct candevice_t *candev);
int m437_register(struct hwspecops_t *hwspecops);
int candev_idx; /* board index in canhardware_t.candevice[] */
unsigned long io_addr; /* IO/physical MEM address */
unsigned long res_addr; /* optional reset register port */
- unsigned long dev_base_addr; /* CPU translated IO/virtual MEM address */
+ can_ioptr_t dev_base_addr; /* CPU translated IO/virtual MEM address */
+ can_ioptr_t aux_base_addr; /* CPU translated IO/virtual MEM address */
unsigned int flags;
int nr_all_chips;
int nr_82527_chips;
char *chip_type;
int chip_idx; /* chip index in candevice_t.chip[] */
int chip_irq;
- unsigned long chip_base_addr;
+ can_ioptr_t chip_base_addr;
unsigned int flags;
long clock; /* Chip clock in Hz */
long baudrate;
- void (*write_register)(unsigned data,unsigned long address);
- unsigned (*read_register)(unsigned long address);
+ void (*write_register)(unsigned data, can_ioptr_t address);
+ unsigned (*read_register)(can_ioptr_t address);
void *chip_data;
* that reuse same object for TX
*/
struct msgobj_t {
- unsigned long obj_base_addr;
+ can_ioptr_t obj_base_addr;
unsigned int minor; /* associated device minor number */
unsigned int object; /* object number in canchip_t +1 for debug printk */
unsigned long obj_flags;
int (*init_chip_data)(struct candevice_t *candev, int chipnr);
int (*init_obj_data)(struct canchip_t *chip, int objnr);
int (*program_irq)(struct candevice_t *candev);
- void (*write_register)(unsigned data,unsigned long address);
- unsigned (*read_register)(unsigned long address);
+ void (*write_register)(unsigned data, can_ioptr_t address);
+ unsigned (*read_register)(can_ioptr_t address);
};
/**
#if defined(CONFIG_OC_LINCAN_PORTIO_ONLY)
-extern inline void can_write_reg(const struct canchip_t *chip, unsigned char data, unsigned address)
+extern inline void can_write_reg(const struct canchip_t *chip, unsigned char data, unsigned reg_offs)
{
- outb(data, chip->chip_base_addr+address);
+ can_outb(data, chip->chip_base_addr+reg_offs);
}
-extern inline unsigned can_read_reg(const struct canchip_t *chip, unsigned address)
+extern inline unsigned can_read_reg(const struct canchip_t *chip, unsigned reg_offs)
{
- return inb(chip->chip_base_addr+address);
+ return can_inb(chip->chip_base_addr+reg_offs);
}
extern inline void canobj_write_reg(const struct canchip_t *chip, const struct msgobj_t *obj,
- unsigned char data, unsigned address)
+ unsigned char data, unsigned reg_offs)
{
- outb(data, obj->obj_base_addr+address);
+ can_outb(data, obj->obj_base_addr+reg_offs);
}
extern inline unsigned canobj_read_reg(const struct canchip_t *chip, const struct msgobj_t *obj,
- unsigned address)
+ unsigned reg_offs)
{
- return inb(obj->obj_base_addr+address);
+ return can_inb(obj->obj_base_addr+reg_offs);
}
#elif defined(CONFIG_OC_LINCAN_MEMIO_ONLY)
-extern inline void can_write_reg(const struct canchip_t *chip, unsigned char data, unsigned address)
+extern inline void can_write_reg(const struct canchip_t *chip, unsigned char data, unsigned reg_offs)
{
- writeb(data, chip->chip_base_addr+address);
+ can_writeb(data, chip->chip_base_addr+reg_offs);
}
-extern inline unsigned can_read_reg(const struct canchip_t *chip, unsigned address)
+extern inline unsigned can_read_reg(const struct canchip_t *chip, unsigned reg_offs)
{
- return readb(chip->chip_base_addr+address);
+ return can_readb(chip->chip_base_addr+reg_offs);
}
extern inline void canobj_write_reg(const struct canchip_t *chip, const struct msgobj_t *obj,
- unsigned char data, unsigned address)
+ unsigned char data, unsigned reg_offs)
{
- writeb(data, obj->obj_base_addr+address);
+ can_writeb(data, obj->obj_base_addr+reg_offs);
}
extern inline unsigned canobj_read_reg(const struct canchip_t *chip, const struct msgobj_t *obj,
- unsigned address)
+ unsigned reg_offs)
{
- return readb(obj->obj_base_addr+address);
+ return can_readb(obj->obj_base_addr+reg_offs);
}
#else /*CONFIG_OC_LINCAN_DYNAMICIO*/
#define CONFIG_OC_LINCAN_DYNAMICIO
#endif
-/* Inline function to write to the hardware registers. The argument address is
- * relative to the memory map of the chip and not the absolute memory address.
+/* Inline function to write to the hardware registers. The argument reg_offs is
+ * relative to the memory map of the chip and not the absolute memory reg_offs.
*/
-extern inline void can_write_reg(const struct canchip_t *chip, unsigned char data, unsigned address)
+extern inline void can_write_reg(const struct canchip_t *chip, unsigned char data, unsigned reg_offs)
{
- unsigned long address_to_write;
- address_to_write = chip->chip_base_addr+address;
+ can_ioptr_t address_to_write;
+ address_to_write = chip->chip_base_addr+reg_offs;
chip->write_register(data, address_to_write);
}
-extern inline unsigned can_read_reg(const struct canchip_t *chip, unsigned address)
+extern inline unsigned can_read_reg(const struct canchip_t *chip, unsigned reg_offs)
{
- unsigned long address_to_read;
- address_to_read = chip->chip_base_addr+address;
+ can_ioptr_t address_to_read;
+ address_to_read = chip->chip_base_addr+reg_offs;
return chip->read_register(address_to_read);
}
extern inline void canobj_write_reg(const struct canchip_t *chip, const struct msgobj_t *obj,
- unsigned char data, unsigned address)
+ unsigned char data, unsigned reg_offs)
{
- unsigned long address_to_write;
- address_to_write = obj->obj_base_addr+address;
+ can_ioptr_t address_to_write;
+ address_to_write = obj->obj_base_addr+reg_offs;
chip->write_register(data, address_to_write);
}
extern inline unsigned canobj_read_reg(const struct canchip_t *chip, const struct msgobj_t *obj,
- unsigned address)
+ unsigned reg_offs)
{
- unsigned long address_to_read;
- address_to_read = obj->obj_base_addr+address;
+ can_ioptr_t address_to_read;
+ address_to_read = obj->obj_base_addr+reg_offs;
return chip->read_register(address_to_read);
}
#endif /*CONFIG_OC_LINCAN_DYNAMICIO*/
-int can_base_addr_fixup(struct candevice_t *candev, unsigned long new_base);
+int can_base_addr_fixup(struct candevice_t *candev, can_ioptr_t new_base);
int can_request_io_region(unsigned long start, unsigned long n, const char *name);
void can_release_io_region(unsigned long start, unsigned long n);
int can_request_mem_region(unsigned long start, unsigned long n, const char *name);
int msmcan_init_hw_data(struct candevice_t *candev);
int msmcan_init_chip_data(struct candevice_t *candev, int chipnr);
int msmcan_init_obj_data(struct canchip_t *chip, int objnr);
-void msmcan_write_register(unsigned data, unsigned long address);
-unsigned msmcan_read_register(unsigned long address);
+void msmcan_write_register(unsigned data, can_ioptr_t address);
+unsigned msmcan_read_register(can_ioptr_t address);
int msmcan_program_irq(struct candevice_t *candev);
int ns_dev_request_io(struct candevice_t *candev);
int ns_dev_release_io(struct candevice_t *candev);
int ns_dev_reset(struct candevice_t *candev);
-void ns_dev_write_register(unsigned data, unsigned long address);
-unsigned ns_dev_read_register(unsigned long address);
+void ns_dev_write_register(unsigned data, can_ioptr_t address);
+unsigned ns_dev_read_register(can_ioptr_t address);
int ns_dev_init_obj_data(struct canchip_t *chip, int objnr);
int ns_dev_program_irq(struct candevice_t *candev);
int nsi_init_hw_data(struct candevice_t *candev);
int nsi_init_chip_data(struct candevice_t *candev, int chipnr);
int nsi_init_obj_data(struct canchip_t *chip, int objnr);
-void nsi_write_register(unsigned data, unsigned long address);
-unsigned nsi_read_register(unsigned long address);
+void nsi_write_register(unsigned data, can_ioptr_t address);
+unsigned nsi_read_register(can_ioptr_t address);
int nsi_program_irq(struct candevice_t *candev);
int nsi_canpci_init_hw_data(struct candevice_t *candev);
int nsi_canpci_init_chip_data(struct candevice_t *candev, int chipnr);
int nsi_canpci_init_obj_data(struct canchip_t *chip, int objnr);
-void nsi_canpci_write_register(unsigned data, unsigned long address);
-unsigned nsi_canpci_read_register(unsigned long address);
+void nsi_canpci_write_register(unsigned data, can_ioptr_t address);
+unsigned nsi_canpci_read_register(can_ioptr_t address);
int nsi_canpci_program_irq(struct candevice_t *candev);
int oscar_init_hw_data(struct candevice_t *candev);
int oscar_init_chip_data(struct candevice_t *candev, int chipnr);
int oscar_init_obj_data(struct canchip_t *chip, int objnr);
-void oscar_write_register(unsigned data, unsigned long address);
-unsigned oscar_read_register(unsigned long address);
+void oscar_write_register(unsigned data, can_ioptr_t address);
+unsigned oscar_read_register(can_ioptr_t address);
int oscar_program_irq(struct candevice_t *candev);
int pci03_init_hw_data(struct candevice_t *candev);
int pci03_init_chip_data(struct candevice_t *candev, int chipnr);
int pci03_init_obj_data(struct canchip_t *chip, int objnr);
-void pci03_write_register(unsigned data, unsigned long address);
-unsigned pci03_read_register(unsigned long address);
+void pci03_write_register(unsigned data, can_ioptr_t address);
+unsigned pci03_read_register(can_ioptr_t address);
int pci03_program_irq(struct candevice_t *candev);
int pcan_dongle_init_hw_data(struct candevice_t *candev);
int pcan_dongle_init_chip_data(struct candevice_t *candev, int chipnr);
int pcan_dongle_init_obj_data(struct canchip_t *chip, int objnr);
-void pcan_dongle_write_register(unsigned data, unsigned long address);
-unsigned pcan_dongle_read_register(unsigned long address);
+void pcan_dongle_write_register(unsigned data, can_ioptr_t address);
+unsigned pcan_dongle_read_register(can_ioptr_t address);
int pcan_dongle_program_irq(struct candevice_t *candev);
#endif // __PCAN_DONGLE_H__
int pccan_init_hw_data(struct candevice_t *candev);
int pccan_init_chip_data(struct candevice_t *candev, int chipnr);
int pccan_init_obj_data(struct canchip_t *chip, int objnr);
-void pccan_write_register(unsigned data, unsigned long address);
-unsigned pccan_read_register(unsigned long address);
+void pccan_write_register(unsigned data, can_ioptr_t address);
+unsigned pccan_read_register(can_ioptr_t address);
int pccan_program_irq(struct candevice_t *candev);
int pcccan_init_hw_data(struct candevice_t *candev);
int pcccan_init_chip_data(struct candevice_t *candev, int chipnr);
int pcccan_init_obj_data(struct canchip_t *chip, int objnr);
-void pcccan_write_register(unsigned data, unsigned long address);
-unsigned pcccan_read_register(unsigned long address);
+void pcccan_write_register(unsigned data, can_ioptr_t address);
+unsigned pcccan_read_register(can_ioptr_t address);
int pcccan_program_irq(struct candevice_t *candev);
int pcm3680_init_hw_data(struct candevice_t *candev);
int pcm3680_init_chip_data(struct candevice_t *candev, int chipnr);
int pcm3680_init_obj_data(struct canchip_t *chip, int objnr);
-void pcm3680_write_register(unsigned data, unsigned long address);
-unsigned pcm3680_read_register(unsigned long address);
+void pcm3680_write_register(unsigned data, can_ioptr_t address);
+unsigned pcm3680_read_register(can_ioptr_t address);
int pcm3680_program_irq(struct candevice_t *candev);
int pikronisa_init_chip_data(struct candevice_t *candev, int chipnr);
int pikronisa_init_obj_data(struct canchip_t *chip, int objnr);
int pikronisa_program_irq(struct candevice_t *candev);
-void pikronisa_write_register(unsigned data, unsigned long address);
-unsigned pikronisa_read_register(unsigned long address);
+void pikronisa_write_register(unsigned data, can_ioptr_t address);
+unsigned pikronisa_read_register(can_ioptr_t address);
int pip_init_hw_data(struct candevice_t *candev);
int pip_init_chip_data(struct candevice_t *candev, int chipnr);
int pip_init_obj_data(struct canchip_t *chip, int objnr);
-void pip_write_register(unsigned data, unsigned long address);
-unsigned pip_read_register(unsigned long address);
+void pip_write_register(unsigned data, can_ioptr_t address);
+unsigned pip_read_register(can_ioptr_t address);
int pip_program_irq(struct candevice_t *candev);
int smartcan_init_hw_data(struct candevice_t *candev);
int smartcan_init_chip_data(struct candevice_t *candev, int chipnr);
int smartcan_init_obj_data(struct canchip_t *chip, int objnr);
-void smartcan_write_register(unsigned data, unsigned long address);
-unsigned smartcan_read_register(unsigned long address);
+void smartcan_write_register(unsigned data, can_ioptr_t address);
+unsigned smartcan_read_register(can_ioptr_t address);
int ssv_init_hw_data(struct candevice_t *candev);
int ssv_init_chip_data(struct candevice_t *candev, int chipnr);
int ssv_init_obj_data(struct canchip_t *chip, int objnr);
-void ssv_write_register(unsigned data, unsigned long address);
-unsigned ssv_read_register(unsigned long address);
+void ssv_write_register(unsigned data, can_ioptr_t address);
+unsigned ssv_read_register(can_ioptr_t address);
int ssv_program_irq(struct candevice_t *candev);
int template_init_hw_data(struct candevice_t *candev);
int template_init_chip_data(struct candevice_t *candev, int chipnr);
int template_init_obj_data(struct canchip_t *chip, int objnr);
-void template_write_register(unsigned data, unsigned long address);
-unsigned template_read_register(unsigned long address);
+void template_write_register(unsigned data, can_ioptr_t address);
+unsigned template_read_register(can_ioptr_t address);
int template_program_irq(struct candevice_t *candev);
int tscan1_init_hw_data(struct candevice_t *candev);
int tscan1_init_chip_data(struct candevice_t *candev, int chipnr);
int tscan1_init_obj_data(struct canchip_t *chip, int objnr);
-void tscan1_write_register(unsigned data, unsigned long address);
-unsigned tscan1_read_register(unsigned long address);
+void tscan1_write_register(unsigned data, can_ioptr_t address);
+unsigned tscan1_read_register(can_ioptr_t address);
int tscan1_program_irq(struct candevice_t *candev);
unsigned long tscan1_getmappedaddr(unsigned long address);
}
-void adlink7841_write_register(unsigned data, unsigned long address)
+void adlink7841_write_register(unsigned data, can_ioptr_t address)
{
- outb(data,address);
+ can_outb(data,address);
}
-unsigned adlink7841_read_register(unsigned long address)
+unsigned adlink7841_read_register(can_ioptr_t address)
{
- return inb(address);
+ return can_inb(address);
}
int adlink7841_reset(struct candevice_t *candev)
sja1000p_fill_chipspecops(candev->chip[chipnr]);
candev->chip[chipnr]->chip_base_addr=
- candev->io_addr+chipnr*ADLINK7841_BYTES_PER_CIRCUIT;
+ can_ioport2ioptr(candev->io_addr+chipnr*ADLINK7841_BYTES_PER_CIRCUIT);
candev->chip[chipnr]->flags = 0;
candev->chip[chipnr]->int_cpu_reg = 0;
candev->chip[chipnr]->int_clk_reg = 0;
int aim104_init_chip_data(struct candevice_t *candev, int chipnr)
{
sja1000_fill_chipspecops(candev->chip[chipnr]);
- candev->chip[chipnr]->chip_base_addr=candev->io_addr;
+ candev->chip[chipnr]->chip_base_addr=can_ioport2ioptr(candev->io_addr);
candev->chip[chipnr]->clock = 16000000;
candev->chip[chipnr]->flags = 0;
candev->chip[chipnr]->sja_cdr_reg = 0x08;
* Return Value: The function does not return a value
* File: src/template.c
*/
-void aim104_write_register(unsigned data, unsigned long address)
+void aim104_write_register(unsigned data, can_ioptr_t address)
{
- outb(data,address);
+ can_outb(data,address);
}
/**
* Return Value: The function returns the value stored in @address
* File: src/template.c
*/
-unsigned aim104_read_register(unsigned long address)
+unsigned aim104_read_register(can_ioptr_t address)
{
- return inb(address);
+ return can_inb(address);
}
/* !!! Don't change this function !!! */
#define IO_RANGE 0x100
#endif
-unsigned bfadcan_read_register(unsigned long address);
-void bfadcan_write_register(unsigned data, unsigned long address);
+unsigned bfadcan_read_register(can_ioptr_t address);
+void bfadcan_write_register(unsigned data, can_ioptr_t address);
/**
{
unsigned int id1, id2;
sja1000p_fill_chipspecops(candev->chip[chipnr]);
- candev->chip[chipnr]->chip_base_addr=candev->io_addr;
+ candev->chip[chipnr]->chip_base_addr=can_ioport2ioptr(candev->io_addr);
if(candev->chip[chipnr]->clock<=0)
candev->chip[chipnr]->clock = CAN_BFAD_CLOCKFREQ;
candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CBP | sjaCDR_CLK_OFF;
candev->chip[chipnr]->sja_ocr_reg = sjaOCR_MODE_NORMAL | sjaOCR_TX0_LH;
- id1 = inb(0xe284);
- id2 = inb(0xe285);
+ id1 = can_inb(0xe284);
+ id2 = can_inb(0xe285);
CANMSG("can driver ver lincan-0.3, at %04lx, CPLD v%d.%d.%d.%d\n",
- candev->chip[chipnr]->chip_base_addr,
- id1>>4, id1&0x0f, id2>>4, id2&0x0f);
+ can_ioptr2ulong(candev->chip[chipnr]->chip_base_addr),
+ id1>>4, id1&0x0f, id2>>4, id2&0x0f);
return 0;
* Return Value: The function does not return a value
* File: src/bfadcan.c
*/
-void bfadcan_write_register(unsigned data, unsigned long address)
+void bfadcan_write_register(unsigned data, can_ioptr_t address)
{
#ifdef WINDOWED_ACCESS
can_spin_irqflags_t flags;
can_spin_lock_irqsave(&bfadcan_win_lock,flags);
- outb(address&0x00ff,0x200);
- outb(data, 0x201);
+ can_outb(can_ioptr2ulong(address)&0x00ff,0x200);
+ can_outb(data, 0x201);
can_spin_unlock_irqrestore(&bfadcan_win_lock,flags);
#else
- outb(data,address);
+ can_outb(data,address);
#endif
}
* Return Value: The function returns the value stored in @address
* File: src/bfadcan.c
*/
-unsigned bfadcan_read_register(unsigned long address)
+unsigned bfadcan_read_register(can_ioptr_t address)
{
#ifdef WINDOWED_ACCESS
can_spin_irqflags_t flags;
int ret;
can_spin_lock_irqsave(&bfadcan_win_lock,flags);
- outb(address&0x00ff,0x200);
- ret = inb(0x201);
+ can_outb(can_ioptr2ulong(address)&0x00ff,0x200);
+ ret = can_inb(0x201);
can_spin_unlock_irqrestore(&bfadcan_win_lock,flags);
return ret;
#else
- return inb(address);
+ return can_inb(address);
#endif
}
int cc104_init_chip_data(struct candevice_t *candev, int chipnr)
{
sja1000_fill_chipspecops(candev->chip[chipnr]);
- candev->chip[chipnr]->chip_base_addr=candev->io_addr;
+ candev->chip[chipnr]->chip_base_addr=can_ioport2ioptr(candev->io_addr);
candev->chip[chipnr]->clock = 16000000;
candev->chip[chipnr]->flags = 0;
candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CBP | sjaCDR_CLK_OFF;
* Return Value: The function does not return a value
* File: src/template.c
*/
-void cc104_write_register(unsigned data, unsigned long address)
+void cc104_write_register(unsigned data, can_ioptr_t address)
{
- outb(data,address);
+ can_outb(data,address);
}
/**
* Return Value: The function returns the value stored in @address
* File: src/template.c
*/
-unsigned cc104_read_register(unsigned long address)
+unsigned cc104_read_register(can_ioptr_t address)
{
- return inb(address);
+ return can_inb(address);
}
/* !!! Don't change this function !!! */
*/
int eb8245_request_io(struct candevice_t *candev)
{
- int remap_addr;
+ can_ioptr_t remap_addr;
if (!can_request_mem_region(candev->io_addr,IO_RANGE,DEVICE_NAME " - eb8245")) {
CANMSG("Unable to request IO-memory: 0x%lx\n",candev->io_addr);
return -ENODEV;
}
- if ( !( remap_addr = (long) ioremap( candev->io_addr, IO_RANGE ) ) ) {
+ if ( !( remap_addr = ioremap( candev->io_addr, IO_RANGE ) ) ) {
CANMSG("Unable to access I/O memory at: 0x%lx\n", candev->io_addr);
can_release_mem_region(candev->io_addr,IO_RANGE);
return -ENODEV;
* Return Value: The function does not return a value
* File: src/eb8245.c
*/
-void eb8245_write_register(unsigned data, unsigned long address)
+void eb8245_write_register(unsigned data, can_ioptr_t address)
{
/*DEBUGMSG("eb8245_write_register: addr=0x%lx data=0x%x",
address,data);*/
- writeb(data,address);
+ can_writeb(data,address);
}
/**
* Return Value: The function returns the value stored in @address
* File: src/eb8245.c
*/
-unsigned eb8245_read_register(unsigned long address)
+unsigned eb8245_read_register(can_ioptr_t address)
{
- return readb(address);
+ return can_readb(address);
}
/* !!! Don't change this function !!! */
void ems_cpcpci_disconnect_irq(struct candevice_t *candev)
{
/* Disable interrupts from card */
- writel(0, candev->dev_base_addr + PITA2_ICR);
+ can_writel(0, candev->aux_base_addr + PITA2_ICR);
}
void ems_cpcpci_connect_irq(struct candevice_t *candev)
{
/* Enable interrupts from card */
- writel(PITA2_ICR_INT0_En, candev->dev_base_addr + PITA2_ICR);
+ can_writel(PITA2_ICR_INT0_En, candev->aux_base_addr + PITA2_ICR);
}
#endif /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
pita2_addr=pci_resource_start(candev->sysdevptr.pcidev,0);
- if (!(candev->dev_base_addr = (long) ioremap(pita2_addr,
+ if (!(candev->aux_base_addr = ioremap(pita2_addr,
pci_resource_len(candev->sysdevptr.pcidev,0)))) {
CANMSG("Unable to access I/O memory at: 0x%lx\n", pita2_addr);
goto error_ioremap_pita2;
}
io_addr=pci_resource_start(candev->sysdevptr.pcidev,1);;
- if (!(candev->io_addr = (long) ioremap(io_addr,
+ if (!(candev->dev_base_addr = ioremap(io_addr,
pci_resource_len(candev->sysdevptr.pcidev,1)))) {
CANMSG("Unable to access I/O memory at: 0x%lx\n", io_addr);
goto error_ioremap_io;
}
- candev->res_addr=candev->io_addr;
+ candev->io_addr=io_addr;
+ candev->res_addr=pita2_addr;
/*
* this is redundant with chip initialization, but remap address
for(i=0;i<candev->nr_all_chips;i++) {
struct canchip_t *chip=candev->chip[i];
if(!chip) continue;
- chip->chip_base_addr = candev->io_addr+
+ chip->chip_base_addr = candev->dev_base_addr+
0x400 + i*EMS_CPCPCI_BYTES_PER_CIRCUIT;
if(!chip->msgobj[0]) continue;
chip->msgobj[0]->obj_base_addr=chip->chip_base_addr;
}
/* Configure PITA-2 parallel interface */
- writel(PITA2_MISC_CONFIG, candev->dev_base_addr + PITA2_MISC);
+ can_writel(PITA2_MISC_CONFIG, candev->aux_base_addr + PITA2_MISC);
ems_cpcpci_disconnect_irq(candev);
return 0;
error_ioremap_io:
- iounmap((void*)candev->dev_base_addr);
+ iounmap(candev->aux_base_addr);
error_ioremap_pita2:
#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))
pci_release_region(candev->sysdevptr.pcidev, 1);
{
ems_cpcpci_disconnect_irq(candev);
- iounmap((void*)candev->io_addr);
- iounmap((void*)candev->dev_base_addr);
+ iounmap(candev->dev_base_addr);
+ iounmap(candev->aux_base_addr);
#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))
pci_release_region(candev->sysdevptr.pcidev, 1);
pci_release_region(candev->sysdevptr.pcidev, 0);
}
-void ems_cpcpci_write_register(unsigned data, unsigned long address)
+void ems_cpcpci_write_register(unsigned data, can_ioptr_t address)
{
- address += ((address&(EMS_CPCPCI_BYTES_PER_CIRCUIT-1))
- *(EMS_CPCPCI_BYTES_PER_REG-1));
- writeb(data,address);
+ address += ((can_ioptr2ulong(address)&(EMS_CPCPCI_BYTES_PER_CIRCUIT-1))
+ *(EMS_CPCPCI_BYTES_PER_REG-1));
+ can_writeb(data,address);
}
-unsigned ems_cpcpci_read_register(unsigned long address)
+unsigned ems_cpcpci_read_register(can_ioptr_t address)
{
- address += ((address&(EMS_CPCPCI_BYTES_PER_CIRCUIT-1))
- *(EMS_CPCPCI_BYTES_PER_REG-1));
- return readb(address);
+ address += ((can_ioptr2ulong(address)&(EMS_CPCPCI_BYTES_PER_CIRCUIT-1))
+ *(EMS_CPCPCI_BYTES_PER_REG-1));
+ return can_readb(address);
}
int ems_cpcpci_irq_handler(int irq, struct canchip_t *chip)
unsigned long icr;
int test_irq_again;
- icr=readl(candev->dev_base_addr + PITA2_ICR);
+ icr=can_readl(candev->aux_base_addr + PITA2_ICR);
if(!(icr & PITA2_ICR_INT0)) return CANCHIP_IRQ_NONE;
/* correct way to handle interrupts from all chips connected to the one PITA-2 */
do {
- writel(PITA2_ICR_INT0_En | PITA2_ICR_INT0, candev->dev_base_addr + PITA2_ICR);
+ can_writel(PITA2_ICR_INT0_En | PITA2_ICR_INT0, candev->aux_base_addr + PITA2_ICR);
test_irq_again=0;
for(i=0;i<candev->nr_all_chips;i++){
chip=candev->chip[i];
if(sja1000p_irq_handler(irq, chip))
test_irq_again=1;
}
- icr=readl(candev->dev_base_addr + PITA2_ICR);
+ icr=can_readl(candev->aux_base_addr + PITA2_ICR);
} while((icr & PITA2_ICR_INT0)||test_irq_again);
return CANCHIP_IRQ_HANDLED;
}
if(ems_cpcpci_request_io(candev)<0)
return -ENODEV;
- /*** candev->dev_base_addr=pci_resource_start(pcidev,0); ***/
+ /*** candev->aux_base_addr=pci_resource_start(pcidev,0); ***/
/* some control registers */
- /*** candev->io_addr=pci_resource_start(pcidev,1); ***/
+ /*** candev->dev_base_addr=pci_resource_start(pcidev,1); ***/
/* 0 more EMS control registers
* 0x400 the first SJA1000
* 0x600 the second SJA1000
for(l=0,i=0;i<4;i++){
l<<=8;
- l|=readb(candev->io_addr + i*4);
+ l|=can_readb(candev->dev_base_addr + i*4);
}
- i=readb(candev->io_addr + i*5);
+ i=can_readb(candev->dev_base_addr + i*5);
CANMSG("EMS CPC-PCI check value %04lx, ID %d\n", l, i);
candev->chip[chipnr]->chip_irq=candev->sysdevptr.pcidev->irq;
- candev->chip[chipnr]->chip_base_addr = candev->io_addr+
+ candev->chip[chipnr]->chip_base_addr = candev->dev_base_addr+
0x400 + chipnr*EMS_CPCPCI_BYTES_PER_CIRCUIT;
candev->chip[chipnr]->flags = 0;
candev->chip[chipnr]->int_cpu_reg = 0;
/*sja1000_fill_chipspecops(candev->chip[chipnr]);*/
sja1000p_fill_chipspecops(candev->chip[chipnr]);
- candev->chip[chipnr]->chip_base_addr=candev->io_addr;
+ candev->chip[chipnr]->chip_base_addr=can_ioport2ioptr(candev->io_addr);
if(candev->chip[chipnr]->clock<=0)
candev->chip[chipnr]->clock = 16000000;
candev->chip[chipnr]->int_clk_reg = 0x0;
* Return Value: The function does not return a value
* File: src/gensja1000io.c
*/
-void gensja1000io_write_register(unsigned data, unsigned long address)
+void gensja1000io_write_register(unsigned data, can_ioptr_t address)
{
/*DEBUGMSG("gensja1000io_write_register: addr=0x%lx data=0x%x",
address,data);*/
- outb(data,address);
+ can_outb(data,address);
}
/**
* Return Value: The function returns the value stored in @address
* File: src/gensja1000io.c
*/
-unsigned gensja1000io_read_register(unsigned long address)
+unsigned gensja1000io_read_register(can_ioptr_t address)
{
- return inb(address);
+ return can_inb(address);
}
/* !!! Don't change this function !!! */
(unsigned long)candev->io_addr );
}
- if (!( candev->dev_base_addr = (long)ioremap( candev->io_addr, IO_RANGE ))) {
+ if (!( candev->dev_base_addr = ioremap( candev->io_addr, IO_RANGE ))) {
DEBUGMSG( "Failed to map IO-memory: 0x%lx - 0x%lx, mapped to 0x%lx\n",
(unsigned long)candev->io_addr,
(unsigned long)candev->io_addr + IO_RANGE - 1,
candev->chip[0]->chipspecops->stop_chip(candev->chip[0]);
// release I/O memory mapping
- iounmap((void*)candev->dev_base_addr);
+ iounmap(candev->dev_base_addr);
// Release the memory region
can_release_mem_region(candev->io_addr, IO_RANGE);
/*( struct canchip_t *pchip, u16 chip_nr, u16 startminor, u32 baseaddr, u8 irq )*/
{
// u32 intCntrVAddr = 0;
- u32 gpioVAddr = 0;
+ can_ioptr_t gpioVAddr = 0;
u32 tempReg = 0;
u32 baseaddr=candev->io_addr;
- // if ( (!( intCntrVAddr = (u32)ioremap( 0x80024000, 0xCD ) ))
- // & (! ( gpioVAddr = (u32)ioremap( 0x80023000, 0xAD ) ))) {
+ // if ( (!( intCntrVAddr = ioremap( 0x80024000, 0xCD ) ))
+ // & (! ( gpioVAddr = ioremap( 0x80023000, 0xAD ) ))) {
// DEBUGMSG("Failed to map Int and GPIO memory\n");
// return -EIO;
// }
- if ( ! ( gpioVAddr = (u32)ioremap( 0x80023000, 0xAD ) )) {
+ if ( ! ( gpioVAddr = ioremap( 0x80023000, 0xAD ) )) {
DEBUGMSG("Failed to map GPIO memory\n");
return -EIO;
} else {
}
if (baseaddr == 0x8002f000) {
- // tempReg = readl(intCntrVAddr);
+ // tempReg = can_readl(intCntrVAddr);
// DEBUGMSG("Read Interrupt Enable Register : 0x%.4lx\n",(long)tempReg);
// DEBUGMSG("Trying to activate CAN0 Interrupt (Bit 18)\n");
- // writel((tempReg | (1<<18)), intCntrVAddr);
- // tempReg = readl(intCntrVAddr);
+ // can_writel((tempReg | (1<<18)), intCntrVAddr);
+ // tempReg = can_readl(intCntrVAddr);
// DEBUGMSG("Read changed Interrupt Enable Register : 0x%.4lx\n",(long)tempReg);
- tempReg = readl(gpioVAddr + 0x5C);
+ tempReg = can_readl(gpioVAddr + 0x5C);
DEBUGMSG("Read GPIO-C Enable Register : 0x%.4lx\n",(long)tempReg);
DEBUGMSG("Trying to activate CAN0 (Bit 1 = 0 for CANTx0, Bit 2 = 0 for CANRx0,)\n");
- writel(tempReg & ~0x6, gpioVAddr + 0x5C);
- tempReg = readl(gpioVAddr + 0x5C);
+ can_writel(tempReg & ~0x6, gpioVAddr + 0x5C);
+ tempReg = can_readl(gpioVAddr + 0x5C);
DEBUGMSG("Read changed GPIO-C Enable Register : 0x%.4lx\n",(long)tempReg);
- tempReg = readl(gpioVAddr + 0x44);
+ tempReg = can_readl(gpioVAddr + 0x44);
DEBUGMSG("Read GPIO-C Direction Register : 0x%.4lx\n",(long)tempReg);
DEBUGMSG("Trying to set CAN0 directions (Bit 1 = 0 for CANTx0 as OUT, Bit 2 = 1 for CANRx0 as IN,)\n");
- writel((tempReg & ~0x2) | 0x4, gpioVAddr + 0x44);
- tempReg = readl(gpioVAddr + 0x44);
+ can_writel((tempReg & ~0x2) | 0x4, gpioVAddr + 0x44);
+ tempReg = can_readl(gpioVAddr + 0x44);
DEBUGMSG("Read changed GPIO-C Direction Register : 0x%.4lx\n",(long)tempReg);
}
else if (baseaddr == 0x80030000) {
- // tempReg = readl(intCntrVAddr);
- // writel((tempReg | (1<<19)), intCntrVAddr);
- tempReg = readl(gpioVAddr + 0x9C);
+ // tempReg = can_readl(intCntrVAddr);
+ // can_writel((tempReg | (1<<19)), intCntrVAddr);
+ tempReg = can_readl(gpioVAddr + 0x9C);
DEBUGMSG("Read GPIO-E Enable Register : 0x%.8lx\n",(long)tempReg);
DEBUGMSG("Trying to activate CAN1 (Bit 22 = 0 for CANRx1, Bit 23 = 0 for CANTx1,)\n");
- writel(tempReg & 0xFF3FFFFF, gpioVAddr + 0x9C);
- tempReg = readl(gpioVAddr + 0x9C);
+ can_writel(tempReg & 0xFF3FFFFF, gpioVAddr + 0x9C);
+ tempReg = can_readl(gpioVAddr + 0x9C);
DEBUGMSG("Read changed GPIO-E Enable Register : 0x%.8lx\n",(long)tempReg);
- tempReg = readl(gpioVAddr + 0x84);
+ tempReg = can_readl(gpioVAddr + 0x84);
DEBUGMSG("Read GPIO-E Direction Register : 0x%.8lx\n",(long)tempReg);
DEBUGMSG("Trying to set CAN1 directions (Bit 22 = 1 for CANRx1 as IN, Bit 23 = 0 for CANTx1 as OUT,)\n");
- writel((tempReg & ~(1<<23)) | 1<<22, gpioVAddr + 0x84);
- tempReg = readl(gpioVAddr + 0x84);
+ can_writel((tempReg & ~(1<<23)) | 1<<22, gpioVAddr + 0x84);
+ tempReg = can_readl(gpioVAddr + 0x84);
DEBUGMSG("Read changed GPIO-E Direction Register : 0x%.8lx\n",(long)tempReg);
}
//DEBUGMSG("Current Interrupt Status Register (ISR): 0x%4.4lx\n",
- // (long)readl(intCntrVAddr + 4));
+ // (long)can_readl(intCntrVAddr + 4));
//DEBUGMSG("Current Interrupt ID: %d\n",
- // (int)(readl(intCntrVAddr + 0x90) & 0xF));
+ // (int)(can_readl(intCntrVAddr + 0x90) & 0xF));
// iounmap( (void*)intCntrVAddr);
- iounmap( (void*)gpioVAddr );
+ iounmap( gpioVAddr );
// DEBUGMSG( "Unmapped Interrupt Controller IO-memory: 0x%lx\n",
// (unsigned long)intCntrVAddr);
DEBUGMSG( "Unmapped GPIO IO-memory: 0x%lx\n",
* File: src/template.c
*/
-void hms30c7202_write_register(unsigned data, unsigned long address)
+void hms30c7202_write_register(unsigned data, can_ioptr_t address)
{
+ unsigned long addr=can_ioptr2ulong(address);
int i;
//unsigned long usecs = 1;
- address = ((address & C_CAN_REGOFFS_MASK) << 1) |
- (address & ~C_CAN_REGOFFS_MASK);
+ address = can_ulong2ioptr(((addr & C_CAN_REGOFFS_MASK) << 1) |
+ (addr & ~C_CAN_REGOFFS_MASK));
//DEBUGMSG("Trying to write 0x%u16x to address 0x%lx\n",data,address);
- writew(data,address);
+ can_writew(data,address);
//udelay( usecs );
for (i=0; i<5; i++);
}
* Return Value: The function returns the value stored in @address
* File: src/template.c
*/
-unsigned hms30c7202_read_register(unsigned long address)
+unsigned hms30c7202_read_register(can_ioptr_t address)
{
+ unsigned long addr=can_ioptr2ulong(address);
u16 value, i;
- address = ((address & C_CAN_REGOFFS_MASK) << 1) |
- (address & ~C_CAN_REGOFFS_MASK);
+ address = can_ulong2ioptr(((addr & C_CAN_REGOFFS_MASK) << 1) |
+ (addr & ~C_CAN_REGOFFS_MASK));
//DEBUGMSG("Trying to read from address 0x%lx :",address);
- value = readw(address);
+ value = can_readw(address);
//udelay( usecs );
for (i=0;i<5;i++);
- value = readw(address);
+ value = can_readw(address);
//udelay( usecs );
for (i=0;i<5;i++);
i82527_pre_read_config(chip, obj);
- CANMSG("i82527_irq_update_filter: obj at 0x%08lx\n",obj->obj_base_addr);
+ CANMSG("i82527_irq_update_filter: obj at 0x%08lx\n",
+ can_ioptr2ulong(obj->obj_base_addr));
}
}
*/
void ipci165_generate_irq(struct candevice_t *candev)
{
- unsigned long crm_addr = candev->io_addr;
- writeb(readb(crm_addr + CRM_UCR) & 0xFB, crm_addr + CRM_UCR);
- writeb(readb(crm_addr + CRM_UCR) | 0x04, crm_addr + CRM_UCR);
+ can_ioptr_t crm_addr = candev->aux_base_addr;
+ can_writeb(can_readb(crm_addr + CRM_UCR) & 0xFB, crm_addr + CRM_UCR);
+ can_writeb(can_readb(crm_addr + CRM_UCR) | 0x04, crm_addr + CRM_UCR);
}
/**
*/
int bci_command(struct candevice_t *candev, char cmd, int size, char *data)
{
- unsigned long dpram_addr = candev->dev_base_addr;
+ can_ioptr_t dpram_addr = candev->dev_base_addr;
DEBUGMSG ("ipci165_bci_command\n");
can_spin_lock(&candev->device_lock);
// check command buffer status
- if (readb(dpram_addr + OF_BCI_SYNC) != 0)
+ if (can_readb(dpram_addr + OF_BCI_SYNC) != 0)
{
/* something went wrong ... */
can_spin_unlock(&candev->device_lock);
}
// prepare command
- writeb(cmd, dpram_addr + OF_BCI_CMD);
- writeb(size + 1, dpram_addr + OF_BCI_NUM);
+ can_writeb(cmd, dpram_addr + OF_BCI_CMD);
+ can_writeb(size + 1, dpram_addr + OF_BCI_NUM);
memcpy_toio(dpram_addr + OF_BCI_DATA, data, size);
// set flag for firmware
- writeb(1, dpram_addr + OF_BCI_SYNC);
+ can_writeb(1, dpram_addr + OF_BCI_SYNC);
// generate interrupt to microcontroller
ipci165_generate_irq (candev);
*/
int bci_response(struct candevice_t *candev, char cmd, int *size, char *data)
{
- unsigned long dpram_addr = candev->dev_base_addr;
+ can_ioptr_t dpram_addr = candev->dev_base_addr;
char tmp;
int delay;
DEBUGMSG ("ipci165_bci_response\n");
delay = 1000;
- while (readb(dpram_addr + OF_BCI_SYNC) != 2)
+ while (can_readb(dpram_addr + OF_BCI_SYNC) != 2)
{
/* wait 1 ms */
/* ipci165_delay(1); */
}
/* we will not copy the command filed, so decrement the size by 1 */
- tmp = readb(dpram_addr + OF_BCI_NUM) - 1;
+ tmp = can_readb(dpram_addr + OF_BCI_NUM) - 1;
if (*size > tmp) *size = tmp;
- if (readb(dpram_addr + OF_BCI_CMD) != cmd)
+ if (can_readb(dpram_addr + OF_BCI_CMD) != cmd)
{
/* release the buffer */
- writeb(0, dpram_addr + OF_BCI_SYNC);
+ can_writeb(0, dpram_addr + OF_BCI_SYNC);
/* unlock the access */
can_spin_unlock(&candev->device_lock);
memcpy_fromio(data, dpram_addr + OF_BCI_DATA, *size);
/* release the buffer */
- writeb(0, dpram_addr + OF_BCI_SYNC);
+ can_writeb(0, dpram_addr + OF_BCI_SYNC);
/* unlock the access */
can_spin_unlock(&candev->device_lock);
return 0;
for (i = 0; i< BCI_QUEUE_SIZE; i++)
{
- writeb(BCI_MSG_STATUS_FREE, chip_data->rx_queue.addr + msg_ofs);
- writeb(BCI_MSG_STATUS_FREE, chip_data->tx_queue.addr + msg_ofs);
+ can_writeb(BCI_MSG_STATUS_FREE, chip_data->rx_queue.addr + msg_ofs);
+ can_writeb(BCI_MSG_STATUS_FREE, chip_data->tx_queue.addr + msg_ofs);
msg_ofs += BCI_MSG_SIZE;
}
*/
int ipci165_connect_irq(struct candevice_t *candev)
{
- unsigned long crm_addr = candev->io_addr;
+ can_ioptr_t crm_addr = candev->aux_base_addr;
unsigned char icr;
DEBUGMSG ("ipci165_connect_irq\n");
return -ENODEV;
// Enable interrupt to PC
- writeb(readb(crm_addr + CRM_ICR) | 0x40, crm_addr + CRM_ICR);
+ can_writeb(can_readb(crm_addr + CRM_ICR) | 0x40, crm_addr + CRM_ICR);
udelay (100);
- icr = readb(crm_addr + CRM_ICR);
+ icr = can_readb(crm_addr + CRM_ICR);
return 0;
}
*/
void ipci165_disconnect_irq(struct candevice_t *candev)
{
- unsigned long crm_addr = candev->io_addr;
+ can_ioptr_t crm_addr = candev->aux_base_addr;
unsigned char icr;
DEBUGMSG ("ipci165_disconnect_irq\n");
// Enable interrupt to PC
- writeb(readb(crm_addr + CRM_ICR) & ~0x40, crm_addr + CRM_ICR);
+ can_writeb(can_readb(crm_addr + CRM_ICR) & ~0x40, crm_addr + CRM_ICR);
udelay (100);
- icr = readb(crm_addr + CRM_ICR);
+ icr = can_readb(crm_addr + CRM_ICR);
/* deinstall interrupt routine */
free_irq(candev->sysdevptr.pcidev->irq, candev);
}
{
struct ipci165_chip_t *chip_data = (struct ipci165_chip_t *)chip->chip_data;
struct bci_queue_t *queue = &(chip_data)->rx_queue;
- unsigned long queue_addr = queue->addr;
- unsigned long msg_addr = queue_addr + queue->idx * BCI_MSG_SIZE;
+ can_ioptr_t queue_addr = queue->addr;
+ can_ioptr_t msg_addr = queue_addr + queue->idx * BCI_MSG_SIZE;
int len;
unsigned char frame_info;
do {
dump_mem(msg_addr, BCI_MSG_SIZE);
- if (readb(msg_addr + BCI_MSG_TYPE) == BCI_MSG_TYPE_CAN)
+ if (can_readb(msg_addr + BCI_MSG_TYPE) == BCI_MSG_TYPE_CAN)
{
#if 0
- printk("ST(0)=%x, ST(1)=%x\n",readw(chip->chip_base_addr+OF_CAN1_STATUS),
- readw(chip->chip_base_addr+OF_CAN2_STATUS));
+ printk("ST(0)=%x, ST(1)=%x\n",can_readw(chip->chip_base_addr+OF_CAN1_STATUS),
+ can_readw(chip->chip_base_addr+OF_CAN2_STATUS));
for (tmp16 = 0 ; tmp16 < BCI_QUEUE_SIZE ; tmp16 ++)
- printk ("MSG_ST(%i)=%x\n",tmp16,readb(chip->chip_base_addr + OF_CH2_TX_QUEUE + tmp16*BCI_MSG_SIZE + BCI_MSG_STATUS));
+ printk ("MSG_ST(%i)=%x\n",tmp16,can_readb(chip->chip_base_addr + OF_CH2_TX_QUEUE + tmp16*BCI_MSG_SIZE + BCI_MSG_STATUS));
/* this is a can message */
DEBUGMSG ("ipci165_irq_read_handler[%i]: message in buffer\n",chip->chip_idx);
#endif
- frame_info = readb(msg_addr + BCI_MSG_FRAME);
+ frame_info = can_readb(msg_addr + BCI_MSG_FRAME);
len = frame_info & 0x0f;
if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
obj->rx_msg.length = len;
obj->rx_msg.cob = 0;
obj->rx_msg.timestamp.tv_sec = 0;
obj->rx_msg.timestamp.tv_usec =
- BCI_TIMESTAMP_RES * readl(msg_addr + BCI_MSG_TIMESTAMP);
- /* BCI_TIMESTAMP_RES * le32_to_cpu(readl(msg_addr + BCI_MSG_TIMESTAMP)); */
+ BCI_TIMESTAMP_RES * can_readl(msg_addr + BCI_MSG_TIMESTAMP);
+ /* BCI_TIMESTAMP_RES * le32_to_cpu(can_readl(msg_addr + BCI_MSG_TIMESTAMP)); */
/* fill CAN message timestamp */
/* can_filltimestamp(&obj->rx_msg.timestamp); */
/* extended frame - 29 bit identifier */
obj->rx_msg.flags |= MSG_EXT;
/* the ID is stored in motorola format (big endian), left justified */
- /* obj->rx_msg.id = be32_to_cpu(readl(msg_addr + BCI_MSG_ID) >> 3); */
+ /* obj->rx_msg.id = be32_to_cpu(can_readl(msg_addr + BCI_MSG_ID) >> 3); */
memcpy_fromio(&tmp32, msg_addr + BCI_MSG_ID, 4);
obj->rx_msg.id = be32_to_cpu(tmp32 >> 3);
if (len > 0)
{
/* standard frame - 11 bit identifier */
/* the ID is stored in motorola format (big endian), left justified */
- /* obj->rx_msg.id = be16_to_cpu(readw(msg_addr + BCI_MSG_ID) >> 5); */
+ /* obj->rx_msg.id = be16_to_cpu(can_readw(msg_addr + BCI_MSG_ID) >> 5); */
memcpy_fromio(&tmp16, msg_addr + BCI_MSG_ID, 2);
obj->rx_msg.id = be16_to_cpu(tmp16 >> 5);
if (len > 0)
else
{
/* this is a status message */
- status = readw(msg_addr + BCI_MSG_CAN_STATUS);
+ status = can_readw(msg_addr + BCI_MSG_CAN_STATUS);
DEBUGMSG ("ipci165_irq_read_handler[%i]: CAN status=%04x\n",chip->chip_idx, status);
/* wake up the reset thread if the CAN is in bus off */
/* update pointer */
queue->idx = (queue->idx + 1) % BCI_QUEUE_SIZE;
/* release the buffer */
- writeb(BCI_MSG_STATUS_FREE, msg_addr + BCI_MSG_STATUS);
+ can_writeb(BCI_MSG_STATUS_FREE, msg_addr + BCI_MSG_STATUS);
msg_addr = queue_addr + queue->idx * BCI_MSG_SIZE;
- } while (readb(msg_addr + BCI_MSG_STATUS) == BCI_MSG_STATUS_FULL);
+ } while (can_readb(msg_addr + BCI_MSG_STATUS) == BCI_MSG_STATUS_FULL);
}
{
struct ipci165_chip_t *chip_data = ((struct ipci165_chip_t *)chip->chip_data);
struct bci_queue_t *queue = &chip_data->tx_queue;
- unsigned long queue_addr = queue->addr;
- unsigned long msg_addr = queue_addr + queue->idx * BCI_MSG_SIZE;
+ can_ioptr_t queue_addr = queue->addr;
+ can_ioptr_t msg_addr = queue_addr + queue->idx * BCI_MSG_SIZE;
struct canque_slot_t *tx_slot;
int len;
while ((canque_test_outslot(obj->qends, &obj->tx_qedge, &obj->tx_slot) >=0))
{
if (test_bit(CHIP_FLAG_RESET,&chip_data->flags) ||
- (readb(msg_addr + BCI_MSG_STATUS) == BCI_MSG_STATUS_FULL))
+ (can_readb(msg_addr + BCI_MSG_STATUS) == BCI_MSG_STATUS_FULL))
{
canque_again_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
((tx_slot->msg.flags & MSG_RTR) ? BCI_MSG_FRAME_RTR : 0) |
((tx_slot->msg.flags & MSG_EXT) ? BCI_MSG_FRAME_EXT : 0);
- writeb(BCI_MSG_SIZE - 2, msg_addr + BCI_MSG_NUM);
- writeb(BCI_MSG_TYPE_CAN, msg_addr + BCI_MSG_TYPE);
- writeb(frame_info, msg_addr + BCI_MSG_FRAME);
+ can_writeb(BCI_MSG_SIZE - 2, msg_addr + BCI_MSG_NUM);
+ can_writeb(BCI_MSG_TYPE_CAN, msg_addr + BCI_MSG_TYPE);
+ can_writeb(frame_info, msg_addr + BCI_MSG_FRAME);
if (frame_info & BCI_MSG_FRAME_EXT)
{
/* extended frame - 29 bit identifier */
/* update pointer */
queue->idx = (queue->idx + 1) % BCI_QUEUE_SIZE;
/* mark the buffer as full */
- writeb(BCI_MSG_STATUS_FULL, msg_addr + BCI_MSG_STATUS);
+ can_writeb(BCI_MSG_STATUS_FULL, msg_addr + BCI_MSG_STATUS);
/* wake up the controller */
ipci165_generate_irq(chip->hostdevice);
/* check receive queue for messages */
queue = &chip_data->rx_queue;
- if (readb(queue->addr + queue->idx * BCI_MSG_SIZE + BCI_MSG_STATUS)
+ if (can_readb(queue->addr + queue->idx * BCI_MSG_SIZE + BCI_MSG_STATUS)
== BCI_MSG_STATUS_FULL)
ipci165_irq_read_handler(chip, obj);
queue = &chip_data->tx_queue;
-/* if (readb(queue->addr + queue->idx * BCI_MSG_SIZE + BCI_MSG_STATUS)
+/* if (can_readb(queue->addr + queue->idx * BCI_MSG_SIZE + BCI_MSG_STATUS)
== BCI_MSG_STATUS_FREE) */
{
can_msgobj_set_fl(obj,TX_REQUEST);
int retval;
struct candevice_t *candev = (struct candevice_t *)dev_id;
- unsigned long crm_addr = candev->io_addr;
- unsigned long ucr1_addr = crm_addr + CRM_UCR + 1;
+ can_ioptr_t crm_addr = candev->aux_base_addr;
+ can_ioptr_t ucr1_addr = crm_addr + CRM_UCR + 1;
struct canchip_t *chip;
unsigned char icr;
int i;
/* DEBUGMSG ("ipci165_irq_handler\n"); */
/* read interrupt control register (byte 0) */
- icr = readb(crm_addr + CRM_ICR);
+ icr = can_readb(crm_addr + CRM_ICR);
if ((icr & 0x44) == 0x44)
{
DEBUGMSG ("ipci165_irq_handler: pending interrupt\n");
/* confirm pending interrupt */
- writeb(readb(ucr1_addr) | 0x01, ucr1_addr);
- writeb(readb(ucr1_addr) & ~0x01, ucr1_addr);
+ can_writeb(can_readb(ucr1_addr) | 0x01, ucr1_addr);
+ can_writeb(can_readb(ucr1_addr) & ~0x01, ucr1_addr);
/* call interrupt handler for every channel */
for (i=0 ; i < candev->nr_all_chips ; i++)
*/
int ipci165_request_io(struct candevice_t *candev)
{
- unsigned long dpram_addr;
- unsigned long crm_addr;
- unsigned long fix_addr;
+ unsigned long dpram_addr; /* physical address before remap for this function */
+ unsigned long crm_addr; /* physical address before remap for this function */
+ unsigned long fix_addr; /* physical address before remap for this function */
int i,j;
DEBUGMSG ("ipci165_request_io\n");
{
CANMSG ("This card was not fixed!\n");
- if (candev->io_addr == 0)
+ if (candev->aux_base_addr == NULL)
{
CANMSG ("You have to specify IO address parameter!\n");
return -EINVAL;
}
CANMSG ("Using specified IO address value for the memory [0x%lx]\n",
- candev->io_addr);
+ can_ioptr2ulong(candev->aux_base_addr));
}
else
{
CANMSG ("Fixed card. Using of 3 region [0x%lx]\n", fix_addr);
- candev->io_addr = fix_addr;
+ candev->aux_base_addr = fix_addr;
}
pci_write_config_dword (candev->sysdevptr.pcidev,
{
#endif /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
- if ((candev->dev_base_addr = (long) ioremap(dpram_addr,
+ if ((candev->dev_base_addr = ioremap(dpram_addr,
pci_resource_len(candev->sysdevptr.pcidev,2))))
{
DEBUGMSG ("ipci165_request_io: dpram remapped to 0x%lx\n", candev->dev_base_addr);
- if ((candev->io_addr = (long) ioremap(crm_addr,
+ if ((candev->aux_base_addr = ioremap(crm_addr,
pci_resource_len(candev->sysdevptr.pcidev,0))))
{
- DEBUGMSG ("ipci165_request_io: crm remapped to 0x%lx\n", candev->io_addr);
+ DEBUGMSG ("ipci165_request_io: crm remapped to 0x%lx\n", can_ioptr2ulong(candev->aux_base_addr));
/* all resources has been allocated */
- candev->res_addr=candev->io_addr;
/* Because of my mapping, I cannot use the
can_base_addr_fixup(candev, remap_addr) to remap the addresses */
return 0;
} else CANMSG("Unable to remap memory at: 0x%lx\n", crm_addr);
- iounmap((void*)candev->io_addr);
+ iounmap(candev->aux_base_addr);
} else CANMSG("Unable to remap memory at: 0x%lx\n", dpram_addr);
- iounmap((void*)candev->dev_base_addr);
+ iounmap(candev->dev_base_addr);
#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))
pci_release_region(candev->sysdevptr.pcidev, 0);
}
#endif
- iounmap((void*)candev->io_addr);
- iounmap((void*)candev->dev_base_addr);
+ iounmap(candev->aux_base_addr);
+ iounmap(candev->dev_base_addr);
#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))
pci_release_region(candev->sysdevptr.pcidev, 2);
*/
int ipci165_download_fw(struct candevice_t *candev)
{
- unsigned long dpram_addr = candev->dev_base_addr;
+ can_ioptr_t dpram_addr = candev->dev_base_addr;
char board_name[BOARD_NAME_LEN+1];
char hw_version[HW_VERSION_LEN+1];
char mode[MODE_LEN+1];
while (fwArray->len)
{
/* fill buffer */
- writeb(LD_CMD_DOWNLOAD, dpram_addr + OF_LD_CMD);
- writeb(fwArray->len, dpram_addr + OF_LD_NUM);
- writeb(0, dpram_addr + OF_LD_NUM + 1);
+ can_writeb(LD_CMD_DOWNLOAD, dpram_addr + OF_LD_CMD);
+ can_writeb(fwArray->len, dpram_addr + OF_LD_NUM);
+ can_writeb(0, dpram_addr + OF_LD_NUM + 1);
- writel(fwArray->addr, dpram_addr + OF_LD_ADDRESS);
- /* writel already performes the cpu_to_le32 conversion by itself */
- /* writel(cpu_to_le32(fwArray->addr), dpram_addr + OF_LD_ADDRESS); */
+ can_writel(fwArray->addr, dpram_addr + OF_LD_ADDRESS);
+ /* can_writel already performes the cpu_to_le32 conversion by itself */
+ /* can_writel(cpu_to_le32(fwArray->addr), dpram_addr + OF_LD_ADDRESS); */
memcpy_toio(dpram_addr + OF_LD_DATA, fwArray->a_data, fwArray->len);
dump_mem((void *)(dpram_addr + OF_LD_SYNC), fwArray->len + 8);
#endif
/* buffer is prepared, set flag for loader */
- writeb(1, dpram_addr + OF_LD_SYNC);
+ can_writeb(1, dpram_addr + OF_LD_SYNC);
/* update pointer */
fwArray++;
/* wait for the loader */
attempt = 1000;
- while (readb(dpram_addr + OF_LD_SYNC) != 0)
+ while (can_readb(dpram_addr + OF_LD_SYNC) != 0)
{
udelay(100);
if (--attempt == 0)
CANMSG ("Firmware downladed successfully\n");
/* start the FW */
- writeb(LD_CMD_START_FW, dpram_addr + OF_LD_CMD);
- writeb(1, dpram_addr + OF_LD_SYNC);
+ can_writeb(LD_CMD_START_FW, dpram_addr + OF_LD_CMD);
+ can_writeb(1, dpram_addr + OF_LD_SYNC);
ipci165_delay (500);
return 0;
*/
int ipci165_reset(struct candevice_t *candev)
{
- unsigned long crm_addr = candev->io_addr;
+ can_ioptr_t crm_addr = candev->aux_base_addr;
unsigned long test_data;
char buffer[BCI_CMD_MAX_LEN];
int i, size, chips;
DEBUGMSG ("ipci165_reset: hardware reset\n");
/* reset the HW */
- ucr = readb(crm_addr + CRM_UCR + 3);
- writeb(ucr | 0x40, crm_addr + CRM_UCR + 3);
+ ucr = can_readb(crm_addr + CRM_UCR + 3);
+ can_writeb(ucr | 0x40, crm_addr + CRM_UCR + 3);
udelay(100);
- writeb(ucr & ~0x40, crm_addr + CRM_UCR + 3);
+ can_writeb(ucr & ~0x40, crm_addr + CRM_UCR + 3);
/* wait a little bit */
ipci165_delay(200);
-#include <linux/config.h>
#include <linux/version.h>
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,17))
+#include <linux/config.h>
+#endif
#if defined(MODVERSIONS)
#include <linux/modversions.h>
{
unsigned long tmp;
/* Disable interrupts from card */
- tmp = inl(candev->dev_base_addr + S5920_INTCSR);
+ tmp = can_inl(candev->dev_base_addr + S5920_INTCSR);
tmp &= ~INTCSR_ADDON_INTENABLE_M;
- outl(tmp, candev->dev_base_addr + S5920_INTCSR);
+ can_outl(tmp, candev->dev_base_addr + S5920_INTCSR);
}
void kv_pcican_connect_irq(struct candevice_t *candev)
{
unsigned long tmp;
/* Enable interrupts from card */
- tmp = inl(candev->dev_base_addr + S5920_INTCSR);
+ tmp = can_inl(candev->dev_base_addr + S5920_INTCSR);
tmp |= INTCSR_ADDON_INTENABLE_M;
- outl(tmp, candev->dev_base_addr + S5920_INTCSR);
+ can_outl(tmp, candev->dev_base_addr + S5920_INTCSR);
}
}
-void kv_pcican_write_register(unsigned data, unsigned long address)
+void kv_pcican_write_register(unsigned data, can_ioptr_t address)
{
- outb(data,address);
+ can_outb(data,address);
}
-unsigned kv_pcican_read_register(unsigned long address)
+unsigned kv_pcican_read_register(can_ioptr_t address)
{
- return inb(address);
+ return can_inb(address);
}
int kv_pcican_reset(struct candevice_t *candev)
DEBUGMSG("Resetting kv_pcican hardware ...\n");
/* Assert PTADR# - we're in passive mode so the other bits are not important */
- outl(0x80808080L, candev->dev_base_addr + S5920_PTCR);
+ can_outl(0x80808080L, candev->dev_base_addr + S5920_PTCR);
kv_pcican_disconnect_irq(candev);
#define IO_RANGE 0x100
-static long base = 0L;
-
/**
* m437_request_io: - reserve io or memory range for can board
* @candev: pointer to candevice/board which asks for io. Field @io_addr
return -ENODEV;
}
- if ( !( base = (long) ioremap( candev->io_addr, IO_RANGE ) ) ) {
+ if ( !( candev->dev_base_addr = ioremap( candev->io_addr, IO_RANGE ) ) ) {
CANMSG("Unable to access I/O memory at: 0x%lx\n", candev->io_addr);
can_release_mem_region(candev->io_addr,IO_RANGE);
return -ENODEV;
unsigned i;
/* disable IRQ generation */
- m437_write_register(iCTL_CCE, iCTL);
+ m437_write_register(iCTL_CCE, candev->dev_base_addr+iCTL);
/* clear all message objects */
for (i=1; i<=15; i++) {
RXIE_RES |
TXIE_RES |
MVAL_RES,
- i*0x10+iMSGCTL0);
+ candev->dev_base_addr+i*0x10+iMSGCTL0);
m437_write_register(
NEWD_RES |
MLST_RES |
CPUU_RES |
TXRQ_RES |
RMPD_RES,
- i*0x10+iMSGCTL1);
+ candev->dev_base_addr+i*0x10+iMSGCTL1);
}
/* power down i82527 */
- m437_write_register(iCPU_PWD, iCPU);
+ m437_write_register(iCPU_PWD, candev->dev_base_addr+iCPU);
/* release I/O memory mapping */
- iounmap((void*)base);
+ iounmap(candev->dev_base_addr);
can_release_mem_region(candev->io_addr,IO_RANGE);
int m437_init_chip_data(struct candevice_t *candev, int chipnr)
{
i82527_fill_chipspecops(candev->chip[chipnr]);
- candev->chip[chipnr]->chip_base_addr=candev->io_addr;
+ candev->chip[chipnr]->chip_base_addr=candev->dev_base_addr;
candev->chip[chipnr]->clock = 16000000;
candev->chip[chipnr]->int_cpu_reg = iCPU_DSC | iCPU_CEN;
candev->chip[chipnr]->int_clk_reg =
* Return Value: The function does not return a value
* File: src/m437.c
*/
-void m437_write_register(unsigned data, unsigned long address)
+void m437_write_register(unsigned data, can_ioptr_t address)
{
- writeb(data,base+address);
+ can_writeb(data,address);
}
/**
* Return Value: The function returns the value stored in @address
* File: src/m437.c
*/
-unsigned m437_read_register(unsigned long address)
+unsigned m437_read_register(can_ioptr_t address)
{
- return readb(base+address);
+ return can_readb(address);
}
/* !!! Don't change this function !!! */
DEBUGMSG("Resetting msmcan hardware ...\n");
/* we don't use template_write_register because we don't use the two first
registers of the card but the third in order to make a hard reset */
- /* outb (1, msmcan_base + candev->res_addr); */
+ /* can_outb (1, msmcan_base + candev->res_addr); */
/* terrible MSMCAN reset design - best to comment out */
i82527_fill_chipspecops(candev->chip[chipnr]);
/* device uses indexed access */
candev->chip[chipnr]->chip_base_addr=
- candev->io_addr << 16;
+ can_ioport2ioptr(candev->io_addr << 16);
candev->chip[chipnr]->clock = 16000000;
/* The CLKOUT has to be enabled to reset MSMCAN MAX1232 watchdog */
candev->chip[chipnr]->int_cpu_reg = iCPU_DSC | iCPU_CEN;
* on the CAN chip. You should only have to edit this function if your hardware
* uses some specific write process.
*/
-void msmcan_write_register(unsigned data, unsigned long address)
+void msmcan_write_register(unsigned data, can_ioptr_t address)
{
/* address is combination of base address shifted left by 16 and index */
can_spin_irqflags_t flags;
+ unsigned long addr=can_ioptr2ulong(address);
/* the msmcan card has two registers, the data register at 0x0
and the address register at 0x01 */
can_spin_lock_irqsave(&msmcan_port_lock,flags);
- outb(address & 0xff, (address>>16)+1);
- outb(data, address>>16);
+ can_outb(addr & 0xff, (addr>>16)+1);
+ can_outb(data, addr>>16);
can_spin_unlock_irqrestore(&msmcan_port_lock,flags);
}
* on the CAN chip. You should only have to edit this function if your hardware
* uses some specific read process.
*/
-unsigned msmcan_read_register(unsigned long address)
+unsigned msmcan_read_register(can_ioptr_t address)
{
/* this is the same thing that the function write_register.
We use the two register, we write the address where we
data */
unsigned char ret;
can_spin_irqflags_t flags;
-
+ unsigned long addr=can_ioptr2ulong(address);
can_spin_lock_irqsave(&msmcan_port_lock,flags);
- outb(address & 0xff, (address>>16)+1);
- ret=inb(address>>16);
+ can_outb(addr & 0xff, (addr>>16)+1);
+ ret=can_inb(addr>>16);
can_spin_unlock_irqrestore(&msmcan_port_lock,flags);
return ret;
}
(unsigned long)candev->io_addr);
}
- if (!(candev->dev_base_addr = (long)ioremap(candev->io_addr, IO_RANGE))) {
+ if (!(candev->dev_base_addr = ioremap(candev->io_addr, IO_RANGE))) {
DEBUGMSG
("Failed to map IO-memory: 0x%lx - 0x%lx, mapped to 0x%lx\n",
(unsigned long)candev->io_addr,
*/
int ns_dev_release_io(struct candevice_t *candev)
{
- u16 tempReg;
- int i;
-
DEBUGMSG("(c%d)ns_dev_release_io (...)\n", candev->chip[0]->chip_idx);
/* Release I/O memory mapping */
- iounmap((void *)candev->dev_base_addr);
+ iounmap(candev->dev_base_addr);
/* Release the memory region */
can_release_mem_region(candev->io_addr, IO_RANGE);
*/
int ns_dev_init_hw_data(struct candevice_t *candev)
{
- u32 sys_contVA = 0;
+ can_ioptr_t sys_contVA = NULL;
/* LUCAN : Magic numbers */
- if (!(sys_contVA = (u32) ioremap(NS9750_PERIPHERAL_BASE_ADDRESS,
+ if (!(sys_contVA = ioremap(NS9750_PERIPHERAL_BASE_ADDRESS,
NS9750_PERIPHERAL_MAP_SIZE))) {
DEBUGMSG("Failed to map FPGA memory\n");
return -EIO;
} else {
DEBUGMSG("Writing to NS9750 sys cont\n");
- writel((BUS_WIDTH_16BIT | ACTIVE_LOW_CHIP_SELECT),
+ can_writel((BUS_WIDTH_16BIT | ACTIVE_LOW_CHIP_SELECT),
sys_contVA + NS9750_SYSTEM_CONTROLLER_OFFSET);
}
/* We have finished with this mapping */
- iounmap((void *)sys_contVA);
+ iounmap(sys_contVA);
candev->nr_82527_chips = 0;
candev->nr_sja1000_chips = 0;
* Return Value: The function does not return a value
* File: src/template.c
*/
-void ns_dev_write_register(unsigned data, unsigned long address)
+void ns_dev_write_register(unsigned data, can_ioptr_t address)
{
int i;
//unsigned long usecs = 1;
- writew(data, address);
+ can_writew(data, address);
//udelay( usecs );
for (i = 0; i < 5; i++) ;
}
* Return Value: The function returns the value stored in @address
* File: src/template.c
*/
-unsigned ns_dev_read_register(unsigned long address)
+unsigned ns_dev_read_register(can_ioptr_t address)
{
u16 value, i;
- value = readw(address);
+ value = can_readw(address);
//udelay( usecs );
for (i = 0; i < 5; i++) ;
- value = readw(address);
+ value = can_readw(address);
//udelay( usecs );
for (i = 0; i < 5; i++) ;
DEBUGMSG("Resetting nsi hardware ...\n");
/* we don't use template_write_register because we don't use the two first
register of the card but the third in order to make a hard reset */
- outb (1, nsican_base + candev->res_addr);
- outb (0, nsican_base + candev->res_addr);
+ can_outb (1, nsican_base + candev->res_addr);
+ can_outb (0, nsican_base + candev->res_addr);
for (i = 1; i < 1000; i++)
udelay (1000);
{
i82527_fill_chipspecops(candev->chip[chipnr]);
candev->chip[chipnr]->chip_base_addr=
- candev->io_addr;
+ can_ioport2ioptr(candev->io_addr);
candev->chip[chipnr]->clock = 16000000;
nsican_irq=candev->chip[chipnr]->chip_irq;
nsican_base=candev->chip[chipnr]->chip_base_addr;
* on the CAN chip. You should only have to edit this function if your hardware
* uses some specific write process.
*/
-void nsi_write_register(unsigned data, unsigned long address)
+void nsi_write_register(unsigned data, can_ioptr_t address)
{
/* address is an absolute address */
/* write the relative address on the eight LSB bits
and the data on the eight MSB bits in one time */
- outw(address-nsican_base + (256 * data), nsican_base);
+ can_outw(address-nsican_base + (256 * data), nsican_base);
}
/* The function template_read_register is used to read from hardware registers
* on the CAN chip. You should only have to edit this function if your hardware
* uses some specific read process.
*/
-unsigned nsi_read_register(unsigned long address)
+unsigned nsi_read_register(can_ioptr_t address)
{
/* this is the same thing that the function write_register.
We use the two register, we write the address where we
can_spin_irqflags_t flags;
can_spin_lock_irqsave(&nsican_port_lock,flags);
- outb(address-nsican_base, nsican_base);
- ret=inb(nsican_base+1);
+ can_outb(address-nsican_base, nsican_base);
+ ret=can_inb(nsican_base+1);
can_spin_unlock_irqrestore(&nsican_port_lock,flags);
return ret;
}
#include <linux/module.h>
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10))
- #define ioread32 readl
- #define iowrite32 writel
- #define ioread8 readb
- #define iowrite8 writeb
+ #define ioread32 can_readl
+ #define iowrite32 can_writel
+ #define ioread8 can_readb
+ #define iowrite8 can_writeb
#else
#endif
* on the CAN chip. You should only have to edit this function if your hardware
* uses some specific write process.
*/
-void nsi_canpci_write_register(unsigned data, unsigned long address)
+void nsi_canpci_write_register(unsigned data, can_ioptr_t address)
{
iowrite8((u8)data,(void*)address);
}
* on the CAN chip. You should only have to edit this function if your hardware
* uses some specific read process.
*/
-unsigned nsi_canpci_read_register(unsigned long address)
+unsigned nsi_canpci_read_register(can_ioptr_t address)
{
return ioread8((void*)address);
}
// sja1000_fill_chipspecops(candev->chip[chipnr]);
sja1000p_fill_chipspecops(candev->chip[chipnr]);
- candev->chip[chipnr]->chip_base_addr = candev->io_addr;
+ candev->chip[chipnr]->chip_base_addr = can_ioport2ioptr(candev->io_addr);
candev->chip[chipnr]->clock = 12000000;
candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CBP; // we use an external tranceiver
candev->chip[chipnr]->sja_ocr_reg = sjaOCR_MODE_NORMAL | sjaOCR_TX0_LH;
return 0;
}
-void oscar_write_register(unsigned data, unsigned long address)
+void oscar_write_register(unsigned data, can_ioptr_t address)
{
- outb(data,address);
+ can_outb(data,address);
}
-unsigned oscar_read_register(unsigned long address)
+unsigned oscar_read_register(can_ioptr_t address)
{
- return inb(address);
+ return can_inb(address);
}
/* !!! Don't change this function !!! */
* Return Value: The function does not return a value
* File: src/pc-i03.c
*/
-void pci03_write_register(unsigned data, unsigned long address)
+void pci03_write_register(unsigned data, can_ioptr_t address)
{
unsigned int *pci03_base_ptr;
unsigned short address_to_write;
* Return Value: The function returns the value stored in @address
* File: src/pc-i03.c
*/
-unsigned pci03_read_register(unsigned long address)
+unsigned pci03_read_register(can_ioptr_t address)
{
unsigned int *pci03_base_ptr;
unsigned short address_to_read;
static void _parport_disable_irq(struct DONGLE_PORT *dng)
{
u16 _PC_ = (u16)dng->dwPort + 2;
- outb(inb(_PC_) & ~0x10, _PC_);
+ can_outb(can_inb(_PC_) & ~0x10, _PC_);
}
static void _parport_enable_irq(struct DONGLE_PORT *dng)
{
u16 _PC_ = (u16)dng->dwPort + 2;
- outb(inb(_PC_) | 0x10, _PC_);
+ can_outb(can_inb(_PC_) | 0x10, _PC_);
}
u16 _PB_ = _PA_ + 1;
u16 _PC_ = _PB_ + 1;
u8 b0, b1 ;
- u8 irqEnable = inb(_PC_) & 0x10; // don't influence irqEnable
+ u8 irqEnable = can_inb(_PC_) & 0x10; // don't influence irqEnable
can_spin_irqflags_t flags;
can_spin_lock_irqsave(&pcan_lock, flags);
- outb((0x0B ^ 0x0D) | irqEnable, _PC_);
- outb((port & 0x1F) | 0x80, _PA_);
- outb((0x0B ^ 0x0C) | irqEnable, _PC_);
- b1=nibble_decode[inb(_PB_)>>3];
- outb(0x40, _PA_);
- b0=nibble_decode[inb(_PB_)>>3];
- outb((0x0B ^ 0x0D) | irqEnable, _PC_);
+ can_outb((0x0B ^ 0x0D) | irqEnable, _PC_);
+ can_outb((port & 0x1F) | 0x80, _PA_);
+ can_outb((0x0B ^ 0x0C) | irqEnable, _PC_);
+ b1=nibble_decode[can_inb(_PB_)>>3];
+ can_outb(0x40, _PA_);
+ b0=nibble_decode[can_inb(_PB_)>>3];
+ can_outb((0x0B ^ 0x0D) | irqEnable, _PC_);
can_spin_unlock_irqrestore(&pcan_lock, flags);
{
u16 _PA_ = (u16)dng->dwPort;
u16 _PC_ = _PA_ + 2;
- u8 irqEnable = inb(_PC_) & 0x10; // don't influence irqEnable
+ u8 irqEnable = can_inb(_PC_) & 0x10; // don't influence irqEnable
can_spin_irqflags_t flags;
can_spin_lock_irqsave(&pcan_lock, flags);
- outb((0x0B ^ 0x0D) | irqEnable, _PC_);
- outb(port & 0x1F, _PA_);
- outb((0x0B ^ 0x0C) | irqEnable, _PC_);
- outb(data, _PA_);
- outb((0x0B ^ 0x0D) | irqEnable, _PC_);
+ can_outb((0x0B ^ 0x0D) | irqEnable, _PC_);
+ can_outb(port & 0x1F, _PA_);
+ can_outb((0x0B ^ 0x0C) | irqEnable, _PC_);
+ can_outb(data, _PA_);
+ can_outb((0x0B ^ 0x0D) | irqEnable, _PC_);
can_spin_unlock_irqrestore(&pcan_lock, flags);
}
u16 _PA_ = (u16)dng->dwPort;
u16 _PC_ = _PA_ + 2;
u8 wert;
- u8 irqEnable = inb(_PC_) & 0x10; // don't influence irqEnable
+ u8 irqEnable = can_inb(_PC_) & 0x10; // don't influence irqEnable
can_spin_irqflags_t flags;
can_spin_lock_irqsave(&pcan_lock, flags);
- outb((0x0B ^ 0x0F) | irqEnable, _PC_);
- outb((port & 0x1F) | 0x80, _PA_);
- outb((0x0B ^ 0x2E) | irqEnable, _PC_);
- wert = inb(_PA_);
- outb((0x0B ^ 0x0F) | irqEnable, _PC_);
+ can_outb((0x0B ^ 0x0F) | irqEnable, _PC_);
+ can_outb((port & 0x1F) | 0x80, _PA_);
+ can_outb((0x0B ^ 0x2E) | irqEnable, _PC_);
+ wert = can_inb(_PA_);
+ can_outb((0x0B ^ 0x0F) | irqEnable, _PC_);
can_spin_unlock_irqrestore(&pcan_lock, flags);
{
u16 wEcr = dng->wEcr;
- dng->ucOldECRContent = inb(wEcr);
- outb((dng->ucOldECRContent & 0x1F) | 0x20, wEcr);
+ dng->ucOldECRContent = can_inb(wEcr);
+ can_outb((dng->ucOldECRContent & 0x1F) | 0x20, wEcr);
if (dng->ucOldECRContent == 0xff)
DEBUGMSG("%s: realy ECP mode configured?\n", DEVICE_NAME);
{
u16 wEcr = dng->wEcr;
- outb(dng->ucOldECRContent, wEcr);
+ can_outb(dng->ucOldECRContent, wEcr);
DEBUGMSG("%s: restore ECR\n", DEVICE_NAME);
}
wPort = (u16)dng->dwPort;
// save old port contents
- dng->ucOldDataContent = inb(wPort);
- dng->ucOldControlContent = inb(wPort + 2);
+ dng->ucOldDataContent = can_inb(wPort);
+ dng->ucOldControlContent = can_inb(wPort + 2);
// switch to epp mode if possible
if (dng->wType == HW_DONGLE_SJA_EPP)
restoreECR(dng);
// restore port state
- outb(dng->ucOldDataContent, wPort);
- outb(dng->ucOldControlContent, wPort + 2);
+ can_outb(dng->ucOldDataContent, wPort);
+ can_outb(dng->ucOldControlContent, wPort + 2);
parport_release(dng->pardev);
candev->chip[chipnr]->chip_type=CHIP_TYPE;
- candev->chip[chipnr]->chip_base_addr=candev->io_addr;
+ candev->chip[chipnr]->chip_base_addr=can_ioport2ioptr(candev->io_addr);
candev->chip[chipnr]->clock = 16000000;
candev->chip[chipnr]->int_clk_reg = 0x0;
candev->chip[chipnr]->int_bus_reg = 0x0;
* Return Value: The function does not return a value
* File: src/template.c
*/
-void pcan_dongle_write_register(unsigned data, unsigned long address)
+void pcan_dongle_write_register(unsigned data, can_ioptr_t address)
{
address -= dongle_port.chip->chip_base_addr; // it's in mutiplexed mode
* Return Value: The function returns the value stored in @address
* File: src/template.c
*/
-unsigned pcan_dongle_read_register(unsigned long address)
+unsigned pcan_dongle_read_register(can_ioptr_t address)
{
u8 val;
DEBUGMSG("Resetting pccanf/s hardware ...\n");
while (i < 1000000) {
i++;
- outb(0x00,candev->res_addr);
+ can_outb(0x00,candev->res_addr);
}
- outb(0x01,candev->res_addr);
- outb(0x00,candev->chip[0]->chip_base_addr+SJACR);
+ can_outb(0x01,candev->res_addr);
+ can_outb(0x00,candev->chip[0]->chip_base_addr+SJACR);
/* Check hardware reset status */
i=0;
- while ( (inb(candev->chip[0]->chip_base_addr+SJACR) & sjaCR_RR)
+ while ( (can_inb(candev->chip[0]->chip_base_addr+SJACR) & sjaCR_RR)
&& (i<=15) ) {
udelay(20000);
i++;
DEBUGMSG("Resetting pccan-d hardware ...\n");
while (i < 1000000) {
i++;
- outb(0x00,candev->res_addr);
+ can_outb(0x00,candev->res_addr);
}
- outb(0x01,candev->res_addr);
- outb(0x00,candev->chip[0]->chip_base_addr+SJACR);
- outb(0x00,candev->chip[1]->chip_base_addr+SJACR);
+ can_outb(0x01,candev->res_addr);
+ can_outb(0x00,candev->chip[0]->chip_base_addr+SJACR);
+ can_outb(0x00,candev->chip[1]->chip_base_addr+SJACR);
/* Check hardware reset status */
i=0;
for (chip_nr=0; chip_nr<2; chip_nr++) {
i=0;
- while ( (inb(candev->chip[chip_nr]->chip_base_addr +
+ while ( (can_inb(candev->chip[chip_nr]->chip_base_addr +
SJACR) & sjaCR_RR) && (i<=15) ) {
udelay(20000);
i++;
DEBUGMSG("Resetting pccan-q hardware ...\n");
while (i < 100000) {
i++;
- outb(0x00,candev->res_addr);
+ can_outb(0x00,candev->res_addr);
}
outb_p(0x01,candev->res_addr);
- outb(0x00,candev->chip[2]->chip_base_addr+SJACR);
- outb(0x00,candev->chip[3]->chip_base_addr+SJACR);
+ can_outb(0x00,candev->chip[2]->chip_base_addr+SJACR);
+ can_outb(0x00,candev->chip[3]->chip_base_addr+SJACR);
/* Check hardware reset status */
for (chip_nr=0; chip_nr<2; chip_nr++) {
i=0;
- while( (inb(candev->chip[chip_nr]->chip_base_addr +
+ while( (can_inb(candev->chip[chip_nr]->chip_base_addr +
iCPU) & iCPU_RST) && (i<=15) ) {
udelay(20000);
i++;
}
for (chip_nr=2; chip_nr<4; chip_nr++) {
i=0;
- while( (inb(candev->chip[chip_nr]->chip_base_addr +
+ while( (can_inb(candev->chip[chip_nr]->chip_base_addr +
SJACR) & sjaCR_RR) && (i<=15) ) {
udelay(20000);
i++;
candev->chip[chipnr]->sja_ocr_reg =
sjaOCR_MODE_NORMAL | sjaOCR_TX0_LH;
}
- candev->chip[chipnr]->chip_base_addr=0x1000*chipnr+0x2000+candev->io_addr;
+ candev->chip[chipnr]->chip_base_addr=can_ioport2ioptr(0x1000*chipnr+0x2000+candev->io_addr);
}
else {
sja1000_fill_chipspecops(candev->chip[chipnr]);
- candev->chip[chipnr]->chip_base_addr=0x1000*chipnr+0x4000+candev->io_addr;
+ candev->chip[chipnr]->chip_base_addr=can_ioport2ioptr(0x1000*chipnr+0x4000+candev->io_addr);
candev->chip[chipnr]->flags = 0;
candev->chip[chipnr]->int_cpu_reg = 0;
candev->chip[chipnr]->int_clk_reg = 0;
}
}
}
- outb(irq_reg_value,0x6000+candev->io_addr);
+ can_outb(irq_reg_value,0x6000+candev->io_addr);
DEBUGMSG("Configured pccan hardware interrupts\n");
- outb(0x80,0x6000+candev->io_addr+0x02);
+ can_outb(0x80,0x6000+candev->io_addr+0x02);
DEBUGMSG("Selected pccan on-board 16 MHz oscillator\n");
return 0;
}
-inline void pccan_write_register(unsigned data, unsigned long address)
+inline void pccan_write_register(unsigned data, can_ioptr_t address)
{
- outb(data,address);
+ can_outb(data,address);
}
-unsigned pccan_read_register(unsigned long address)
+unsigned pccan_read_register(can_ioptr_t address)
{
- return inb(address);
+ return can_inb(address);
}
int pccanf_register(struct hwspecops_t *hwspecops)
DEBUGMSG("Resetting pcccan-1 hardware ...\n");
while (i < 1000000) {
i++;
- outb(0x0,candev->res_addr);
+ can_outb(0x0,candev->res_addr);
}
/* Check hardware reset status */
i=0;
- outb(iCPU,candev->io_addr+0x1);
- while ( (inb(candev->io_addr+0x2)&0x80) && (i<=15) ) {
+ can_outb(iCPU,candev->io_addr+0x1);
+ while ( (can_inb(candev->io_addr+0x2)&0x80) && (i<=15) ) {
udelay(20000);
i++;
}
int pcccan_init_chip_data(struct candevice_t *candev, int chipnr)
{
i82527_fill_chipspecops(candev->chip[chipnr]);
- candev->chip[chipnr]->chip_base_addr=candev->io_addr;
+ candev->chip[chipnr]->chip_base_addr=can_ioport2ioptr(candev->io_addr);
candev->chip[chipnr]->clock = 16000000;
candev->chip[chipnr]->int_cpu_reg = iCPU_DSC | iCPU_DMC;
candev->chip[chipnr]->int_clk_reg = iCLK_SL1 | iCLK_CD0;
* Return Value: The function does not return a value
* File: src/pcccan.c
*/
-void pcccan_write_register(unsigned data, unsigned long address)
+void pcccan_write_register(unsigned data, can_ioptr_t address)
{
can_spin_irqflags_t flags;
can_spin_lock_irqsave(&pcccan_port_lock,flags);
- outb(address - pcccan_base, pcccan_base+1);
- outb(data, pcccan_base+6);
+ can_outb(address - pcccan_base, pcccan_base+1);
+ can_outb(data, pcccan_base+6);
can_spin_unlock_irqrestore(&pcccan_port_lock,flags);
}
* Return Value: The function returns the value stored in @address
* File: src/pcccan.c
*/
-unsigned pcccan_read_register(unsigned long address)
+unsigned pcccan_read_register(can_ioptr_t address)
{
unsigned ret;
can_spin_irqflags_t flags;
can_spin_lock_irqsave(&pcccan_port_lock,flags);
- outb(address - pcccan_base, pcccan_base+1);
- ret=inb(pcccan_base+2);
+ can_outb(address - pcccan_base, pcccan_base+1);
+ ret=can_inb(pcccan_base+2);
can_spin_unlock_irqrestore(&pcccan_port_lock,flags);
return ret;
*/
int pcm3680_request_io(struct candevice_t *candev)
{
- unsigned long remap_addr;
+ can_ioptr_t remap_addr;
if (!can_request_mem_region(candev->io_addr,IO_RANGE,DEVICE_NAME " - pcm3680")) {
CANMSG("Unable to request IO-memory: 0x%lx\n",candev->io_addr);
return -ENODEV;
}
- if ( !( remap_addr = (long) ioremap( candev->io_addr, IO_RANGE ) ) ) {
+ if ( !( remap_addr = ioremap( candev->io_addr, IO_RANGE ) ) ) {
CANMSG("Unable to access I/O memory at: 0x%lx\n", candev->io_addr);
can_release_mem_region(candev->io_addr,IO_RANGE);
return -ENODEV;
{
sja1000p_fill_chipspecops(candev->chip[chipnr]);
candev->chip[chipnr]->chip_base_addr=
- candev->io_addr + 0x200*chipnr;
+ candev->dev_base_addr + 0x200*chipnr;
candev->chip[chipnr]->clock = 16000000;
candev->chip[chipnr]->int_clk_reg = 0x0;
candev->chip[chipnr]->int_bus_reg = 0x0;
* Return Value: The function does not return a value
* File: src/template.c
*/
-void pcm3680_write_register(unsigned data, unsigned long address)
+void pcm3680_write_register(unsigned data, can_ioptr_t address)
{
- writeb(data,address);
+ can_writeb(data,address);
}
/**
* Return Value: The function returns the value stored in @address
* File: src/template.c
*/
-unsigned pcm3680_read_register(unsigned long address)
+unsigned pcm3680_read_register(can_ioptr_t address)
{
- return readb(address);
+ return can_readb(address);
}
/* !!! Don't change this function !!! */
*/
int pikronisa_request_io(struct candevice_t *candev)
{
- int remap_addr;
+ can_ioptr_t remap_addr;
if (!can_request_mem_region(candev->io_addr,IO_RANGE,DEVICE_NAME " - pikronisa")) {
CANMSG("Unable to request IO-memory: 0x%lx\n",candev->io_addr);
return -ENODEV;
}
- if ( !( remap_addr = (long) ioremap( candev->io_addr, IO_RANGE ) ) ) {
+ if ( !( remap_addr = ioremap( candev->io_addr, IO_RANGE ) ) ) {
CANMSG("Unable to access I/O memory at: 0x%lx\n", candev->io_addr);
can_release_mem_region(candev->io_addr,IO_RANGE);
return -ENODEV;
int pikronisa_release_io(struct candevice_t *candev)
{
/* release I/O memory mapping */
- iounmap((void*)candev->dev_base_addr);
+ iounmap(candev->dev_base_addr);
can_release_mem_region(candev->io_addr,IO_RANGE);
return 0;
/*sja1000_fill_chipspecops(candev->chip[chipnr]);*/
sja1000p_fill_chipspecops(candev->chip[chipnr]);
- candev->chip[chipnr]->chip_base_addr=candev->io_addr;
+ candev->chip[chipnr]->chip_base_addr=candev->dev_base_addr;
candev->chip[chipnr]->clock = 24000000;
candev->chip[chipnr]->int_clk_reg = 0x0;
candev->chip[chipnr]->int_bus_reg = 0x0;
* Return Value: The function does not return a value
* File: src/pikronisa.c
*/
-void pikronisa_write_register(unsigned data, unsigned long address)
+void pikronisa_write_register(unsigned data, can_ioptr_t address)
{
/*DEBUGMSG("pikronisa_write_register: addr=0x%lx data=0x%x",
address,data);*/
- writeb(data,address);
+ can_writeb(data,address);
}
/**
* Return Value: The function returns the value stored in @address
* File: src/pikronisa.c
*/
-unsigned pikronisa_read_register(unsigned long address)
+unsigned pikronisa_read_register(can_ioptr_t address)
{
- return readb(address);
+ return can_readb(address);
}
/* !!! Don't change this function !!! */
* Return Value: The function does not return a value
* File: src/pikronisa.c
*/
-void pimx1_write_register(unsigned data, unsigned long address)
+void pimx1_write_register(unsigned data, can_ioptr_t address)
{
/*DEBUGMSG("pimx1_write_register: addr=0x%lx data=0x%x\n",
address,data);*/
- writeb(data,address);
+ can_writeb(data,address);
}
/**
* Return Value: The function returns the value stored in @address
* File: src/pikronisa.c
*/
-unsigned pimx1_read_register(unsigned long address)
+unsigned pimx1_read_register(can_ioptr_t address)
{
- return readb(address);
+ return can_readb(address);
}
/**
DEBUGMSG("Resetting %s hardware ...\n", candev->hwname);
while (i < 1000000) {
i++;
- outb(0x01, candev->res_addr);
+ can_outb(0x01, candev->res_addr);
}
- outb(0x0, candev->res_addr);
+ can_outb(0x0, candev->res_addr);
/* Check hardware reset status */
i = 0;
- while ((inb(candev->io_addr + iCPU) & iCPU_RST) && (i <= 15)) {
+ while ((can_inb(candev->io_addr + iCPU) & iCPU_RST) && (i <= 15)) {
udelay(20000);
i++;
}
int pip_init_chip_data(struct candevice_t *candev, int chipnr)
{
i82527_fill_chipspecops(candev->chip[chipnr]);
- candev->chip[chipnr]->chip_base_addr = candev->io_addr;
+ candev->chip[chipnr]->chip_base_addr = can_ioport2ioptr(candev->io_addr);
candev->chip[chipnr]->clock = 8000000;
candev->chip[chipnr]->int_cpu_reg = 0;
candev->chip[chipnr]->int_clk_reg = iCLK_SL1;
unsigned char can_addr = 0, can_reg = 0;
DEBUGMSG("pip_program_irq\n");
/* Reset can controller */
- outb(0x01, candev->res_addr);
+ can_outb(0x01, candev->res_addr);
if (strcmp(candev->hwname, "pip5") == 0) {
irq_mask = PIP5_IRQ_MAP;
} else if (strcmp(candev->hwname, "pip6") == 0) {
return -ENODEV;
}
}
- can_reg = inb(PIP_CANRES_REG);
+ can_reg = can_inb(PIP_CANRES_REG);
DEBUGMSG("PIP_CANRES was 0x%x\n", can_reg);
can_reg = (candev->chip[0]->chip_irq << 4) | can_addr;
DEBUGMSG("Setting PIP_CANRES_REG to 0x%x\n", can_reg);
- outb((candev->chip[0]->chip_irq << 4) | can_addr, PIP_CANRES_REG);
+ can_outb((candev->chip[0]->chip_irq << 4) | can_addr, PIP_CANRES_REG);
/* re-enable the chip */
- outb(0x00, candev->res_addr);
+ can_outb(0x00, candev->res_addr);
return 0;
}
-void pip_write_register(unsigned data, unsigned long address)
+void pip_write_register(unsigned data, can_ioptr_t address)
{
- outb(data, address);
+ can_outb(data, address);
}
-unsigned pip_read_register(unsigned long address)
+unsigned pip_read_register(can_ioptr_t address)
{
- return inb(address);
+ return can_inb(address);
}
/* !!! Don't change these functions !!! */
len += sprintf(buf+len,"type : %s\n",chip->chip_type);
len += sprintf(buf+len,"index : %d\n",chip->chip_idx);
len += sprintf(buf+len,"irq : %d\n",chip->chip_irq);
- len += sprintf(buf+len,"addr : %lu\n",chip->chip_base_addr);
+ len += sprintf(buf+len,"addr : %lu\n",
+ can_ioptr2ulong(chip->chip_base_addr));
len += sprintf(buf+len,"config : %s\n",
- (chip->flags & CHIP_CONFIGURED) ? "yes":"no");
+ (chip->flags & CHIP_CONFIGURED) ? "yes":"no");
len += sprintf(buf+len,"clock : %ld Hz\n",chip->clock);
len += sprintf(buf+len,"baud : %ld\n",chip->baudrate);
len += sprintf(buf+len,"num obj : %d\n",chip->max_objects);
* This function is prepared to simplify board specific xxx_request_io() function
* for memory mapped devices.
*/
-int can_base_addr_fixup(struct candevice_t *candev, unsigned long new_base)
+int can_base_addr_fixup(struct candevice_t *candev, can_ioptr_t new_base)
{
- unsigned long offs;
+ long offs;
int i, j;
offs=new_base-candev->dev_base_addr;
int i=0;
DEBUGMSG("Resetting smartcan hardware ...\n");
- outb(0x00,candev->res_addr);
+ can_outb(0x00,candev->res_addr);
while (i < 1000000) {
i++;
- outb(0x01,candev->res_addr);
+ can_outb(0x01,candev->res_addr);
}
- outb(0x00,candev->res_addr);
+ can_outb(0x00,candev->res_addr);
/* Check hardware reset status */
i=0;
- outb(candev->io_addr+iCPU,candev->io_addr);
- while ( (inb(candev->io_addr+1)&0x80) && (i<=15) ) {
+ can_outb(candev->io_addr+iCPU,candev->io_addr);
+ while ( (can_inb(candev->io_addr+1)&0x80) && (i<=15) ) {
udelay(20000);
i++;
}
int smartcan_init_chip_data(struct candevice_t *candev, int chipnr)
{
i82527_fill_chipspecops(candev->chip[chipnr]);
- candev->chip[chipnr]->chip_base_addr=candev->io_addr;
+ candev->chip[chipnr]->chip_base_addr=can_ioport2ioptr(candev->io_addr);
candev->chip[chipnr]->clock = 16000000;
candev->chip[chipnr]->int_cpu_reg = iCPU_DSC;
candev->chip[chipnr]->int_clk_reg = iCLK_SL1;
}
-void smartcan_write_register(unsigned data, unsigned long address)
+void smartcan_write_register(unsigned data, can_ioptr_t address)
{
can_spin_irqflags_t flags;
can_spin_lock_irqsave(&smartcan_port_lock,flags);
- outb(address-smartcan_base,smartcan_base);
- outb(data,smartcan_base+1);
+ can_outb(address-smartcan_base,smartcan_base);
+ can_outb(data,smartcan_base+1);
can_spin_unlock_irqrestore(&smartcan_port_lock,flags);
}
-unsigned smartcan_read_register(unsigned long address)
+unsigned smartcan_read_register(can_ioptr_t address)
{
unsigned ret;
can_spin_irqflags_t flags;
can_spin_lock_irqsave(&smartcan_port_lock,flags);
- outb(address-smartcan_base,smartcan_base);
- ret=inb(smartcan_base+1);
+ can_outb(address-smartcan_base,smartcan_base);
+ ret=can_inb(smartcan_base+1);
can_spin_unlock_irqrestore(&smartcan_port_lock,flags);
return ret;
}
#include "../include/i82527.h"
int ssvcan_irq[2]={-1,-1};
-unsigned long ssvcan_base=0x0;
+can_ioptr_t ssvcan_base=0x0;
static CAN_DEFINE_SPINLOCK(ssv_port_lock);
{
i82527_fill_chipspecops(candev->chip[chipnr]);
candev->chip[chipnr]->chip_base_addr=
- candev->io_addr+0x100*chipnr;
+ can_ioport2ioptr(candev->io_addr+0x100*chipnr);
candev->chip[chipnr]->clock = 16000000;
ssvcan_irq[chipnr]=candev->chip[chipnr]->chip_irq;
* on the CAN chip. You should only have to edit this function if your hardware
* uses some specific write process.
*/
-void ssv_write_register(unsigned data, unsigned long address)
+void ssv_write_register(unsigned data, can_ioptr_t address)
{
/* address is an absolute address */
/* write the relative address on the eight LSB bits
and the data on the eight MSB bits in one time */
if((address-ssvcan_base)<0x100)
- outw(address-ssvcan_base + (256 * data), ssvcan_base);
+ can_outw(address-ssvcan_base + (256 * data), ssvcan_base);
else
- outw(address-ssvcan_base-0x100 + (256 * data), ssvcan_base+0x02);
+ can_outw(address-ssvcan_base-0x100 + (256 * data), ssvcan_base+0x02);
}
/* The function template_read_register is used to read from hardware registers
* on the CAN chip. You should only have to edit this function if your hardware
* uses some specific read process.
*/
-unsigned ssv_read_register(unsigned long address)
+unsigned ssv_read_register(can_ioptr_t address)
{
/* this is the same thing that the function write_register.
We use the two register, we write the address where we
if((address-ssvcan_base)<0x100)
{
can_spin_lock_irqsave(&ssv_port_lock,flags);
- outb(address-ssvcan_base, ssvcan_base);
- ret=inb(ssvcan_base+1);
+ can_outb(address-ssvcan_base, ssvcan_base);
+ ret=can_inb(ssvcan_base+1);
can_spin_unlock_irqrestore(&ssv_port_lock,flags);
}
else
{
can_spin_lock_irqsave(&ssv_port_lock,flags);
- outb(address-ssvcan_base-0x100, ssvcan_base+0x02);
- ret=inb(ssvcan_base+1+0x02);
+ can_outb(address-ssvcan_base-0x100, ssvcan_base+0x02);
+ ret=can_inb(ssvcan_base+1+0x02);
can_spin_unlock_irqrestore(&ssv_port_lock,flags);
}
/*sja1000_fill_chipspecops(candev->chip[chipnr]);*/
/*sja1000p_fill_chipspecops(candev->chip[chipnr]);*/
- candev->chip[chipnr]->chip_base_addr=candev->io_addr;
+ candev->chip[chipnr]->chip_base_addr=can_ioport2ioptr(candev->io_addr);
candev->chip[chipnr]->clock = 16000000;
candev->chip[chipnr]->int_cpu_reg = iCPU_DSC;
candev->chip[chipnr]->int_clk_reg = iCLK_SL1;
* Return Value: The function does not return a value
* File: src/template.c
*/
-void template_write_register(unsigned data, unsigned long address)
+void template_write_register(unsigned data, can_ioptr_t address)
{
- outb(data,address);
+ can_outb(data,address);
}
/**
* Return Value: The function returns the value stored in @address
* File: src/template.c
*/
-unsigned template_read_register(unsigned long address)
+unsigned template_read_register(can_ioptr_t address)
{
- return inb(address);
+ return can_inb(address);
}
/* !!! Don't change this function !!! */
default: mode=0x60; break;
}
- outb(0x00, candev->io_addr+TSCAN1_WIN_REG);
- outb(mode, candev->io_addr+TSCAN1_MOD_REG);
+ can_outb(0x00, candev->io_addr+TSCAN1_WIN_REG);
+ can_outb(mode, candev->io_addr+TSCAN1_MOD_REG);
return 0;
}
can_release_io_region(remap_can_io_addr, TSXXX_CAN_RANGE);
}
- outb(0x20, candev->io_addr+TSCAN1_MOD_REG);
+ can_outb(0x20, candev->io_addr+TSCAN1_MOD_REG);
can_release_io_region(candev->io_addr, TSXXX_IO_RANGE);
return 0;
return -ENODEV;
do {
- if (inb(remap_io_addr+TSXXX_ID0_REG)!=TSCAN1_ID0 ||
- inb(remap_io_addr+TSXXX_ID1_REG)!=TSCAN1_ID1)
+ if (can_inb(remap_io_addr+TSXXX_ID0_REG)!=TSCAN1_ID0 ||
+ can_inb(remap_io_addr+TSXXX_ID1_REG)!=TSCAN1_ID1)
break;
- outb(0x00, remap_io_addr+TSCAN1_WIN_REG);
- outb(0x20, remap_io_addr+TSCAN1_MOD_REG);
+ can_outb(0x00, remap_io_addr+TSCAN1_WIN_REG);
+ can_outb(0x20, remap_io_addr+TSCAN1_MOD_REG);
if(pjmp)
- *pjmp = inb(remap_io_addr+TSCAN1_JMP_REG);
+ *pjmp = can_inb(remap_io_addr+TSCAN1_JMP_REG);
result = 0;
} while (0);
return -ENODEV;
do {
- if (inb(remap_io_addr+TSXXX_ID0_REG)!=TS7KV_ID0 ||
- inb(remap_io_addr+TSXXX_ID1_REG)!=TS7KV_ID1)
+ if (can_inb(remap_io_addr+TSXXX_ID0_REG)!=TS7KV_ID0 ||
+ can_inb(remap_io_addr+TSXXX_ID1_REG)!=TS7KV_ID1)
break;
if(pjmp)
- *pjmp = inb(remap_io_addr+TS7KV_JMP_REG);
+ *pjmp = can_inb(remap_io_addr+TS7KV_JMP_REG);
result = 0;
} while (0);
* Return Value: The function does not return a value
* File: src/tscan1.c
*/
-void tscan1_write_register(unsigned data, unsigned long address)
+void tscan1_write_register(unsigned data, can_ioptr_t address)
{
- outb(data, address);
+ can_outb(data, address);
}
-void ts7kv_write_register(unsigned data, unsigned long address)
+void ts7kv_write_register(unsigned data, can_ioptr_t address)
{
- unsigned long base = address & ~0x1f;
+ unsigned long addr=can_ioptr2ulong(address);
+ can_ioptr_t base = can_ulong2ioptr(addr & ~0x1f);
unsigned char nwin = 0x10;
unsigned char savewin;
can_spin_irqflags_t flags;
- if((address&0x1f) > 0x1d) {
+ if((addr&0x1f) > 0x1d) {
nwin++;
address -= 0x10;
}
can_spin_lock_irqsave(&ts7kv_win_lock,flags);
- savewin = inb(base+TS7KV_WIN_REG);
+ savewin = can_inb(base+TS7KV_WIN_REG);
if(nwin == savewin) {
- outb(data, address);
+ can_outb(data, address);
}else{
- outb(nwin, base+TS7KV_WIN_REG);
- outb(data, address);
- outb(savewin, base+TS7KV_WIN_REG);
+ can_outb(nwin, base+TS7KV_WIN_REG);
+ can_outb(data, address);
+ can_outb(savewin, base+TS7KV_WIN_REG);
}
can_spin_unlock_irqrestore(&ts7kv_win_lock,flags);
}
* Return Value: The function returns the value stored in @address
* File: src/tscan1.c
*/
-unsigned tscan1_read_register(unsigned long address)
+unsigned tscan1_read_register(can_ioptr_t address)
{
- return inb(address);
+ return can_inb(address);
}
-unsigned ts7kv_read_register(unsigned long address)
+unsigned ts7kv_read_register(can_ioptr_t address)
{
- unsigned long base = address & ~0x1f;
+ unsigned long addr=can_ioptr2ulong(address);
+ can_ioptr_t base = can_ulong2ioptr(addr & ~0x1f);
unsigned char nwin = 0x10;
unsigned char savewin;
unsigned val;
can_spin_irqflags_t flags;
- if((address&0x1f) > 0x1d) {
+ if((addr&0x1f) > 0x1d) {
nwin++;
address -= 0x10;
}
can_spin_lock_irqsave(&ts7kv_win_lock,flags);
- savewin = inb(base+TS7KV_WIN_REG);
+ savewin = can_inb(base+TS7KV_WIN_REG);
if(nwin == savewin) {
- val = inb(address);
+ val = can_inb(address);
}else{
- outb(nwin, base+TS7KV_WIN_REG);
- val = inb(address);
- outb(savewin, base+TS7KV_WIN_REG);
+ can_outb(nwin, base+TS7KV_WIN_REG);
+ val = can_inb(address);
+ can_outb(savewin, base+TS7KV_WIN_REG);
}
can_spin_unlock_irqrestore(&ts7kv_win_lock,flags);
*/
int unican_request_io(struct candevice_t *candev)
{
- unsigned long remap_addr;
+ can_ioptr_t remap_addr;
if (!can_request_mem_region(candev->io_addr,IO_RANGE,DEVICE_NAME " - unican")) {
CANMSG("Unable to request IO-memory: 0x%lx\n",candev->io_addr);
return -ENODEV;
}
- if ( !( remap_addr = (long) ioremap( candev->io_addr, IO_RANGE ) ) ) {
+ if ( !( remap_addr = ioremap( candev->io_addr, IO_RANGE ) ) ) {
CANMSG("Unable to access I/O memory at: 0x%lx\n", candev->io_addr);
can_release_mem_region(candev->io_addr,IO_RANGE);
return -ENODEV;
*/
int unican_release_io(struct candevice_t *candev)
{
- iounmap((void*)candev->dev_base_addr);
+ iounmap(candev->dev_base_addr);
can_release_mem_region(candev->io_addr,IO_RANGE);
return 0;
}
chip->int_clk_reg = 0x0;
chip->int_bus_reg = 0x0;
chip->max_objects = 1;
- chip->chip_base_addr=candev->io_addr;
+ chip->chip_base_addr=candev->dev_base_addr;
CANMSG("initializing unican chip operations\n");
chip->chipspecops->chip_config=unican_chip_config;
int unican_pci_request_io(struct candevice_t *candev)
{
- unsigned long remap_addr;
+ can_ioptr_t remap_addr;
#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))
if(pci_request_region(candev->sysdevptr.pcidev, 0, "unican_pci") != 0){
}
#endif /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
- candev->dev_base_addr=pci_resource_start(candev->sysdevptr.pcidev,0);
- candev->io_addr=candev->dev_base_addr;
- candev->res_addr=candev->dev_base_addr;
+ candev->io_addr=pci_resource_start(candev->sysdevptr.pcidev,0);
+ candev->res_addr=candev->io_addr;
- if ( !( remap_addr = (long) ioremap( candev->io_addr, IO_RANGE ) ) ) {
+ if ( !( remap_addr = ioremap( candev->io_addr, IO_RANGE ) ) ) {
CANMSG("Unable to access I/O memory at: 0x%lx\n", candev->io_addr);
#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))
pci_release_region(candev->sysdevptr.pcidev, 0);
can_base_addr_fixup(candev, remap_addr);
DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", candev->io_addr, candev->io_addr + IO_RANGE - 1);
DEBUGMSG("VMA: dev_base_addr: 0x%lx chip_base_addr: 0x%lx\n",
- candev->dev_base_addr, candev->chip[0]->chip_base_addr);
+ can_ioptr2ulong(candev->dev_base_addr),
+ can_ioptr2ulong(candev->chip[0]->chip_base_addr));
return 0;
}
int unican_pci_release_io(struct candevice_t *candev)
{
- iounmap((void*)candev->dev_base_addr);
+ iounmap(candev->dev_base_addr);
#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))
pci_release_region(candev->sysdevptr.pcidev, 0);
#else /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
printk(KERN_CRIT "Unican PCI region 0 is not MEM\n");
return -EIO;
}
- candev->dev_base_addr=pci_resource_start(pcidev,0);
- candev->io_addr=candev->dev_base_addr;
- candev->res_addr=candev->dev_base_addr;
+ candev->io_addr=pci_resource_start(pcidev,0);
+ candev->res_addr=candev->io_addr;
+ candev->dev_base_addr=NULL;
/*candev->flags |= CANDEV_PROGRAMMABLE_IRQ;*/
projects / lincan.git / commitdiff