Change not checked on real hardware.
DEBUGMSG("starting interrupt on chip 1\n");
it_mask=8;
}
DEBUGMSG("starting interrupt on chip 1\n");
it_mask=8;
}
- candev=(struct candevice_t *)chip->chip_data;
+ candev=chip->hostdevice;
it_reg = ioread32( (void*)(candev->io_addr+PLX_INTCSR));
it_reg|=it_mask|0x40;
iowrite32(it_reg,(void*)(candev->io_addr+PLX_INTCSR));
it_reg = ioread32( (void*)(candev->io_addr+PLX_INTCSR));
it_reg|=it_mask|0x40;
iowrite32(it_reg,(void*)(candev->io_addr+PLX_INTCSR));
DEBUGMSG("stoping interrupt on chip 1\n");
it_mask=8;
}
DEBUGMSG("stoping interrupt on chip 1\n");
it_mask=8;
}
- candev=(struct candevice_t *)chip->chip_data;
+ candev=chip->hostdevice;
it_reg = ioread32( (void*)(candev->io_addr+PLX_INTCSR));
it_reg&=~it_mask;
iowrite32(it_reg,(void*)(candev->io_addr+PLX_INTCSR));
it_reg = ioread32( (void*)(candev->io_addr+PLX_INTCSR));
it_reg&=~it_mask;
iowrite32(it_reg,(void*)(candev->io_addr+PLX_INTCSR));
DEBUGMSG("starting chip 1\n");
it_mask=8;
}
DEBUGMSG("starting chip 1\n");
it_mask=8;
}
- candev=(struct candevice_t *)chip->chip_data;
+ candev=chip->hostdevice;
it_reg = ioread32( (void*)(candev->io_addr+PLX_INTCSR));
rmb();
it_reg|=it_mask|0x40;
it_reg = ioread32( (void*)(candev->io_addr+PLX_INTCSR));
rmb();
it_reg|=it_mask|0x40;
DEBUGMSG("stoping chip 1\n");
it_mask=8;
}
DEBUGMSG("stoping chip 1\n");
it_mask=8;
}
- candev=(struct candevice_t *)chip->chip_data;
+ candev=chip->hostdevice;
it_reg = ioread32( (void*)(candev->io_addr+PLX_INTCSR));
rmb();
it_reg&=~it_mask;
it_reg = ioread32( (void*)(candev->io_addr+PLX_INTCSR));
rmb();
it_reg&=~it_mask;
int retcode;
unsigned long it_reg;
struct candevice_t *candev;
int retcode;
unsigned long it_reg;
struct candevice_t *candev;
- candev=(struct candevice_t *)chip->chip_data;
+ candev=chip->hostdevice;
retcode = CANCHIP_IRQ_NONE;
it_reg = ioread32( (void*)(candev->io_addr+PLX_INTCSR));
rmb();
retcode = CANCHIP_IRQ_NONE;
it_reg = ioread32( (void*)(candev->io_addr+PLX_INTCSR));
rmb();
candev->chip[chipnr]->chipspecops->stop_chip=nsi_canpci_stop_chip;
candev->chip[chipnr]->chipspecops->config_irqs=nsi_canpci_config_irqs;
candev->chip[chipnr]->chipspecops->irq_handler=nsi_canpci_irq_handler;
candev->chip[chipnr]->chipspecops->stop_chip=nsi_canpci_stop_chip;
candev->chip[chipnr]->chipspecops->config_irqs=nsi_canpci_config_irqs;
candev->chip[chipnr]->chipspecops->irq_handler=nsi_canpci_irq_handler;
- candev->chip[chipnr]->chip_data =candev;
+ /*candev->chip[chipnr]->chip_data = NULL;*/
candev->chip[chipnr]->chip_base_addr= (unsigned long) (((t_CardArray*)(candev->dev_base_addr))->addr_BAR_remap[chipnr+2]);
candev->chip[chipnr]->clock = iCLOCK;
candev->chip[chipnr]->chip_base_addr= (unsigned long) (((t_CardArray*)(candev->dev_base_addr))->addr_BAR_remap[chipnr+2]);
candev->chip[chipnr]->clock = iCLOCK;
*/
unsigned nsi_canpci_read_register(unsigned long address)
{
*/
unsigned nsi_canpci_read_register(unsigned long address)
{
- /* this is the same thing that the function write_register.
- We use the two register, we write the address where we
- want to read in a first time. In a second time we read the
- data */
return ioread8((void*)address);
}
return ioread8((void*)address);
}