Changed to solve ARM-linux kernel and LinCAN name collision.
/* Command register */
enum sja1000_BASIC_CMR {
- CMR_TR = 1, // Transmission request
- CMR_AT = 1<<1, // Abort Transmission
- CMR_RRB = 1<<2, // Release Receive Buffer
- CMR_CDO = 1<<3, // Clear Data Overrun
- CMR_GTS = 1<<4 // Go To Sleep
+ sjaCMR_TR = 1, // Transmission request
+ sjaCMR_AT = 1<<1, // Abort Transmission
+ sjaCMR_RRB = 1<<2, // Release Receive Buffer
+ sjaCMR_CDO = 1<<3, // Clear Data Overrun
+ sjaCMR_GTS = 1<<4 // Go To Sleep
};
/* Status Register */
enum sja1000_BASIC_SR {
- SR_RBS = 1, // Receive Buffer Status
- SR_DOS = 1<<1, // Data Overrun Status
- SR_TBS = 1<<2, // Transmit Buffer Status
- SR_TCS = 1<<3, // Transmission Complete Status
- SR_RS = 1<<4, // Receive Status
- SR_TS = 1<<5, // Transmit Status
- SR_ES = 1<<6, // Error Status
- SR_BS = 1<<7 // Bus Status
+ sjaSR_RBS = 1, // Receive Buffer Status
+ sjaSR_DOS = 1<<1, // Data Overrun Status
+ sjaSR_TBS = 1<<2, // Transmit Buffer Status
+ sjaSR_TCS = 1<<3, // Transmission Complete Status
+ sjaSR_RS = 1<<4, // Receive Status
+ sjaSR_TS = 1<<5, // Transmit Status
+ sjaSR_ES = 1<<6, // Error Status
+ sjaSR_BS = 1<<7 // Bus Status
};
/* Control Register */
enum sja1000_BASIC_CR {
- CR_RR = 1, // Reset Request
- CR_RIE = 1<<1, // Receive Interrupt Enable
- CR_TIE = 1<<2, // Transmit Interrupt Enable
- CR_EIE = 1<<3, // Error Interrupt Enable
- CR_OIE = 1<<4 // Overrun Interrupt Enable
+ sjaCR_RR = 1, // Reset Request
+ sjaCR_RIE = 1<<1, // Receive Interrupt Enable
+ sjaCR_TIE = 1<<2, // Transmit Interrupt Enable
+ sjaCR_EIE = 1<<3, // Error Interrupt Enable
+ sjaCR_OIE = 1<<4 // Overrun Interrupt Enable
};
/* Interrupt (status) Register */
enum sja1000_BASIC_IR {
- IR_RI = 1, // Receive Interrupt
- IR_TI = 1<<1, // Transmit Interrupt
- IR_EI = 1<<2, // Error Interrupt
- IR_DOI = 1<<3, // Data Overrun Interrupt
- IR_WUI = 1<<4 // Wake-Up Interrupt
+ sjaIR_RI = 1, // Receive Interrupt
+ sjaIR_TI = 1<<1, // Transmit Interrupt
+ sjaIR_EI = 1<<2, // Error Interrupt
+ sjaIR_DOI = 1<<3, // Data Overrun Interrupt
+ sjaIR_WUI = 1<<4 // Wake-Up Interrupt
};
/* Clock Divider Register */
enum sja1000_CDR {
/* f_out = f_osc/(2*(CDR[2:0]+1)) or f_osc if CDR[2:0]==7 */
- CDR_CLKOUT_MASK = 7,
- CDR_CLK_OFF = 1<<3, // Clock Off
- CDR_RXINPEN = 1<<5, // TX1 output is RX irq output
- CDR_CBP = 1<<6, // Input Comparator By-Pass
- CDR_PELICAN = 1<<7 // PeliCAN Mode
+ sjaCDR_CLKOUT_MASK = 7,
+ sjaCDR_CLK_OFF = 1<<3, // Clock Off
+ sjaCDR_RXINPEN = 1<<5, // TX1 output is RX irq output
+ sjaCDR_CBP = 1<<6, // Input Comparator By-Pass
+ sjaCDR_PELICAN = 1<<7 // PeliCAN Mode
};
/* Output Control Register */
enum sja1000_OCR {
- OCR_MODE_BIPHASE = 0,
- OCR_MODE_TEST = 1,
- OCR_MODE_NORMAL = 2,
- OCR_MODE_CLOCK = 3,
+ sjaOCR_MODE_BIPHASE = 0,
+ sjaOCR_MODE_TEST = 1,
+ sjaOCR_MODE_NORMAL = 2,
+ sjaOCR_MODE_CLOCK = 3,
// TX0 push-pull not inverted
- OCR_TX0_LH = 0x18,
+ sjaOCR_TX0_LH = 0x18,
// TX0 push-pull inverted
- OCR_TX0_HL = 0x1c,
+ sjaOCR_TX0_HL = 0x1c,
// TX1 floating (off)
- OCR_TX1_ZZ = 0,
+ sjaOCR_TX1_ZZ = 0,
// TX1 pull-down not inverted
- OCR_TX1_LZ = 0x40
+ sjaOCR_TX1_LZ = 0x40
};
/** Frame format information 0x11 */
enum sja1000_BASIC_ID0 {
- ID0_RTR = 1<<4, // Remote request
- ID0_DLC_M = (1<<4)-1 // Length Mask
+ sjaID0_RTR = 1<<4, // Remote request
+ sjaID0_DLC_M = (1<<4)-1 // Length Mask
};
/** Mode Register 0x00 */
enum sja1000_PeliCAN_MOD {
- MOD_SM = 1<<4, // Sleep Mode (writable only in OPERATING mode)
- MOD_AFM= 1<<3, // Acceptance Filter Mode (writable only in RESET)
- MOD_STM= 1<<2, // Self Test Mode (writable only in RESET)
- MOD_LOM= 1<<1, // Listen Only Mode (writable only in RESET)
- MOD_RM = 1 // Reset Mode
+ sjaMOD_SM = 1<<4, // Sleep Mode (writable only in OPERATING mode)
+ sjaMOD_AFM= 1<<3, // Acceptance Filter Mode (writable only in RESET)
+ sjaMOD_STM= 1<<2, // Self Test Mode (writable only in RESET)
+ sjaMOD_LOM= 1<<1, // Listen Only Mode (writable only in RESET)
+ sjaMOD_RM = 1 // Reset Mode
};
/** Command Register 0x01 */
enum sja1000_PeliCAN_CMR {
- CMR_SRR = 1<<4, // Self Reception Request (GoToSleep in BASIC mode)
- CMR_CDO = 1<<3, // Clear Data Overrun
- CMR_RRB = 1<<2, // Release Receive Buffer
- CMR_AT = 1<<1, // Abort Transmission
- CMR_TR = 1 }; // Transmission Request
+ sjaCMR_SRR= 1<<4, // Self Reception Request (GoToSleep in BASIC mode)
+ sjaCMR_CDO= 1<<3, // Clear Data Overrun
+ sjaCMR_RRB= 1<<2, // Release Receive Buffer
+ sjaCMR_AT = 1<<1, // Abort Transmission
+ sjaCMR_TR = 1 }; // Transmission Request
/** Status Register 0x02 */
enum sja1000_SR {
- SR_BS = 1<<7, // Bus Status
- SR_ES = 1<<6, // Error Status
- SR_TS = 1<<5, // Transmit Status
- SR_RS = 1<<4, // Receive Status
- SR_TCS = 1<<3, // Transmission Complete Status
- SR_TBS = 1<<2, // Transmit Buffer Status
- SR_DOS = 1<<1, // Data Overrun Status
- SR_RBS = 1 }; // Receive Buffer Status
+ sjaSR_BS = 1<<7, // Bus Status
+ sjaSR_ES = 1<<6, // Error Status
+ sjaSR_TS = 1<<5, // Transmit Status
+ sjaSR_RS = 1<<4, // Receive Status
+ sjaSR_TCS = 1<<3, // Transmission Complete Status
+ sjaSR_TBS = 1<<2, // Transmit Buffer Status
+ sjaSR_DOS = 1<<1, // Data Overrun Status
+ sjaSR_RBS = 1 }; // Receive Buffer Status
/** Interrupt Enable Register 0x04 */
enum sja1000_PeliCAN_IER {
- IER_BEIE= 1<<7, // Bus Error Interrupt Enable
- IER_ALIE= 1<<6, // Arbitration Lost Interrupt Enable
- IER_EPIE= 1<<5, // Error Passive Interrupt Enable
- IER_WUIE= 1<<4, // Wake-Up Interrupt Enable
- IER_DOIE = 1<<3,// Data Overrun Interrupt Enable
- IER_EIE = 1<<2, // Error Warning Interrupt Enable
- IER_TIE = 1<<1, // Transmit Interrupt Enable
- IER_RIE = 1, // Receive Interrupt Enable
- ENABLE_INTERRUPTS = IER_BEIE|IER_EPIE|IER_DOIE|IER_EIE|IER_TIE|IER_RIE,
- DISABLE_INTERRUPTS = 0
+ sjaIER_BEIE= 1<<7, // Bus Error Interrupt Enable
+ sjaIER_ALIE= 1<<6, // Arbitration Lost Interrupt Enable
+ sjaIER_EPIE= 1<<5, // Error Passive Interrupt Enable
+ sjaIER_WUIE= 1<<4, // Wake-Up Interrupt Enable
+ sjaIER_DOIE= 1<<3, // Data Overrun Interrupt Enable
+ sjaIER_EIE = 1<<2, // Error Warning Interrupt Enable
+ sjaIER_TIE = 1<<1, // Transmit Interrupt Enable
+ sjaIER_RIE = 1, // Receive Interrupt Enable
+ sjaENABLE_INTERRUPTS = sjaIER_BEIE|sjaIER_EPIE|sjaIER_DOIE|sjaIER_EIE|sjaIER_TIE|sjaIER_RIE,
+ sjaDISABLE_INTERRUPTS = 0
// WARNING: the chip automatically enters RESET (bus off) mode when
// error counter > 255
};
/** Arbitration Lost Capture Register 0x0b.
* Counting starts from 0 (bit1 of ID). Bits 5-7 reserved*/
enum sja1000_PeliCAN_ALC {
- ALC_SRTR = 0x0b, // Arbitration lost in bit SRTR
- ALC_IDE = 0x1c, // Arbitration lost in bit IDE
- ALC_RTR = 0x1f, // Arbitration lost in RTR
+ sjaALC_SRTR = 0x0b,// Arbitration lost in bit SRTR
+ sjaALC_IDE = 0x1c, // Arbitration lost in bit IDE
+ sjaALC_RTR = 0x1f, // Arbitration lost in RTR
};
/** Error Code Capture Register 0x0c*/
enum sja1000_PeliCAN_ECC {
- ECC_ERCC1 = 1<<7,
- ECC_ERCC0 = 1<<6,
- ECC_BIT = 0,
- ECC_FORM = ECC_ERCC0,
- ECC_STUFF = ECC_ERCC1,
- ECC_OTHER = ECC_ERCC0 | ECC_ERCC1,
- ECC_DIR = 1<<5, // 1 == RX, 0 == TX
- ECC_SEG_M = (1<<5) -1 // Segment mask, see page 37 of SJA1000 Data Sheet
+ sjaECC_ERCC1 = 1<<7,
+ sjaECC_ERCC0 = 1<<6,
+ sjaECC_BIT = 0,
+ sjaECC_FORM = sjaECC_ERCC0,
+ sjaECC_STUFF = sjaECC_ERCC1,
+ sjaECC_OTHER = sjaECC_ERCC0 | sjaECC_ERCC1,
+ sjaECC_DIR = 1<<5, // 1 == RX, 0 == TX
+ sjaECC_SEG_M = (1<<5) -1 // Segment mask, see page 37 of SJA1000 Data Sheet
};
/** Frame format information 0x10 */
enum sja1000_PeliCAN_FRM {
- FRM_FF = 1<<7, // Frame Format 1 == extended, 0 == standard
- FRM_RTR = 1<<6, // Remote request
- FRM_DLC_M = (1<<4)-1 // Length Mask
+ sjaFRM_FF = 1<<7, // Frame Format 1 == extended, 0 == standard
+ sjaFRM_RTR = 1<<6, // Remote request
+ sjaFRM_DLC_M = (1<<4)-1 // Length Mask
};
/** Interrupt (status) Register 0x03 */
enum sja1000_PeliCAN_IR {
- IR_BEI = 1<<7, // Bus Error Interrupt
- IR_ALI = 1<<6, // Arbitration Lost Interrupt
- IR_EPI = 1<<5, // Error Passive Interrupt (entered error passive state or error active state)
- IR_WUI = 1<<4, // Wake-Up Interrupt
- IR_DOI = 1<<3, // Data Overrun Interrupt
- IR_EI = 1<<2, // Error Interrupt
- IR_TI = 1<<1, // Transmit Interrupt
- IR_RI = 1 // Receive Interrupt
+ sjaIR_BEI = 1<<7, // Bus Error Interrupt
+ sjaIR_ALI = 1<<6, // Arbitration Lost Interrupt
+ sjaIR_EPI = 1<<5, // Error Passive Interrupt (entered error passive state or error active state)
+ sjaIR_WUI = 1<<4, // Wake-Up Interrupt
+ sjaIR_DOI = 1<<3, // Data Overrun Interrupt
+ sjaIR_EI = 1<<2, // Error Interrupt
+ sjaIR_TI = 1<<1, // Transmit Interrupt
+ sjaIR_RI = 1 // Receive Interrupt
};
-#if 0
/** Bus Timing 1 Register 0x07 */
enum sja1000_BTR1 {
- MAX_TSEG1 = 15,
- MAX_TSEG2 = 7
+ sjaMAX_TSEG1 = 15,
+ sjaMAX_TSEG2 = 7
};
-#endif
/** Output Control Register 0x08 */
enum sja1000_OCR {
- OCR_MODE_BIPHASE = 0,
- OCR_MODE_TEST = 1,
- OCR_MODE_NORMAL = 2,
- OCR_MODE_CLOCK = 3,
+ sjaOCR_MODE_BIPHASE = 0,
+ sjaOCR_MODE_TEST = 1,
+ sjaOCR_MODE_NORMAL = 2,
+ sjaOCR_MODE_CLOCK = 3,
/// TX0 push-pull not inverted
- OCR_TX0_LH = 0x18,
+ sjaOCR_TX0_LH = 0x18,
/// TX1 floating (off)
- OCR_TX1_ZZ = 0
+ sjaOCR_TX1_ZZ = 0
};
/** Clock Divider register 0x1f */
enum sja1000_CDR {
- CDR_PELICAN = 1<<7,
+ sjaCDR_PELICAN = 1<<7,
/// bypass input comparator
- CDR_CBP = 1<<6,
+ sjaCDR_CBP = 1<<6,
/// switch TX1 to generate RX INT
- CDR_RXINPEN = 1<<5,
- CDR_CLK_OFF = 1<<3,
+ sjaCDR_RXINPEN = 1<<5,
+ sjaCDR_CLK_OFF = 1<<3,
/// f_out = f_osc/(2*(CDR[2:0]+1)) or f_osc if CDR[2:0]==7
- CDR_CLKOUT_MASK = 7
+ sjaCDR_CLKOUT_MASK = 7
};
/** flags for sja1000_baud_rate */
pc_i03 pcm3680 aim104 m437 pcccan ssv \
bfadcan pikronisa kv_pcican msmcan virtual template \
unican unican_cl2
+# ems_cpcpci
+# hms30c7202_can c_can c_can_irq
+
#SUPPORTED_CARDS = pcm3680 bfadcan pikronisa template
/* Check hardware reset status chip 0 */
i=0;
while ( (aim104_read_register(candev->io_addr + SJACR)
- & CR_RR) && (i<=15) ) {
+ & sjaCR_RR) && (i<=15) ) {
udelay(20000);
i++;
}
* The @clock entry holds the chip clock value in Hz.
* The entry @sja_cdr_reg holds hardware specific options for the Clock Divider
* register. Options defined in the %sja1000.h file:
- * %CDR_CLKOUT_MASK, %CDR_CLK_OFF, %CDR_RXINPEN, %CDR_CBP, %CDR_PELICAN
+ * %sjaCDR_CLKOUT_MASK, %sjaCDR_CLK_OFF, %sjaCDR_RXINPEN, %sjaCDR_CBP, %sjaCDR_PELICAN
* The entry @sja_ocr_reg holds hardware specific options for the Output Control
* register. Options defined in the %sja1000.h file:
- * %OCR_MODE_BIPHASE, %OCR_MODE_TEST, %OCR_MODE_NORMAL, %OCR_MODE_CLOCK,
- * %OCR_TX0_LH, %OCR_TX1_ZZ.
+ * %sjaOCR_MODE_BIPHASE, %sjaOCR_MODE_TEST, %sjaOCR_MODE_NORMAL, %sjaOCR_MODE_CLOCK,
+ * %sjaOCR_TX0_LH, %sjaOCR_TX1_ZZ.
* The entry @int_clk_reg holds hardware specific options for the Clock Out
* register. Options defined in the %i82527.h file:
* %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1.
struct chip_t *chip=candev->chip[0];
unsigned cdr;
- bfadcan_write_register(MOD_RM, chip->chip_base_addr+SJAMOD);
+ bfadcan_write_register(sjaMOD_RM, chip->chip_base_addr+SJAMOD);
udelay(1000);
cdr=bfadcan_read_register(chip->chip_base_addr+SJACDR);
- bfadcan_write_register(cdr|CDR_PELICAN, chip->chip_base_addr+SJACDR);
+ bfadcan_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
bfadcan_write_register(0, chip->chip_base_addr+SJAIER);
i=20;
bfadcan_write_register(0, chip->chip_base_addr+SJAMOD);
- while (bfadcan_read_register(chip->chip_base_addr+SJAMOD)&MOD_RM){
+ while (bfadcan_read_register(chip->chip_base_addr+SJAMOD)&sjaMOD_RM){
if(!i--) return -ENODEV;
udelay(1000);
bfadcan_write_register(0, chip->chip_base_addr+SJAMOD);
}
cdr=bfadcan_read_register(chip->chip_base_addr+SJACDR);
- bfadcan_write_register(cdr|CDR_PELICAN, chip->chip_base_addr+SJACDR);
+ bfadcan_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
bfadcan_write_register(0, chip->chip_base_addr+SJAIER);
* The @clock entry holds the chip clock value in Hz.
* The entry @sja_cdr_reg holds hardware specific options for the Clock Divider
* register. Options defined in the %sja1000.h file:
- * %CDR_CLKOUT_MASK, %CDR_CLK_OFF, %CDR_RXINPEN, %CDR_CBP, %CDR_PELICAN
+ * %sjaCDR_CLKOUT_MASK, %sjaCDR_CLK_OFF, %sjaCDR_RXINPEN, %sjaCDR_CBP, %sjaCDR_PELICAN
* The entry @sja_ocr_reg holds hardware specific options for the Output Control
* register. Options defined in the %sja1000.h file:
- * %OCR_MODE_BIPHASE, %OCR_MODE_TEST, %OCR_MODE_NORMAL, %OCR_MODE_CLOCK,
- * %OCR_TX0_LH, %OCR_TX1_ZZ.
+ * %sjaOCR_MODE_BIPHASE, %sjaOCR_MODE_TEST, %sjaOCR_MODE_NORMAL, %sjaOCR_MODE_CLOCK,
+ * %sjaOCR_TX0_LH, %sjaOCR_TX1_ZZ.
* The entry @int_clk_reg holds hardware specific options for the Clock Out
* register. Options defined in the %i82527.h file:
* %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1.
candev->chip[chipnr]->int_cpu_reg = iCPU_DSC;
candev->chip[chipnr]->int_clk_reg = iCLK_SL1;
candev->chip[chipnr]->int_bus_reg = iBUS_CBY;
- candev->chip[chipnr]->sja_cdr_reg = CDR_CBP | CDR_CLK_OFF;
- candev->chip[chipnr]->sja_ocr_reg = OCR_MODE_NORMAL |
- OCR_TX0_LH;
+ candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CBP | sjaCDR_CLK_OFF;
+ candev->chip[chipnr]->sja_ocr_reg = sjaOCR_MODE_NORMAL |
+ sjaOCR_TX0_LH;
id1 = inb(0xe284);
id2 = inb(0xe285);
{
int i=0;
u16 flags;
- DEBUGMSG("(c%d)calling c_can_enable_configuration(...)\n", pchip->chip_nr);
+ DEBUGMSG("(c%d)calling c_can_enable_configuration(...)\n", pchip->chip_idx);
/*
DEBUGMSG("Trying disable_irq(...) : ");
//disable IRQ
int i=0;
u16 flags;
- DEBUGMSG("(c%d)calling c_can_disable_configuration(...)\n", pchip->chip_nr);
+ DEBUGMSG("(c%d)calling c_can_disable_configuration(...)\n", pchip->chip_idx);
//read Control Register
flags=c_can_read_reg_w(pchip, CCCR);
int c_can_chip_config(struct chip_t *pchip)
{
- DEBUGMSG("(c%d)calling c_can_chip_config(...)\n", pchip->chip_nr);
+ DEBUGMSG("(c%d)calling c_can_chip_config(...)\n", pchip->chip_idx);
// Validate pointer
if ( NULL == pchip ) return -1;
unsigned short tempCR = 0;
- DEBUGMSG("(c%d)calling c_can_baud_rate(...)\n", pchip->chip_nr);
+ DEBUGMSG("(c%d)calling c_can_baud_rate(...)\n", pchip->chip_idx);
if (c_can_enable_configuration(pchip))
return -ENODEV;
unsigned short readMaskCM;
unsigned short writeMaskCM;
- DEBUGMSG("(c%dm%d)calling c_can_mask(...)\n", pmsgobj->hostchip->chip_nr, pmsgobj->object);
+ DEBUGMSG("(c%dm%d)calling c_can_mask(...)\n", pmsgobj->hostchip->chip_idx, pmsgobj->object);
readMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_MASK;
writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_MASK | IFXCM_WRRD;
char *boolstring = "false";
if (useflag) boolstring = "true";
#endif
- DEBUGMSG("(c%dm%d)calling c_can_use_mask(...)\n", pmsgobj->hostchip->chip_nr, pmsgobj->object);
+ DEBUGMSG("(c%dm%d)calling c_can_use_mask(...)\n", pmsgobj->hostchip->chip_idx, pmsgobj->object);
readMaskCM = IFXCM_CNTRL | IFXCM_ARB;
writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_WRRD;;
unsigned short maskCM = IFXCM_ARB;
- DEBUGMSG("(c%d)calling c_can_clear_objects(...)\n", pchip->chip_nr);
+ DEBUGMSG("(c%d)calling c_can_clear_objects(...)\n", pchip->chip_idx);
spin_lock( &c_can_if1lock );
spin_lock( &c_can_if2lock );
{
u16 tempreg;
- DEBUGMSG("(c%d)calling c_can_config_irqs(...)\n", pchip->chip_nr);
+ DEBUGMSG("(c%d)calling c_can_config_irqs(...)\n", pchip->chip_idx);
/*
CANMSG("c_can_config_irqs not implemented\n");
unsigned short mcreg = 0;
u32 id=pmsgobj->rx_preconfig_id;
- DEBUGMSG("(c%dm%d)calling c_can_pre_read_config(...)\n", pmsgobj->hostchip->chip_nr, pmsgobj->object);
+ DEBUGMSG("(c%dm%d)calling c_can_pre_read_config(...)\n", pmsgobj->hostchip->chip_idx, pmsgobj->object);
spin_lock( &c_can_if1lock );
unsigned short dataB1 = 0;
unsigned short dataB2 = 0;
- DEBUGMSG("(c%dm%d)calling c_can_send_msg(...)\n", pmsgobj->hostchip->chip_nr, pmsgobj->object);
+ DEBUGMSG("(c%dm%d)calling c_can_send_msg(...)\n", pmsgobj->hostchip->chip_idx, pmsgobj->object);
spin_lock( &c_can_if2lock );
//unsigned short writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_WRRD;
unsigned short mcreg = 0;
- DEBUGMSG("(c%dm%d)calling c_can_remote_request(...)\n", pmsgobj->hostchip->chip_nr, pmsgobj->object);
+ DEBUGMSG("(c%dm%d)calling c_can_remote_request(...)\n", pmsgobj->hostchip->chip_idx, pmsgobj->object);
//Remote request is only available when the message object is in receiving mode
if (!can_msgobj_test_fl(pmsgobj,RX_MODE))
{
unsigned short tempCR = 0;
- DEBUGMSG("(c%d)calling c_can_set_btregs(...)\n", pchip->chip_nr);
+ DEBUGMSG("(c%d)calling c_can_set_btregs(...)\n", pchip->chip_idx);
// Validate pointer
if ( NULL == pchip ) return -1;
{
u16 flags = 0;
- DEBUGMSG("(c%d)calling c_can_start_chip(...)\n", pchip->chip_nr);
+ DEBUGMSG("(c%d)calling c_can_start_chip(...)\n", pchip->chip_idx);
// Validate pointer
if ( NULL == pchip )
{
u16 flags = 0;
- DEBUGMSG("(c%d)calling c_can_stop_chip(...)\n", pchip->chip_nr);
+ DEBUGMSG("(c%d)calling c_can_stop_chip(...)\n", pchip->chip_idx);
// Validate pointer
if ( NULL == pchip )
{
unsigned long tempstat = 0;
- DEBUGMSG("(c%d)calling c_can_check_tx_stat(...)\n", pchip->chip_nr);
+ DEBUGMSG("(c%d)calling c_can_check_tx_stat(...)\n", pchip->chip_idx);
// Validate pointer
if ( NULL == pchip ) return -1;
/*int c_can_register(struct chip_t *pchip)
{
- DEBUGMSG("(c%d)call c_can_register\n", pchip->chip_nr);
+ DEBUGMSG("(c%d)call c_can_register\n", pchip->chip_idx);
// Validate pointer
if ( NULL == pchip ) return -1;
}
DEBUGMSG("(c%dm%d)Received Message:\n",
pchip->chip_idx, pmsgobj->object);
- DEBUGMSG(" id = %d\n",
+ DEBUGMSG(" id = %ld\n",
pmsgobj->rx_msg.id);
DEBUGMSG(" length = %d\n",
pmsgobj->rx_msg.length);
if(!irqreg) {
DEBUGMSG( "\n(c%d)IRQ handler: addr=%.8lx spurious interrupt\n",
pchip->chip_idx,
- (long)( pchip->/*v*/base_addr/* + CCSR*/));
+ (long)( pchip->/*v*/chip_base_addr/* + CCSR*/));
return CAN_IRQ_NONE;
}
DEBUGMSG( "\n(c%d)IRQ handler: addr=%.8lx irqreg=0x%.4x\n",
pchip->chip_idx,
- (long)( pchip->/*v*/base_addr/* + CCSR*/),
+ (long)( pchip->/*v*/chip_base_addr/* + CCSR*/),
irqreg);
* The @clock entry holds the chip clock value in Hz.
* The entry @sja_cdr_reg holds hardware specific options for the Clock Divider
* register. Options defined in the %sja1000.h file:
- * %CDR_CLKOUT_MASK, %CDR_CLK_OFF, %CDR_RXINPEN, %CDR_CBP, %CDR_PELICAN
+ * %sjaCDR_CLKOUT_MASK, %sjaCDR_CLK_OFF, %sjaCDR_RXINPEN, %sjaCDR_CBP, %sjaCDR_PELICAN
* The entry @sja_ocr_reg holds hardware specific options for the Output Control
* register. Options defined in the %sja1000.h file:
- * %OCR_MODE_BIPHASE, %OCR_MODE_TEST, %OCR_MODE_NORMAL, %OCR_MODE_CLOCK,
- * %OCR_TX0_LH, %OCR_TX1_ZZ.
+ * %sjaOCR_MODE_BIPHASE, %sjaOCR_MODE_TEST, %sjaOCR_MODE_NORMAL, %sjaOCR_MODE_CLOCK,
+ * %sjaOCR_TX0_LH, %sjaOCR_TX1_ZZ.
* The entry @int_clk_reg holds hardware specific options for the Clock Out
* register. Options defined in the %i82527.h file:
* %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1.
candev->chip[chipnr]->chip_base_addr=candev->io_addr;
candev->chip[chipnr]->clock = 16000000;
candev->chip[chipnr]->flags = 0;
- candev->chip[chipnr]->sja_cdr_reg = CDR_CBP | CDR_CLK_OFF;
- candev->chip[chipnr]->sja_ocr_reg = OCR_MODE_NORMAL |
- OCR_TX0_LH;
+ candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CBP | sjaCDR_CLK_OFF;
+ candev->chip[chipnr]->sja_ocr_reg = sjaOCR_MODE_NORMAL |
+ sjaOCR_TX0_LH;
return 0;
}
{
address += ((address&(EMS_CPCPCI_BYTES_PER_CIRCUIT-1))
*(EMS_CPCPCI_BYTES_PER_REG-1));
- readb(data,address);
+ writeb(data,address);
}
unsigned ems_cpcpci_read_register(unsigned long address)
{
address += ((address&(EMS_CPCPCI_BYTES_PER_CIRCUIT-1))
*(EMS_CPCPCI_BYTES_PER_REG-1));
- return inb(address);
+ return readb(address);
}
int ems_cpcpci_reset(struct candevice_t *candev)
if(!candev->chip[chip_nr]) continue;
chip=candev->chip[chip_nr];
- ems_cpcpci_write_register(MOD_RM, chip->chip_base_addr+SJAMOD);
+ ems_cpcpci_write_register(sjaMOD_RM, chip->chip_base_addr+SJAMOD);
udelay(1000);
cdr=ems_cpcpci_read_register(chip->chip_base_addr+SJACDR);
- ems_cpcpci_write_register(cdr|CDR_PELICAN, chip->chip_base_addr+SJACDR);
+ ems_cpcpci_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
ems_cpcpci_write_register(0, chip->chip_base_addr+SJAIER);
i=20;
ems_cpcpci_write_register(0, chip->chip_base_addr+SJAMOD);
- while (ems_cpcpci_read_register(chip->chip_base_addr+SJAMOD)&MOD_RM){
+ while (ems_cpcpci_read_register(chip->chip_base_addr+SJAMOD)&sjaMOD_RM){
if(!i--) return -ENODEV;
udelay(1000);
ems_cpcpci_write_register(0, chip->chip_base_addr+SJAMOD);
}
cdr=ems_cpcpci_read_register(chip->chip_base_addr+SJACDR);
- ems_cpcpci_write_register(cdr|CDR_PELICAN, chip->chip_base_addr+SJACDR);
+ ems_cpcpci_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
ems_cpcpci_write_register(0, chip->chip_base_addr+SJAIER);
candev->chip[chipnr]->int_cpu_reg = 0;
candev->chip[chipnr]->int_clk_reg = 0;
candev->chip[chipnr]->int_bus_reg = 0;
- candev->chip[chipnr]->sja_cdr_reg = CDR_CBP | CDR_CLK_OFF;
+ candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CBP | sjaCDR_CLK_OFF;
candev->chip[chipnr]->sja_ocr_reg = EMS_CPCPCI_OCR_DEFAULT_STD;
candev->chip[chipnr]->clock = 8000000;
candev->chip[chipnr]->flags |= CHIP_IRQ_PCI;
*/
int hms30c7202_request_io(struct candevice_t *candev)
{
- DEBUGMSG("(c%d)calling hms30c7202_request_io(...)\n", pchip->chip_nr);
+ DEBUGMSG("(c%d)calling hms30c7202_request_io(...)\n", candev->chip[0]->chip_idx);
if(!can_request_mem_region(candev->io_addr, IO_RANGE, DEVICE_NAME )) {
CANMSG("hmsc30c7202_can failed to request mem region %lx.\n",
int hms30c7202_init_obj_data(struct chip_t *chip, int objnr)
{
- DEBUGMSG("(c%d)calling hms30c7202_init_obj_data( ...)\n", pchip->chip_nr);
+ DEBUGMSG("(c%d)calling hms30c7202_init_obj_data( ...)\n", chip->chip_idx);
/* It seems, that there is no purpose to setup object base address */
chip->msgobj[objnr]->obj_base_addr=0;
if(!candev->chip[chip_nr]) continue;
chip=candev->chip[chip_nr];
- kv_pcican_write_register(MOD_RM, chip->chip_base_addr+SJAMOD);
+ kv_pcican_write_register(sjaMOD_RM, chip->chip_base_addr+SJAMOD);
udelay(1000);
cdr=kv_pcican_read_register(chip->chip_base_addr+SJACDR);
- kv_pcican_write_register(cdr|CDR_PELICAN, chip->chip_base_addr+SJACDR);
+ kv_pcican_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
kv_pcican_write_register(0, chip->chip_base_addr+SJAIER);
i=20;
kv_pcican_write_register(0, chip->chip_base_addr+SJAMOD);
- while (kv_pcican_read_register(chip->chip_base_addr+SJAMOD)&MOD_RM){
+ while (kv_pcican_read_register(chip->chip_base_addr+SJAMOD)&sjaMOD_RM){
if(!i--) return -ENODEV;
udelay(1000);
kv_pcican_write_register(0, chip->chip_base_addr+SJAMOD);
}
cdr=kv_pcican_read_register(chip->chip_base_addr+SJACDR);
- kv_pcican_write_register(cdr|CDR_PELICAN, chip->chip_base_addr+SJACDR);
+ kv_pcican_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
kv_pcican_write_register(0, chip->chip_base_addr+SJAIER);
candev->chip[chipnr]->int_cpu_reg = 0;
candev->chip[chipnr]->int_clk_reg = 0;
candev->chip[chipnr]->int_bus_reg = 0;
- candev->chip[chipnr]->sja_cdr_reg = CDR_CBP | CDR_CLK_OFF;
+ candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CBP | sjaCDR_CLK_OFF;
candev->chip[chipnr]->sja_ocr_reg = KV_PCICAN_OCR_DEFAULT_STD;
candev->chip[chipnr]->clock = 16000000;
candev->chip[chipnr]->flags |= CHIP_IRQ_PCI;
* The @clock entry holds the chip clock value in Hz.
* The entry @sja_cdr_reg holds hardware specific options for the Clock Divider
* register. Options defined in the %sja1000.h file:
- * %CDR_CLKOUT_MASK, %CDR_CLK_OFF, %CDR_RXINPEN, %CDR_CBP, %CDR_PELICAN
+ * %sjaCDR_CLKOUT_MASK, %sjaCDR_CLK_OFF, %sjaCDR_RXINPEN, %sjaCDR_CBP, %sjaCDR_PELICAN
* The entry @sja_ocr_reg holds hardware specific options for the Output Control
* register. Options defined in the %sja1000.h file:
- * %OCR_MODE_BIPHASE, %OCR_MODE_TEST, %OCR_MODE_NORMAL, %OCR_MODE_CLOCK,
- * %OCR_TX0_LH, %OCR_TX1_ZZ.
+ * %sjaOCR_MODE_BIPHASE, %sjaOCR_MODE_TEST, %sjaOCR_MODE_NORMAL, %sjaOCR_MODE_CLOCK,
+ * %sjaOCR_TX0_LH, %sjaOCR_TX1_ZZ.
* The entry @int_clk_reg holds hardware specific options for the Clock Out
* register. Options defined in the %i82527.h file:
* %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1.
/* Check hardware reset status */
i=0;
- while ( (pci03_read_register(pci03_base_addr + SJACR) & CR_RR)
+ while ( (pci03_read_register(pci03_base_addr + SJACR) & sjaCR_RR)
&& (i<=15) ) {
udelay(20000);
i++;
* The @clock entry holds the chip clock value in Hz.
* The entry @sja_cdr_reg holds hardware specific options for the Clock Divider
* register. Options defined in the %sja1000.h file:
- * %CDR_CLKOUT_MASK, %CDR_CLK_OFF, %CDR_RXINPEN, %CDR_CBP, %CDR_PELICAN
+ * %sjaCDR_CLKOUT_MASK, %sjaCDR_CLK_OFF, %sjaCDR_RXINPEN, %sjaCDR_CBP, %sjaCDR_PELICAN
* The entry @sja_ocr_reg holds hardware specific options for the Output Control
* register. Options defined in the %sja1000.h file:
- * %OCR_MODE_BIPHASE, %OCR_MODE_TEST, %OCR_MODE_NORMAL, %OCR_MODE_CLOCK,
- * %OCR_TX0_LH, %OCR_TX1_ZZ.
+ * %sjaOCR_MODE_BIPHASE, %sjaOCR_MODE_TEST, %sjaOCR_MODE_NORMAL, %sjaOCR_MODE_CLOCK,
+ * %sjaOCR_TX0_LH, %sjaOCR_TX1_ZZ.
* The entry @int_clk_reg holds hardware specific options for the Clock Out
* register. Options defined in the %i82527.h file:
* %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1.
candev->chip[chipnr]->chip_type=CHIP_TYPE;
candev->chip[chipnr]->chip_base_addr=candev->io_addr;
candev->chip[chipnr]->clock = 16000000;
- candev->chip[chipnr]->sja_cdr_reg = CDR_CBP | CDR_CLK_OFF;
- candev->chip[chipnr]->sja_ocr_reg = OCR_MODE_NORMAL |
- OCR_TX0_HL | OCR_TX1_LZ;
+ candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CBP | sjaCDR_CLK_OFF;
+ candev->chip[chipnr]->sja_ocr_reg = sjaOCR_MODE_NORMAL |
+ sjaOCR_TX0_HL | sjaOCR_TX1_LZ;
return 0;
}
/* Check hardware reset status */
i=0;
- while ( (inb(candev->chip[0]->chip_base_addr+SJACR) & CR_RR)
+ while ( (inb(candev->chip[0]->chip_base_addr+SJACR) & sjaCR_RR)
&& (i<=15) ) {
udelay(20000);
i++;
for (chip_nr=0; chip_nr<2; chip_nr++) {
i=0;
while ( (inb(candev->chip[chip_nr]->chip_base_addr +
- SJACR) & CR_RR) && (i<=15) ) {
+ SJACR) & sjaCR_RR) && (i<=15) ) {
udelay(20000);
i++;
}
for (chip_nr=2; chip_nr<4; chip_nr++) {
i=0;
while( (inb(candev->chip[chip_nr]->chip_base_addr +
- SJACR) & CR_RR) && (i<=15) ) {
+ SJACR) & sjaCR_RR) && (i<=15) ) {
udelay(20000);
i++;
}
candev->chip[chipnr]->int_clk_reg = 0;
candev->chip[chipnr]->int_bus_reg = 0;
candev->chip[chipnr]->sja_cdr_reg =
- CDR_CLK_OFF;
+ sjaCDR_CLK_OFF;
candev->chip[chipnr]->sja_ocr_reg =
- OCR_MODE_NORMAL | OCR_TX0_LH;
+ sjaOCR_MODE_NORMAL | sjaOCR_TX0_LH;
}
candev->chip[chipnr]->chip_base_addr=0x1000*chipnr+0x2000+candev->io_addr;
}
candev->chip[chipnr]->int_cpu_reg = 0;
candev->chip[chipnr]->int_clk_reg = 0;
candev->chip[chipnr]->int_bus_reg = 0;
- candev->chip[chipnr]->sja_cdr_reg = CDR_CLK_OFF;
+ candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CLK_OFF;
candev->chip[chipnr]->sja_ocr_reg =
- OCR_MODE_NORMAL | OCR_TX0_LH;
+ sjaOCR_MODE_NORMAL | sjaOCR_TX0_LH;
}
candev->chip[chipnr]->clock = 16000000;
* The @clock entry holds the chip clock value in Hz.
* The entry @sja_cdr_reg holds hardware specific options for the Clock Divider
* register. Options defined in the %sja1000.h file:
- * %CDR_CLKOUT_MASK, %CDR_CLK_OFF, %CDR_RXINPEN, %CDR_CBP, %CDR_PELICAN
+ * %sjaCDR_CLKOUT_MASK, %sjaCDR_CLK_OFF, %sjaCDR_RXINPEN, %sjaCDR_CBP, %sjaCDR_PELICAN
* The entry @sja_ocr_reg holds hardware specific options for the Output Control
* register. Options defined in the %sja1000.h file:
- * %OCR_MODE_BIPHASE, %OCR_MODE_TEST, %OCR_MODE_NORMAL, %OCR_MODE_CLOCK,
- * %OCR_TX0_LH, %OCR_TX1_ZZ.
+ * %sjaOCR_MODE_BIPHASE, %sjaOCR_MODE_TEST, %sjaOCR_MODE_NORMAL, %sjaOCR_MODE_CLOCK,
+ * %sjaOCR_TX0_LH, %sjaOCR_TX1_ZZ.
* The entry @int_clk_reg holds hardware specific options for the Clock Out
* register. Options defined in the %i82527.h file:
* %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1.
DEBUGMSG("Resetting pcm3680 hardware ...\n");
for(chipnr=0;chipnr<candev->nr_sja1000_chips;chipnr++) {
chip=candev->chip[chipnr];
- pcm3680_write_register(MOD_RM, chip->chip_base_addr+SJAMOD);
+ pcm3680_write_register(sjaMOD_RM, chip->chip_base_addr+SJAMOD);
udelay(1000);
pcm3680_write_register(0x00, chip->chip_base_addr + SJAIER);
/* Write arbitrary data to reset chip */
pcm3680_write_register(0x01, chip->chip_base_addr + 0x100);
udelay(1000);
i=20;
- while (pcm3680_read_register(chip->chip_base_addr+SJAMOD)&MOD_RM){
+ while (pcm3680_read_register(chip->chip_base_addr+SJAMOD)&sjaMOD_RM){
if(!i--) return -ENODEV;
udelay(1000);
pcm3680_write_register(0, chip->chip_base_addr+SJAMOD);
}
udelay(1000);
- pcm3680_write_register(CDR_PELICAN, chip->chip_base_addr+SJACDR);
+ pcm3680_write_register(sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
pcm3680_write_register(0x00, chip->chip_base_addr + SJAIER);
}
* The @clock entry holds the chip clock value in Hz.
* The entry @sja_cdr_reg holds hardware specific options for the Clock Divider
* register. Options defined in the %sja1000.h file:
- * %CDR_CLKOUT_MASK, %CDR_CLK_OFF, %CDR_RXINPEN, %CDR_CBP, %CDR_PELICAN
+ * %sjaCDR_CLKOUT_MASK, %sjaCDR_CLK_OFF, %sjaCDR_RXINPEN, %sjaCDR_CBP, %sjaCDR_PELICAN
* The entry @sja_ocr_reg holds hardware specific options for the Output Control
* register. Options defined in the %sja1000.h file:
- * %OCR_MODE_BIPHASE, %OCR_MODE_TEST, %OCR_MODE_NORMAL, %OCR_MODE_CLOCK,
- * %OCR_TX0_LH, %OCR_TX1_ZZ.
+ * %sjaOCR_MODE_BIPHASE, %sjaOCR_MODE_TEST, %sjaOCR_MODE_NORMAL, %sjaOCR_MODE_CLOCK,
+ * %sjaOCR_TX0_LH, %sjaOCR_TX1_ZZ.
* The entry @int_clk_reg holds hardware specific options for the Clock Out
* register. Options defined in the %i82527.h file:
* %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1.
candev->chip[chipnr]->clock = 16000000;
candev->chip[chipnr]->int_clk_reg = 0x0;
candev->chip[chipnr]->int_bus_reg = 0x0;
- candev->chip[chipnr]->sja_cdr_reg = CDR_CBP | CDR_CLK_OFF;
- candev->chip[chipnr]->sja_ocr_reg = OCR_MODE_NORMAL |
- OCR_TX0_LH;
+ candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CBP | sjaCDR_CLK_OFF;
+ candev->chip[chipnr]->sja_ocr_reg = sjaOCR_MODE_NORMAL |
+ sjaOCR_TX0_LH;
return 0;
}
struct chip_t *chip=candev->chip[0];
unsigned cdr;
- pikronisa_write_register(MOD_RM, chip->chip_base_addr+SJAMOD);
+ pikronisa_write_register(sjaMOD_RM, chip->chip_base_addr+SJAMOD);
udelay(1000);
cdr=pikronisa_read_register(chip->chip_base_addr+SJACDR);
- pikronisa_write_register(cdr|CDR_PELICAN, chip->chip_base_addr+SJACDR);
+ pikronisa_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
pikronisa_write_register(0, chip->chip_base_addr+SJAIER);
i=20;
pikronisa_write_register(0, chip->chip_base_addr+SJAMOD);
- while (pikronisa_read_register(chip->chip_base_addr+SJAMOD)&MOD_RM){
+ while (pikronisa_read_register(chip->chip_base_addr+SJAMOD)&sjaMOD_RM){
if(!i--) return -ENODEV;
udelay(1000);
pikronisa_write_register(0, chip->chip_base_addr+SJAMOD);
}
cdr=pikronisa_read_register(chip->chip_base_addr+SJACDR);
- pikronisa_write_register(cdr|CDR_PELICAN, chip->chip_base_addr+SJACDR);
+ pikronisa_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
pikronisa_write_register(0, chip->chip_base_addr+SJAIER);
* The @clock entry holds the chip clock value in Hz.
* The entry @sja_cdr_reg holds hardware specific options for the Clock Divider
* register. Options defined in the %sja1000.h file:
- * %CDR_CLKOUT_MASK, %CDR_CLK_OFF, %CDR_RXINPEN, %CDR_CBP, %CDR_PELICAN
+ * %sjaCDR_CLKOUT_MASK, %sjaCDR_CLK_OFF, %sjaCDR_RXINPEN, %sjaCDR_CBP, %sjaCDR_PELICAN
* The entry @sja_ocr_reg holds hardware specific options for the Output Control
* register. Options defined in the %sja1000.h file:
- * %OCR_MODE_BIPHASE, %OCR_MODE_TEST, %OCR_MODE_NORMAL, %OCR_MODE_CLOCK,
- * %OCR_TX0_LH, %OCR_TX1_ZZ.
+ * %sjaOCR_MODE_BIPHASE, %sjaOCR_MODE_TEST, %sjaOCR_MODE_NORMAL, %sjaOCR_MODE_CLOCK,
+ * %sjaOCR_TX0_LH, %sjaOCR_TX1_ZZ.
* The entry @int_clk_reg holds hardware specific options for the Clock Out
* register. Options defined in the %i82527.h file:
* %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1.
candev->chip[chipnr]->clock = 24000000;
candev->chip[chipnr]->int_clk_reg = 0x0;
candev->chip[chipnr]->int_bus_reg = 0x0;
- candev->chip[chipnr]->sja_cdr_reg = CDR_CBP | CDR_CLK_OFF;
- candev->chip[chipnr]->sja_ocr_reg = OCR_MODE_NORMAL | OCR_TX0_LH;
+ candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CBP | sjaCDR_CLK_OFF;
+ candev->chip[chipnr]->sja_ocr_reg = sjaOCR_MODE_NORMAL | sjaOCR_TX0_LH;
return 0;
}
flags=can_read_reg(chip,SJACR);
- while ((!(flags & CR_RR)) && (i<=10)) {
- can_write_reg(chip,flags|CR_RR,SJACR);
+ while ((!(flags & sjaCR_RR)) && (i<=10)) {
+ can_write_reg(chip,flags|sjaCR_RR,SJACR);
udelay(100);
i++;
flags=can_read_reg(chip,SJACR);
flags=can_read_reg(chip,SJACR);
- while ( (flags & CR_RR) && (i<=10) ) {
- can_write_reg(chip,flags & (CR_RIE|CR_TIE|CR_EIE|CR_OIE),SJACR);
+ while ( (flags & sjaCR_RR) && (i<=10) ) {
+ can_write_reg(chip,flags & (sjaCR_RIE|sjaCR_TIE|sjaCR_EIE|sjaCR_OIE),SJACR);
udelay(100);
i++;
flags=can_read_reg(chip,SJACR);
return -ENODEV;
/* Enable hardware interrupts */
- can_write_reg(chip,(CR_RIE|CR_TIE|CR_EIE|CR_OIE),SJACR);
+ can_write_reg(chip,(sjaCR_RIE|sjaCR_TIE|sjaCR_EIE|sjaCR_OIE),SJACR);
sja1000_disable_configuration(chip);
can_write_reg(chip, sjw<<6 | best_brp, SJABTR0);
can_write_reg(chip, ((flags & BTR1_SAM) != 0)<<7 | tseg2<<4 | tseg1,
SJABTR1);
-// can_write_reg(chip, OCR_MODE_NORMAL | OCR_TX0_LH | OCR_TX1_ZZ, SJAOCR);
+// can_write_reg(chip, sjaOCR_MODE_NORMAL | sjaOCR_TX0_LH | sjaOCR_TX1_ZZ, SJAOCR);
/* BASIC mode, bypass input comparator */
-// can_write_reg(chip, CDR_CBP| /* CDR_CLK_OFF | */ 7, SJACDR);
+// can_write_reg(chip, sjaCDR_CBP| /* sjaCDR_CLK_OFF | */ 7, SJACDR);
sja1000_disable_configuration(chip);
i=can_read_reg(chip,SJASR);
- if (!(i&SR_RBS)) {
+ if (!(i&sjaSR_RBS)) {
//Temp
for (i=0; i<0x20; i++)
CANMSG("0x%x is 0x%x\n",i,can_read_reg(chip,i));
sja1000_irq_read_handler(chip, obj);
// enable interrupts
- can_write_reg(chip, CR_OIE | CR_EIE | CR_TIE | CR_RIE, SJACR);
+ can_write_reg(chip, sjaCR_OIE | sjaCR_EIE | sjaCR_TIE | sjaCR_RIE, SJACR);
return 1;
sja1000_start_chip(chip); //sja1000 goes automatically into reset mode on errors
/* Wait until Transmit Buffer Status is released */
- while ( !(can_read_reg(chip, SJASR) & SR_TBS) &&
+ while ( !(can_read_reg(chip, SJASR) & sjaSR_TBS) &&
i++<MAX_TRANSMIT_WAIT_LOOPS) {
udelay(i);
}
- if (!(can_read_reg(chip, SJASR) & SR_TBS)) {
+ if (!(can_read_reg(chip, SJASR) & sjaSR_TBS)) {
CANMSG("Transmit timed out, cancelling\n");
- can_write_reg(chip, CMR_AT, SJACMR);
+ can_write_reg(chip, sjaCMR_AT, SJACMR);
i=0;
- while ( !(can_read_reg(chip, SJASR) & SR_TBS) &&
+ while ( !(can_read_reg(chip, SJASR) & sjaSR_TBS) &&
i++<MAX_TRANSMIT_WAIT_LOOPS) {
udelay(i);
}
- if (!(can_read_reg(chip, SJASR) & SR_TBS)) {
+ if (!(can_read_reg(chip, SJASR) & sjaSR_TBS)) {
CANMSG("Could not cancel, please reset\n");
return -EIO;
}
len = msg->length;
if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
- id = (msg->id<<5) | ((msg->flags&MSG_RTR)?ID0_RTR:0) | len;
+ id = (msg->id<<5) | ((msg->flags&MSG_RTR)?sjaID0_RTR:0) | len;
can_write_reg(chip, id>>8, SJATXID1);
can_write_reg(chip, id & 0xff , SJATXID0);
int sja1000_send_msg(struct chip_t *chip, struct msgobj_t *obj,
struct canmsg_t *msg)
{
- can_write_reg(chip, CMR_TR, SJACMR);
+ can_write_reg(chip, sjaCMR_TR, SJACMR);
return 0;
}
int sja1000_check_tx_stat(struct chip_t *chip)
{
- if (can_read_reg(chip,SJASR) & SR_TCS)
+ if (can_read_reg(chip,SJASR) & sjaSR_TCS)
return 0;
else
return 1;
{
unsigned short flags = 0;
- flags = can_read_reg(chip, SJACR) & (CR_RIE|CR_TIE|CR_EIE|CR_OIE);
+ flags = can_read_reg(chip, SJACR) & (sjaCR_RIE|sjaCR_TIE|sjaCR_EIE|sjaCR_OIE);
can_write_reg(chip, flags, SJACR);
return 0;
{
unsigned short flags = 0;
- flags = can_read_reg(chip, SJACR) & (CR_RIE|CR_TIE|CR_EIE|CR_OIE);
- can_write_reg(chip, flags|CR_RR, SJACR);
+ flags = can_read_reg(chip, SJACR) & (sjaCR_RIE|sjaCR_TIE|sjaCR_EIE|sjaCR_OIE);
+ can_write_reg(chip, flags|sjaCR_RR, SJACR);
return 0;
}
// DEBUGMSG("sja1000_irq_handler: SJASR:%02x\n",
// can_read_reg(chip, SJASR));
- if ((irq_register & (IR_WUI|IR_DOI|IR_EI|IR_TI|IR_RI)) == 0)
+ if ((irq_register & (sjaIR_WUI|sjaIR_DOI|sjaIR_EI|sjaIR_TI|sjaIR_RI)) == 0)
return CAN_IRQ_NONE;
- if ((irq_register & IR_RI) != 0)
+ if ((irq_register & sjaIR_RI) != 0)
sja1000_irq_read_handler(chip, obj);
- if ((irq_register & IR_TI) != 0) {
+ if ((irq_register & sjaIR_TI) != 0) {
can_msgobj_set_fl(obj,TX_REQUEST);
while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)){
can_msgobj_clear_fl(obj,TX_REQUEST);
- if (can_read_reg(chip, SJASR) & SR_TBS)
+ if (can_read_reg(chip, SJASR) & sjaSR_TBS)
sja1000_irq_write_handler(chip, obj);
can_msgobj_clear_fl(obj,TX_LOCK);
}
}
- if ((irq_register & (IR_EI|IR_DOI)) != 0) {
+ if ((irq_register & (sjaIR_EI|sjaIR_DOI)) != 0) {
// Some error happened
// FIXME: chip should be brought to usable state. Transmission cancelled if in progress.
// Reset flag set to 0 if chip is already off the bus. Full state report
do {
id = can_read_reg(chip, SJARXID0) | (can_read_reg(chip, SJARXID1)<<8);
obj->rx_msg.length = len = id & 0x0f;
- obj->rx_msg.flags = id&ID0_RTR ? MSG_RTR : 0;
+ obj->rx_msg.flags = id&sjaID0_RTR ? MSG_RTR : 0;
#ifdef CAN_MSG_VERSION_2
obj->rx_msg.timestamp.tv_sec = 0;
obj->rx_msg.timestamp.tv_usec = 0;
for (i=0; i<len; i++)
obj->rx_msg.data[i]=can_read_reg(chip, SJARXDAT0 + i);
- can_write_reg(chip, CMR_RRB, SJACMR);
+ can_write_reg(chip, sjaCMR_RRB, SJACMR);
canque_filter_msg2edges(obj->qends, &obj->rx_msg);
- } while(can_read_reg(chip, SJASR) & SR_RBS);
+ } while(can_read_reg(chip, SJASR) & sjaSR_RBS);
}
void sja1000_irq_write_handler(struct chip_t *chip, struct msgobj_t *obj)
while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)){
can_msgobj_clear_fl(obj,TX_REQUEST);
- if (can_read_reg(chip, SJASR) & SR_TBS)
+ if (can_read_reg(chip, SJASR) & sjaSR_TBS)
sja1000_irq_write_handler(chip, obj);
can_msgobj_clear_fl(obj,TX_LOCK);
flags=can_read_reg(chip,SJAMOD);
- while ((!(flags & MOD_RM)) && (i<=10)) {
- can_write_reg(chip, MOD_RM, SJAMOD);
-// TODO: configurable MOD_AFM (32/16 bit acceptance filter)
-// config MOD_LOM (listen only)
+ while ((!(flags & sjaMOD_RM)) && (i<=10)) {
+ can_write_reg(chip, sjaMOD_RM, SJAMOD);
+// TODO: configurable sjaMOD_AFM (32/16 bit acceptance filter)
+// config sjaMOD_LOM (listen only)
udelay(100);
i++;
flags=can_read_reg(chip, SJAMOD);
flags=can_read_reg(chip,SJAMOD);
- while ( (flags & MOD_RM) && (i<=50) ) {
+ while ( (flags & sjaMOD_RM) && (i<=50) ) {
// could be as long as 11*128 bit times after buss-off
can_write_reg(chip, 0, SJAMOD);
-// TODO: configurable MOD_AFM (32/16 bit acceptance filter)
-// config MOD_LOM (listen only)
+// TODO: configurable sjaMOD_AFM (32/16 bit acceptance filter)
+// config sjaMOD_LOM (listen only)
udelay(100);
i++;
flags=can_read_reg(chip, SJAMOD);
return -ENODEV;
/* Set mode, clock out, comparator */
- can_write_reg(chip,CDR_PELICAN|chip->sja_cdr_reg,SJACDR);
+ can_write_reg(chip,sjaCDR_PELICAN|chip->sja_cdr_reg,SJACDR);
/* Set driver output configuration */
can_write_reg(chip,chip->sja_ocr_reg,SJAOCR);
return -ENODEV;
/* Enable hardware interrupts */
- can_write_reg(chip, ENABLE_INTERRUPTS, SJAIER);
+ can_write_reg(chip, sjaENABLE_INTERRUPTS, SJAIER);
sja1000p_disable_configuration(chip);
clock /=2;
/* tseg even = round down, odd = round up */
- for (tseg=(0+0+2)*2; tseg<=(MAX_TSEG2+MAX_TSEG1+2)*2+1; tseg++) {
+ for (tseg=(0+0+2)*2; tseg<=(sjaMAX_TSEG2+sjaMAX_TSEG1+2)*2+1; tseg++) {
brp = clock/((1+tseg/2)*rate)+tseg%2;
if (brp == 0 || brp > 64)
continue;
tseg2 = best_tseg-(sampl_pt*(best_tseg+1))/100;
if (tseg2 < 0)
tseg2 = 0;
- if (tseg2 > MAX_TSEG2)
- tseg2 = MAX_TSEG2;
+ if (tseg2 > sjaMAX_TSEG2)
+ tseg2 = sjaMAX_TSEG2;
tseg1 = best_tseg-tseg2-2;
- if (tseg1>MAX_TSEG1) {
- tseg1 = MAX_TSEG1;
+ if (tseg1>sjaMAX_TSEG1) {
+ tseg1 = sjaMAX_TSEG1;
tseg2 = best_tseg-tseg1-2;
}
int i, flags, len, datastart;
do {
flags = can_read_reg(chip,SJAFRM);
- if(flags&FRM_FF) {
+ if(flags&sjaFRM_FF) {
obj->rx_msg.id =
(can_read_reg(chip,SJAID0)<<21) +
(can_read_reg(chip,SJAID1)<<13) +
datastart = SJADATS;
}
obj->rx_msg.flags =
- ((flags & FRM_RTR) ? MSG_RTR : 0) |
- ((flags & FRM_FF) ? MSG_EXT : 0);
- len = flags & FRM_DLC_M;
+ ((flags & sjaFRM_RTR) ? MSG_RTR : 0) |
+ ((flags & sjaFRM_FF) ? MSG_EXT : 0);
+ len = flags & sjaFRM_DLC_M;
obj->rx_msg.length = len;
if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
for(i=0; i< len; i++) {
canque_filter_msg2edges(obj->qends, &obj->rx_msg);
- can_write_reg(chip, CMR_RRB, SJACMR);
+ can_write_reg(chip, sjaCMR_RRB, SJACMR);
- } while (can_read_reg(chip, SJASR) & SR_RBS);
+ } while (can_read_reg(chip, SJASR) & sjaSR_RBS);
}
/**
int status;
status=can_read_reg(chip,SJASR);
- if(status & SR_BS) {
+ if(status & sjaSR_BS) {
/* Try to recover from error condition */
DEBUGMSG("sja1000p_pre_read_config bus-off recover 0x%x\n",status);
sja1000p_enable_configuration(chip);
sja1000p_disable_configuration(chip);
}
- if (!(status&SR_RBS)) {
+ if (!(status&sjaSR_RBS)) {
return 0;
}
- can_write_reg(chip, DISABLE_INTERRUPTS, SJAIER); //disable interrupts for a moment
+ can_write_reg(chip, sjaDISABLE_INTERRUPTS, SJAIER); //disable interrupts for a moment
sja1000p_read(chip, obj);
- can_write_reg(chip, ENABLE_INTERRUPTS, SJAIER); //enable interrupts
+ can_write_reg(chip, sjaENABLE_INTERRUPTS, SJAIER); //enable interrupts
return 1;
}
int len;
/* Wait until Transmit Buffer Status is released */
- while ( !((status=can_read_reg(chip, SJASR)) & SR_TBS) &&
+ while ( !((status=can_read_reg(chip, SJASR)) & sjaSR_TBS) &&
i++<MAX_TRANSMIT_WAIT_LOOPS) {
udelay(i);
}
- if(status & SR_BS) {
+ if(status & sjaSR_BS) {
/* Try to recover from error condition */
DEBUGMSG("sja1000p_pre_write_config bus-off recover 0x%x\n",status);
sja1000p_enable_configuration(chip);
can_read_reg(chip, SJAECC);
sja1000p_disable_configuration(chip);
}
- if (!(can_read_reg(chip, SJASR) & SR_TBS)) {
+ if (!(can_read_reg(chip, SJASR) & sjaSR_TBS)) {
CANMSG("Transmit timed out, cancelling\n");
// here we should check if there is no write/select waiting for this
// transmit. If so, set error ret and wake up.
-// CHECKME: if we do not disable IER_TIE (TX IRQ) here we get interrupt
+// CHECKME: if we do not disable sjaIER_TIE (TX IRQ) here we get interrupt
// immediately
- can_write_reg(chip, CMR_AT, SJACMR);
+ can_write_reg(chip, sjaCMR_AT, SJACMR);
i=0;
- while ( !(can_read_reg(chip, SJASR) & SR_TBS) &&
+ while ( !(can_read_reg(chip, SJASR) & sjaSR_TBS) &&
i++<MAX_TRANSMIT_WAIT_LOOPS) {
udelay(i);
}
- if (!(can_read_reg(chip, SJASR) & SR_TBS)) {
+ if (!(can_read_reg(chip, SJASR) & sjaSR_TBS)) {
CANMSG("Could not cancel, please reset\n");
return -EIO;
}
}
len = msg->length;
if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
- /* len &= FRM_DLC_M; ensured by above condition already */
- can_write_reg(chip, ((msg->flags&MSG_EXT)?FRM_FF:0) |
- ((msg->flags & MSG_RTR) ? FRM_RTR : 0) | len, SJAFRM);
+ /* len &= sjaFRM_DLC_M; ensured by above condition already */
+ can_write_reg(chip, ((msg->flags&MSG_EXT)?sjaFRM_FF:0) |
+ ((msg->flags & MSG_RTR) ? sjaFRM_RTR : 0) | len, SJAFRM);
if(msg->flags&MSG_EXT) {
id=msg->id<<3;
can_write_reg(chip, id & 0xff, SJAID3);
int sja1000p_send_msg(struct chip_t *chip, struct msgobj_t *obj,
struct canmsg_t *msg)
{
- can_write_reg(chip, CMR_TR, SJACMR);
+ can_write_reg(chip, sjaCMR_TR, SJACMR);
return 0;
}
*/
int sja1000p_check_tx_stat(struct chip_t *chip)
{
- if (can_read_reg(chip,SJASR) & SR_TCS)
+ if (can_read_reg(chip,SJASR) & sjaSR_TCS)
return 0;
else
return 1;
{
enum sja1000_PeliCAN_MOD flags;
- flags = can_read_reg(chip, SJAMOD) & (MOD_LOM|MOD_STM|MOD_AFM|MOD_SM);
+ flags = can_read_reg(chip, SJAMOD) & (sjaMOD_LOM|sjaMOD_STM|sjaMOD_AFM|sjaMOD_SM);
can_write_reg(chip, flags, SJAMOD);
return 0;
{
enum sja1000_PeliCAN_MOD flags;
- flags = can_read_reg(chip, SJAMOD) & (MOD_LOM|MOD_STM|MOD_AFM|MOD_SM);
- can_write_reg(chip, flags|MOD_RM, SJAMOD);
+ flags = can_read_reg(chip, SJAMOD) & (sjaMOD_LOM|sjaMOD_STM|sjaMOD_AFM|sjaMOD_SM);
+ can_write_reg(chip, flags|sjaMOD_RM, SJAMOD);
return 0;
}
// DEBUGMSG("sja1000_irq_handler: SJASR:%02x\n",
// can_read_reg(chip,SJASR));
- if ((irq_register & (IR_BEI|IR_EPI|IR_DOI|IR_EI|IR_TI|IR_RI)) == 0)
+ if ((irq_register & (sjaIR_BEI|sjaIR_EPI|sjaIR_DOI|sjaIR_EI|sjaIR_TI|sjaIR_RI)) == 0)
return CAN_IRQ_NONE;
if(!(chip->flags&CHIP_CONFIGURED)) {
return CAN_IRQ_NONE;
}
- if ((irq_register & IR_RI) != 0) {
+ if ((irq_register & sjaIR_RI) != 0) {
DEBUGMSG("sja1000_irq_handler: RI\n");
sja1000p_read(chip,obj);
obj->ret = 0;
}
- if ((irq_register & IR_TI) != 0) {
+ if ((irq_register & sjaIR_TI) != 0) {
DEBUGMSG("sja1000_irq_handler: TI\n");
obj->ret = 0;
can_msgobj_set_fl(obj,TX_REQUEST);
while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)){
can_msgobj_clear_fl(obj,TX_REQUEST);
- if (can_read_reg(chip, SJASR) & SR_TBS)
+ if (can_read_reg(chip, SJASR) & sjaSR_TBS)
sja1000p_irq_write_handler(chip, obj);
can_msgobj_clear_fl(obj,TX_LOCK);
DEBUGMSG("TX looping in sja1000_irq_handler\n");
}
}
- if ((irq_register & (IR_EI|IR_BEI|IR_EPI|IR_DOI)) != 0) {
+ if ((irq_register & (sjaIR_EI|sjaIR_BEI|sjaIR_EPI|sjaIR_DOI)) != 0) {
// Some error happened
status=can_read_reg(chip,SJASR);
error_code=can_read_reg(chip,SJAECC);
/* no such device or address - no ACK received */
}
if(obj->tx_retry_cnt++>MAX_RETR) {
- can_write_reg(chip, CMR_AT, SJACMR); // cancel any transmition
+ can_write_reg(chip, sjaCMR_AT, SJACMR); // cancel any transmition
obj->tx_retry_cnt = 0;
}
- if(status&SR_BS) {
+ if(status&sjaSR_BS) {
CANMSG("bus-off, resetting sja1000p\n");
can_write_reg(chip, 0, SJAMOD);
}
while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)){
can_msgobj_clear_fl(obj,TX_REQUEST);
- if (can_read_reg(chip, SJASR) & SR_TBS){
+ if (can_read_reg(chip, SJASR) & sjaSR_TBS){
obj->tx_retry_cnt=0;
sja1000p_irq_write_handler(chip, obj);
}
* The @clock entry holds the chip clock value in Hz.
* The entry @sja_cdr_reg holds hardware specific options for the Clock Divider
* register. Options defined in the %sja1000.h file:
- * %CDR_CLKOUT_MASK, %CDR_CLK_OFF, %CDR_RXINPEN, %CDR_CBP, %CDR_PELICAN
+ * %sjaCDR_CLKOUT_MASK, %sjaCDR_CLK_OFF, %sjaCDR_RXINPEN, %sjaCDR_CBP, %sjaCDR_PELICAN
* The entry @sja_ocr_reg holds hardware specific options for the Output Control
* register. Options defined in the %sja1000.h file:
- * %OCR_MODE_BIPHASE, %OCR_MODE_TEST, %OCR_MODE_NORMAL, %OCR_MODE_CLOCK,
- * %OCR_TX0_LH, %OCR_TX1_ZZ.
+ * %sjaOCR_MODE_BIPHASE, %sjaOCR_MODE_TEST, %sjaOCR_MODE_NORMAL, %sjaOCR_MODE_CLOCK,
+ * %sjaOCR_TX0_LH, %sjaOCR_TX1_ZZ.
* The entry @int_clk_reg holds hardware specific options for the Clock Out
* register. Options defined in the %i82527.h file:
* %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1.
candev->chip[chipnr]->int_cpu_reg = iCPU_DSC;
candev->chip[chipnr]->int_clk_reg = iCLK_SL1;
candev->chip[chipnr]->int_bus_reg = iBUS_CBY;
- candev->chip[chipnr]->sja_cdr_reg = CDR_CBP | CDR_CLK_OFF;
- candev->chip[chipnr]->sja_ocr_reg = OCR_MODE_NORMAL |
- OCR_TX0_LH;
+ candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CBP | sjaCDR_CLK_OFF;
+ candev->chip[chipnr]->sja_ocr_reg = sjaOCR_MODE_NORMAL |
+ sjaOCR_TX0_LH;
return 0;
}
projects / lincan.git / commitdiff