The delays are required mostly for old, incorrectly
engineered CAN boards. So use of mdelay is deprecated
as well.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
i=0;
while ( (aim104_read_register(candev->io_addr + SJACR)
& sjaCR_RR) && (i<=15) ) {
i=0;
while ( (aim104_read_register(candev->io_addr + SJACR)
& sjaCR_RR) && (i<=15) ) {
/* Check hardware reset status */
i=0;
while ( (m437_read_register(candev->dev_base_addr+iCPU) & iCPU_RST) && (i<=15)) {
/* Check hardware reset status */
i=0;
while ( (m437_read_register(candev->dev_base_addr+iCPU) & iCPU_RST) && (i<=15)) {
/* Check hardware reset status */
i=0;
while ( (nsi_read_register(nsican_base+iCPU) & iCPU_RST) && (i<=15)) {
/* Check hardware reset status */
i=0;
while ( (nsi_read_register(nsican_base+iCPU) & iCPU_RST) && (i<=15)) {
DEBUGMSG("Resetting pc-i03 hardware ...\n");
pci03_write_register(0x01,pci03_base_addr +
0x100); // Write arbitrary data to reset mem
DEBUGMSG("Resetting pc-i03 hardware ...\n");
pci03_write_register(0x01,pci03_base_addr +
0x100); // Write arbitrary data to reset mem
pci03_write_register(0x00, pci03_base_addr + SJACR);
pci03_write_register(0x00, pci03_base_addr + SJACR);
i=0;
while ( (pci03_read_register(pci03_base_addr + SJACR) & sjaCR_RR)
&& (i<=15) ) {
i=0;
while ( (pci03_read_register(pci03_base_addr + SJACR) & sjaCR_RR)
&& (i<=15) ) {
i=0;
while ( (can_inb(candev->chip[0]->chip_base_addr+SJACR) & sjaCR_RR)
&& (i<=15) ) {
i=0;
while ( (can_inb(candev->chip[0]->chip_base_addr+SJACR) & sjaCR_RR)
&& (i<=15) ) {
i=0;
while ( (can_inb(candev->chip[chip_nr]->chip_base_addr +
SJACR) & sjaCR_RR) && (i<=15) ) {
i=0;
while ( (can_inb(candev->chip[chip_nr]->chip_base_addr +
SJACR) & sjaCR_RR) && (i<=15) ) {
i=0;
while( (can_inb(candev->chip[chip_nr]->chip_base_addr +
iCPU) & iCPU_RST) && (i<=15) ) {
i=0;
while( (can_inb(candev->chip[chip_nr]->chip_base_addr +
iCPU) & iCPU_RST) && (i<=15) ) {
i=0;
while( (can_inb(candev->chip[chip_nr]->chip_base_addr +
SJACR) & sjaCR_RR) && (i<=15) ) {
i=0;
while( (can_inb(candev->chip[chip_nr]->chip_base_addr +
SJACR) & sjaCR_RR) && (i<=15) ) {
i=0;
can_outb(iCPU,candev->io_addr+0x1);
while ( (can_inb(candev->io_addr+0x2)&0x80) && (i<=15) ) {
i=0;
can_outb(iCPU,candev->io_addr+0x1);
while ( (can_inb(candev->io_addr+0x2)&0x80) && (i<=15) ) {
/* Check hardware reset status */
i = 0;
while ((can_inb(candev->io_addr + iCPU) & iCPU_RST) && (i <= 15)) {
/* Check hardware reset status */
i = 0;
while ((can_inb(candev->io_addr + iCPU) & iCPU_RST) && (i <= 15)) {
i=0;
can_outb(candev->io_addr+iCPU,candev->io_addr);
while ( (can_inb(candev->io_addr+1)&0x80) && (i<=15) ) {
i=0;
can_outb(candev->io_addr+iCPU,candev->io_addr);
while ( (can_inb(candev->io_addr+1)&0x80) && (i<=15) ) {
/* Check hardware reset status */
i=0;
while ( (ssv_read_register(ssvcan_base+iCPU) & iCPU_RST) && (i<=15)) {
/* Check hardware reset status */
i=0;
while ( (ssv_read_register(ssvcan_base+iCPU) & iCPU_RST) && (i<=15)) {
/* Check hardware reset status */
i=0;
while ( (ssv_read_register(ssvcan_base+0x100+iCPU) & iCPU_RST) && (i<=15)) {
/* Check hardware reset status */
i=0;
while ( (ssv_read_register(ssvcan_base+0x100+iCPU) & iCPU_RST) && (i<=15)) {