X-Git-Url: http://rtime.felk.cvut.cz/gitweb/lincan.git/blobdiff_plain/fa9556b05ef6e9babc073870a70a6eb7c950fab8..a6d355f1cf48f39eecb2f1bdead51817d1fd5989:/lincan/src/ems_cpcpci.c

diff --git a/lincan/src/ems_cpcpci.c b/lincan/src/ems_cpcpci.c
index b0f8b04..d20e281 100644
--- a/lincan/src/ems_cpcpci.c
+++ b/lincan/src/ems_cpcpci.c
@@ -30,8 +30,13 @@
 
 /*PSB4610 PITA-2 bridge control registers*/   
 #define PITA2_ICR  0x00  /* Interrupt Control Register */
-#define   PITA2_ICR_INT0    0x00000002 /* [RC] INT0 Active/Clear */
-#define   PITA2_ICR_INT0_En 0x00020000 /* [RW] Enable INT0 */
+#define   PITA2_ICR_INT0    0x00000002	/* [RC] INT0 Active/Clear */
+#define   PITA2_ICR_GP0_INT 0x00000004	/* [RC] GP0 Interrupt */
+					/* GP0_Int_En=1, GP0_Out_En=0 and low detected */
+#define   PITA2_ICR_GP1_INT 0x00000008	/* [RC] GP1 Interrupt */
+#define   PITA2_ICR_GP2_INT 0x00000010	/* [RC] GP2 Interrupt */
+#define   PITA2_ICR_GP3_INT 0x00000020	/* [RC] GP2 Interrupt */
+#define   PITA2_ICR_INT0_En 0x00020000	/* [RW] Enable INT0 */
 
 #define PITA2_MISC 0x1C  /* Miscellaneous Register */
 #define   PITA2_MISC_CONFIG 0x04000000
@@ -118,7 +123,7 @@ int ems_cpcpci_request_io(struct candevice_t *candev)
 	 * can change when resources are temporarily released
 	 */
 	for(i=0;i<candev->nr_all_chips;i++) {
-		struct chip_t *chip=candev->chip[i];
+		struct canchip_t *chip=candev->chip[i];
 		if(!chip) continue;
 		chip->chip_base_addr = candev->io_addr+
 			0x400 + i*EMS_CPCPCI_BYTES_PER_CIRCUIT;
@@ -178,36 +183,37 @@ unsigned ems_cpcpci_read_register(unsigned long address)
 	return readb(address);
 }
 
-extern can_irqreturn_t sja1000p_irq_handler(int irq, void *dev_id, struct pt_regs *regs);
-
-can_irqreturn_t ems_cpcpci_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
+int ems_cpcpci_irq_handler(int irq, struct canchip_t *chip)
 {
-	struct chip_t *chip=(struct chip_t *)dev_id;
+	//struct canchip_t *chip=(struct canchip_t *)dev_id;
 	struct candevice_t *candev=chip->hostdevice;
 	int i;
 	unsigned long icr;
+	int test_irq_again;
 
 	icr=readl(candev->dev_base_addr + PITA2_ICR);
-	if(!(icr & PITA2_ICR_INT0)) return IRQ_NONE;
+	if(!(icr & PITA2_ICR_INT0)) return CANCHIP_IRQ_NONE;
 	
 	/* correct way to handle interrupts from all chips connected to the one PITA-2 */
 	do {
 		writel(PITA2_ICR_INT0_En | PITA2_ICR_INT0, candev->dev_base_addr + PITA2_ICR);
+		test_irq_again=0;
 		for(i=0;i<candev->nr_all_chips;i++){
 			chip=candev->chip[i];
 			if(!chip || !(chip->flags&CHIP_CONFIGURED))
 				continue;
-			sja1000p_irq_handler(irq, dev_id, regs);
+			if(sja1000p_irq_handler(irq, chip))
+				test_irq_again=1;
 		}
 		icr=readl(candev->dev_base_addr + PITA2_ICR);
-	} while(icr & PITA2_ICR_INT0);
-	return IRQ_HANDLED;
+	} while((icr & PITA2_ICR_INT0)||test_irq_again);
+	return CANCHIP_IRQ_HANDLED;
 }
 
 int ems_cpcpci_reset(struct candevice_t *candev)
 {
 	int i=0,chip_nr;
-	struct chip_t *chip;
+	struct canchip_t *chip;
 	unsigned cdr;
 
 	DEBUGMSG("Resetting EMS_CPCPCI hardware ...\n");
@@ -295,7 +301,7 @@ int ems_cpcpci_init_hw_data(struct candevice_t *candev)
 	
 	CANMSG("EMS CPC-PCI check value %04lx, ID %d\n", l, i);
 	
-	if((l!=0x55aa01cb)||(i!=0x11)) {
+	if(l!=0x55aa01cb) {
 		CANMSG("EMS CPC-PCI unexpected check values\n");
 	}
 
@@ -337,7 +343,7 @@ int ems_cpcpci_init_chip_data(struct candevice_t *candev, int chipnr)
 	return 0;
 }	
 
-int ems_cpcpci_init_obj_data(struct chip_t *chip, int objnr)
+int ems_cpcpci_init_obj_data(struct canchip_t *chip, int objnr)
 {
 	chip->msgobj[objnr]->obj_base_addr=chip->chip_base_addr;
 	return 0;