X-Git-Url: http://rtime.felk.cvut.cz/gitweb/lincan.git/blobdiff_plain/f2fcdbb5f9333a58a08f56daaca8cad7e5a95699..3129fcd8094edcb910b708463fdf1a234f11fb55:/lincan/include/main.h diff --git a/lincan/include/main.h b/lincan/include/main.h index c6a0741..17e8f55 100644 --- a/lincan/include/main.h +++ b/lincan/include/main.h @@ -43,6 +43,13 @@ #define IRQ_RETVAL(x) #endif /* <=2.5.67 */ +/** + * struct canhardware_t - structure representing pointers to all CAN boards + * @nr_boards: number of present boards + * @rtr_queue: RTR - remote transmission request queue (expect some changes there) + * @rtr_lock: locking for RTR queue + * @candevice: array of pointers to CAN devices/boards + */ struct canhardware_t { int nr_boards; struct rtr_id *rtr_queue; @@ -50,6 +57,36 @@ struct canhardware_t { struct candevice_t *candevice[MAX_HW_CARDS]; }; +/** + * struct candevice_t - CAN device/board structure + * @hwname: text string with board type + * @candev_idx: board index in canhardware_t.candevice[] + * @io_addr: IO/physical MEM address + * @res_addr: optional reset register port + * @dev_base_addr: CPU translated IO/virtual MEM address + * @flags: board flags: %PROGRAMMABLE_IRQ .. interrupt number + * can be programmed into board + * @nr_all_chips: number of chips present on the board + * @nr_82527_chips: number of Intel 8257 chips + * @nr_sja1000_chips: number of Philips SJA100 chips + * @chip: array of pointers to the chip structures + * @hwspecops: pointer to board specific operations + * @hosthardware_p: pointer to the root hardware structure + * + * The structure represent configuration and state of associated board. + * The driver infrastructure prepares this structure and calls + * board type specific board_register() function. The board support provided + * register function fills right function pointers in @hwspecops structure. + * Then driver setup calls functions init_hw_data(), init_chip_data(), + * init_chip_data(), init_obj_data() and program_irq(). Function init_hw_data() + * and init_chip_data() have to specify number and types of connected chips + * or objects respectively. + * The use of @nr_all_chips is preferred over use of fields @nr_82527_chips + * and @nr_sja1000_chips in the board non-specific functions. + * The @io_addr and @dev_base_addr is filled from module parameters + * to the same value. The request_io function can fix-up @dev_base_addr + * field if virtual address is different than bus address. + */ struct candevice_t { char *hwname; /* text board type */ int candev_idx; /* board index in canhardware_t.candevice[] */ @@ -57,10 +94,6 @@ struct candevice_t { unsigned long res_addr; /* optional seset register port */ unsigned long dev_base_addr; /* CPU translated IO/virtual MEM address */ unsigned int flags; - - /* Hardware chip configuration. In case of multiple chips *chip - * is the first in an array of chip_t structures. - */ int nr_all_chips; int nr_82527_chips; int nr_sja1000_chips; @@ -71,48 +104,65 @@ struct candevice_t { struct canhardware_t *hosthardware_p; }; +/** + * struct chip_t - CAN chip state and type information + * @chip_type: text string describing chip type + * @chip_idx: index of the chip in candevice_t.chip[] array + * @chip_irq: chip interrupt number if any + * @chip_base_addr: chip base address in the CPU IO or virtual memory space + * @flags: chip flags: %CHIP_CONFIGURED .. chip is configured, + * %CHIP_SEGMENTED .. access to the chip is segmented (mainly for i82527 chips) + * @clock: chip base clock frequency in Hz + * @write_register: write chip register function copy - + * @read_register: read chip register function copy + * @sja_cdr_reg: SJA specific register - + * holds hardware specific options for the Clock Divider + * register. Options defined in the sja1000.h file: + * %CDR_CLKOUT_MASK, %CDR_CLK_OFF, %CDR_RXINPEN, %CDR_CBP, %CDR_PELICAN + * @sja_ocr_reg: SJA specific register - + * hold hardware specific options for the Output Control + * register. Options defined in the sja1000.h file: + * %OCR_MODE_BIPHASE, %OCR_MODE_TEST, %OCR_MODE_NORMAL, %OCR_MODE_CLOCK, + * %OCR_TX0_LH, %OCR_TX1_ZZ. + * @int_cpu_reg: Intel specific register - + * holds hardware specific options for the CPU Interface + * register. Options defined in the i82527.h file: + * %iCPU_CEN, %iCPU_MUX, %iCPU_SLP, %iCPU_PWD, %iCPU_DMC, %iCPU_DSC, %iCPU_RST. + * @int_clk_reg: Intel specific register - + * holds hardware specific options for the Clock Out + * register. Options defined in the i82527.h file: + * %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1. + * @int_bus_reg: Intel specific register - + * holds hardware specific options for the Bus Configuration + * register. Options defined in the i82527.h file: + * %iBUS_DR0, %iBUS_DR1, %iBUS_DT1, %iBUS_POL, %iBUS_CBY. + * @msgobj: array of pointers to individual communication objects + * @chipspecops: pointer to the set of chip specific object filled by init_chip_data() function + * @hostdevice: pointer to chip hosting board + * @max_objects: maximal number of communication objects connected to this chip + * + * The fields @write_register and @read_register are copied from + * corresponding fields from @hwspecops structure + * (chip->hostdevice->hwspecops->write_register and + * chip->hostdevice->hwspecops->read_register) + * to speedup can_write_reg() and can_read_reg() functions. + */ struct chip_t { char *chip_type; int chip_idx; /* chip index in candevice_t.chip[] */ int chip_irq; unsigned long chip_base_addr; unsigned int flags; - int clock; // Chip clock in Hz + int clock; /* Chip clock in Hz */ - /* This is copy of the chip->hostdevice->hwspecops->read_register - * and the chip->hostdevice->hwspecops->write_register. - * The pointers were added for performance reasons, and are initialized - * by init_chip_struct() from values given by hardware specific init_hwspecops(). - */ void (*write_register)(unsigned char data,unsigned long address); unsigned (*read_register)(unsigned long address); - /* sja_cdr_reg holds hardware specific options for the Clock Divider - * register. Options defined in the sja1000.h file: - * CDR_CLKOUT_MASK, CDR_CLK_OFF, CDR_RXINPEN, CDR_CBP, CDR_PELICAN - * - * sja_ocr_reg holds hardware specific options for the Output Control - * register. Options defined in the sja1000.h file: - * OCR_MODE_BIPHASE, OCR_MODE_TEST, OCR_MODE_NORMAL, OCR_MODE_CLOCK, - * OCR_TX0_LH, OCR_TX1_ZZ. - * - * int_clk_reg holds hardware specific options for the Clock Out - * register. Options defined in the i82527.h file: - * iCLK_CD0, iCLK_CD1, iCLK_CD2, iCLK_CD3, iCLK_SL0, iCLK_SL1. - * - * int_bus_reg holds hardware specific options for the Bus Configuration - * register. Options defined in the i82527.h file: - * iBUS_DR0, iBUS_DR1, iBUS_DT1, iBUS_POL, iBUS_CBY. - * - * int_cpu_reg holds hardware specific options for the CPU Interface - * register. Options defined in the i82527.h file: - * iCPU_CEN, iCPU_MUX, iCPU_SLP, iCPU_PWD, iCPU_DMC, iCPU_DSC, iCPU_RST. - */ - unsigned short sja_cdr_reg; // sja1000 only! - unsigned short sja_ocr_reg; // sja1000 only! - unsigned short int_cpu_reg; // intel 82527 only! - unsigned short int_clk_reg; // intel 82527 only! - unsigned short int_bus_reg; // intel 82527 only! + unsigned short sja_cdr_reg; /* sja1000 only! */ + unsigned short sja_ocr_reg; /* sja1000 only! */ + unsigned short int_cpu_reg; /* intel 82527 only! */ + unsigned short int_clk_reg; /* intel 82527 only! */ + unsigned short int_bus_reg; /* intel 82527 only! */ struct msgobj_t *msgobj[MAX_MSGOBJS]; @@ -123,6 +173,25 @@ struct chip_t { int max_objects; /* 1 for sja1000, 15 for */ }; +/** + * struct msgobj_t - structure holding communication object state + * @obj_base_addr: + * @minor: associated device minor number + * @object: object number in chip_t structure +1 + * @flags: message object flags + * @ret: field holding status of the last Tx operation + * @qends: pointer to message object corresponding ends structure + * @tx_qedge: edge corresponding to transmitted message + * @tx_slot: slot holding transmitted message, slot is taken from + * canque_test_outslot() call and is freed by canque_free_outslot() + * or rescheduled canque_again_outslot() + * @rx_msg: temporary storage to hold received messages before + * calling to canque_filter_msg2edges() + * @hostchip: pointer to the &chip_t structure this object belongs to + * @obj_used: counter of users (associated file structures for Linux + * userspace clients) of this object + * @obj_users: list of user structures of type &canuser_t. + */ struct msgobj_t { unsigned long obj_base_addr; unsigned int minor; /* associated device minor number */ @@ -143,6 +212,16 @@ struct msgobj_t { #define CAN_USER_MAGIC 0x05402033 +/** + * struct canuser_t - structure holding CAN user/client state + * @peers: for connection into list of object users + * @qends: pointer to the ends structure corresponding for this user + * @file: pointer to open device file state structure + * @msgobj: communication object the user is connected to + * @rx_edge0: default receive queue for filter IOCTL + * @magic: magic number to check consistency when pointer is retrieved + * from file private field + */ struct canuser_t { struct list_head peers; struct canque_ends_t *qends; @@ -152,6 +231,25 @@ struct canuser_t { int magic; }; +/** + * struct hwspecops_t - hardware/board specific operations + * @request_io: reserve io or memory range for can board + * @release_io: free reserved io memory range + * @reset: hardware reset routine + * @init_hw_data: called to initialize &candevice_t structure, mainly + * @res_add, @nr_all_chips, @nr_82527_chips, @nr_sja1000_chips + * and @flags fields + * @init_chip_data: called initialize each &chip_t structure, mainly + * @chip_type, @chip_base_addr, @clock and chip specific registers. + * It is responsible to setup &chip_t->@chipspecops functions + * for non-standard chip types (type other than "i82527", "sja1000" or "sja1000p") + * @init_obj_data: called initialize each &msgobj_t structure, + * mainly @obj_base_addr field. + * @program_irq: program interrupt generation hardware of the board + * if flag %PROGRAMMABLE_IRQ is present for specified device/board + * @write_register: low level write register routine + * @read_register: low level read register routine + */ struct hwspecops_t { int (*request_io)(struct candevice_t *candev); int (*release_io)(struct candevice_t *candev); @@ -164,6 +262,28 @@ struct hwspecops_t { unsigned (*read_register)(unsigned long address); }; +/** + * struct chipspecops_t - can controller chip specific operations + * @chip_config: CAN chip configuration + * @baud_rate: set communication parameters + * @standard_mask: setup of mask for message filtering + * @extended_mask: setup of extended mask for message filtering + * @message15_mask: set mask of i82527 message object 15 + * @clear_objects: clears state of all message object residing in chip + * @config_irqs: tunes chip hardware interrupt delivery + * @pre_read_config: prepares message object for message reception + * @pre_write_config: prepares message object for message transmission + * @send_msg: initiate message transmission + * @remote_request: configures message object and asks for RTR message + * @check_tx_stat: checks state of transmission engine + * @wakeup_tx: wakeup TX processing + * @enable_configuration: enable chip configuration mode + * @disable_configuration: disable chip configuration mode + * @set_btregs: configures bitrate registers + * @start_chip: starts chip message processing + * @stop_chip: stops chip message processing + * @irq_handler: interrupt service routine + */ struct chipspecops_t { int (*chip_config)(struct chip_t *chip); int (*baud_rate)(struct chip_t *chip, int rate, int clock, int sjw, @@ -202,11 +322,7 @@ struct mem_addr { struct rtr_id { unsigned long id; struct canmsg_t *rtr_message; -#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,3,0)) - struct wait_queue *rtr_wq; -#else - struct __wait_queue_head rtr_wq; -#endif + wait_queue_head_t rtr_wq; struct rtr_id *next; };