X-Git-Url: http://rtime.felk.cvut.cz/gitweb/lincan.git/blobdiff_plain/d659fb1c5ce646e10820cfd349d8a4220d1ee67d..2a4663dd0b20d96d1ffe20993dd0c63ed2ca9f20:/lincan/src/kv_pcican.c diff --git a/lincan/src/kv_pcican.c b/lincan/src/kv_pcican.c index e7f36e3..eb344b4 100644 --- a/lincan/src/kv_pcican.c +++ b/lincan/src/kv_pcican.c @@ -4,7 +4,7 @@ * Rewritten for new CAN queues by Pavel Pisa - OCERA team member * email:pisa@cmp.felk.cvut.cz * This software is released under the GPL-License. - * Version lincan-0.2 9 Jul 2003 + * Version lincan-0.3 17 Jun 2004 */ #include "../include/can.h" @@ -121,7 +121,7 @@ int kv_pcican_release_io(struct candevice_t *candev) } -void kv_pcican_write_register(unsigned char data, unsigned long address) +void kv_pcican_write_register(unsigned data, unsigned long address) { outb(data,address); } @@ -148,24 +148,24 @@ int kv_pcican_reset(struct candevice_t *candev) if(!candev->chip[chip_nr]) continue; chip=candev->chip[chip_nr]; - kv_pcican_write_register(MOD_RM, chip->chip_base_addr+SJAMOD); + kv_pcican_write_register(sjaMOD_RM, chip->chip_base_addr+SJAMOD); udelay(1000); cdr=kv_pcican_read_register(chip->chip_base_addr+SJACDR); - kv_pcican_write_register(cdr|CDR_PELICAN, chip->chip_base_addr+SJACDR); + kv_pcican_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR); kv_pcican_write_register(0, chip->chip_base_addr+SJAIER); i=20; kv_pcican_write_register(0, chip->chip_base_addr+SJAMOD); - while (kv_pcican_read_register(chip->chip_base_addr+SJAMOD)&MOD_RM){ + while (kv_pcican_read_register(chip->chip_base_addr+SJAMOD)&sjaMOD_RM){ if(!i--) return -ENODEV; udelay(1000); kv_pcican_write_register(0, chip->chip_base_addr+SJAMOD); } cdr=kv_pcican_read_register(chip->chip_base_addr+SJACDR); - kv_pcican_write_register(cdr|CDR_PELICAN, chip->chip_base_addr+SJACDR); + kv_pcican_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR); kv_pcican_write_register(0, chip->chip_base_addr+SJAIER); @@ -233,14 +233,14 @@ int kv_pcican_init_chip_data(struct candevice_t *candev, int chipnr) candev->chip[chipnr]->chip_irq=candev->sysdevptr.pcidev->irq; - candev->chip[chipnr]->chip_type="sja1000p"; + sja1000p_fill_chipspecops(candev->chip[chipnr]); candev->chip[chipnr]->chip_base_addr= candev->io_addr+chipnr*KV_PCICAN_BYTES_PER_CIRCUIT; candev->chip[chipnr]->flags = 0; candev->chip[chipnr]->int_cpu_reg = 0; candev->chip[chipnr]->int_clk_reg = 0; candev->chip[chipnr]->int_bus_reg = 0; - candev->chip[chipnr]->sja_cdr_reg = CDR_CBP | CDR_CLK_OFF; + candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CBP | sjaCDR_CLK_OFF; candev->chip[chipnr]->sja_ocr_reg = KV_PCICAN_OCR_DEFAULT_STD; candev->chip[chipnr]->clock = 16000000; candev->chip[chipnr]->flags |= CHIP_IRQ_PCI;