X-Git-Url: http://rtime.felk.cvut.cz/gitweb/lincan.git/blobdiff_plain/cc1afb21bdc089426652f21769164645cae062fd..243fec4450d3a3246f3f0d92751a95daef7c1503:/embedded/arch/arm/mach-lpc21xx/defines/LPC214x.h

diff --git a/embedded/arch/arm/mach-lpc21xx/defines/LPC214x.h b/embedded/arch/arm/mach-lpc21xx/defines/LPC214x.h
index d6a95d4..d1b428a 100644
--- a/embedded/arch/arm/mach-lpc21xx/defines/LPC214x.h
+++ b/embedded/arch/arm/mach-lpc21xx/defines/LPC214x.h
@@ -1,7 +1,7 @@
 /******************************************************************************
  *
- * $RCSfile: LPC214x.h,v $
- * $Revision: 1.4 $
+ * $RCSfile$
+ * $Revision$
  *
  * Header file for Philips LPC214x ARM Processors 
  * Copyright 2006 Pavel Pisa <pisa@cmp.felk.cvut.cz>
@@ -147,19 +147,19 @@
 
 #define ADC1             ((adc214xRegs_t *)0xE0060000)
 
-#define AD1CR            ADC0->cr       // Control Register 
-#define AD1GDR           ADC0->gdr	// Global Data Register
-#define AD1GSR           ADC0->gsr	// Global Start Register
-#define AD1INTEN         ADC0->inten	// Interrupt Enable Register
-#define AD1DR0           ADC0->dr0	// Channel 0 Data Register
-#define AD1DR1           ADC0->dr1	// Channel 1 Data Register
-#define AD1DR2           ADC0->dr2	// Channel 2 Data Register
-#define AD1DR3           ADC0->dr3	// Channel 3 Data Register
-#define AD1DR4           ADC0->dr4	// Channel 4 Data Register
-#define AD1DR5           ADC0->dr5	// Channel 5 Data Register
-#define AD1DR6           ADC0->dr6	// Channel 6 Data Register
-#define AD1DR7           ADC0->dr7	// Channel 7 Data Register
-#define AD1STAT          ADC0->stat	// Status Register
+#define AD1CR            ADC1->cr       // Control Register 
+#define AD1GDR           ADC1->gdr	// Global Data Register
+#define AD1GSR           ADC1->gsr	// Global Start Register
+#define AD1INTEN         ADC1->inten	// Interrupt Enable Register
+#define AD1DR0           ADC1->dr0	// Channel 0 Data Register
+#define AD1DR1           ADC1->dr1	// Channel 1 Data Register
+#define AD1DR2           ADC1->dr2	// Channel 2 Data Register
+#define AD1DR3           ADC1->dr3	// Channel 3 Data Register
+#define AD1DR4           ADC1->dr4	// Channel 4 Data Register
+#define AD1DR5           ADC1->dr5	// Channel 5 Data Register
+#define AD1DR6           ADC1->dr6	// Channel 6 Data Register
+#define AD1DR7           ADC1->dr7	// Channel 7 Data Register
+#define AD1STAT          ADC1->stat	// Status Register
 
 
 #endif /*INC_LPC21xx_H*/