X-Git-Url: http://rtime.felk.cvut.cz/gitweb/lincan.git/blobdiff_plain/cc1afb21bdc089426652f21769164645cae062fd..243fec4450d3a3246f3f0d92751a95daef7c1503:/embedded/arch/arm/generic/defines/cpu_def.h diff --git a/embedded/arch/arm/generic/defines/cpu_def.h b/embedded/arch/arm/generic/defines/cpu_def.h index 8c7b97d..c03ff6e 100644 --- a/embedded/arch/arm/generic/defines/cpu_def.h +++ b/embedded/arch/arm/generic/defines/cpu_def.h @@ -47,31 +47,12 @@ struct undef_hook { int register_undef_hook(struct undef_hook *hook); -#define NR_IRQS 256 +/* Low level CPU specific IRQ handling code */ -typedef struct irq_handler { - void (*handler)(int, void *, struct pt_regs *); - unsigned long flags; - void *dev_id; - const char *devname; - struct irq_handler *next; - short vectno; -} irq_handler_t; +#if !defined(__thumb__) +/* Regular 32-bit ARM architecture */ -#define IRQH_ON_LIST 0x100 /* handler is used */ - -extern irq_handler_t *irq_array[NR_IRQS]; -extern void *irq_vec[NR_IRQS]; - -int add_irq_handler(int vectno,irq_handler_t *handler); - -int del_irq_handler(int vectno,irq_handler_t *handler); - -int test_irq_handler(int vectno,const irq_handler_t *handler); - -void irq_redirect2vector(int vectno,struct pt_regs *regs); - -/* IRQ handling code */ +#define WITH_IRQ_HANDLER_ARGS #define sti() \ ({ \ @@ -129,7 +110,7 @@ void irq_redirect2vector(int vectno,struct pt_regs *regs); /* FIQ handling code */ -#define fiq_sti() \ +#define fiq_sti() \ ({ \ unsigned long temp; \ __asm__ __volatile__( \ @@ -141,7 +122,7 @@ void irq_redirect2vector(int vectno,struct pt_regs *regs); : "memory", "cc"); \ }) -#define fiq_cli() \ +#define fiq_cli() \ ({ \ unsigned long temp; \ __asm__ __volatile__( \ @@ -153,7 +134,7 @@ void irq_redirect2vector(int vectno,struct pt_regs *regs); : "memory", "cc"); \ }) -#define fiq_save_and_cli(flags) \ +#define fiq_save_and_cli(flags) \ ({ \ unsigned long temp; \ (void) (&temp == &flags); \ @@ -166,6 +147,89 @@ void irq_redirect2vector(int vectno,struct pt_regs *regs); : "memory", "cc"); \ }) +#elif defined(__thumb2__) || defined (__ARM_ARCH_6M__) +/* ARM Cortex-M3 architecture */ + +/* The interrupts are not delivered with argument, + it is retrieved independent way - irq_arch_get_irqidx */ +#undef WITH_IRQ_HANDLER_ARGS + +/* Offset between first interrupt source and exception table base */ +#define IRQ_IRQIDX_OFFSET 16 + +#define sti() \ + ({ \ + __asm__ __volatile__( \ + "cpsie i @ sti\n" \ + : : : "memory", "cc"); \ + }) + +#define cli() \ + ({ \ + __asm__ __volatile__( \ + "cpsid i @ cli\n" \ + : : : "memory", "cc"); \ + }) + +#define save_and_cli(flags) \ + ({ \ + unsigned long temp; \ + (void) (&temp == &flags); \ + __asm__ __volatile__( \ + "mrs %0, primask @ save_and_cli\n" \ +" cpsid i\n" \ + : "=r" (flags) \ + : \ + : "memory", "cc"); \ + }) + +#define save_flags(flags) \ + ({ \ + unsigned long temp; \ + (void) (&temp == &flags); \ + __asm__ __volatile__( \ + "mrs %0, primask @ save_flags\n" \ + : "=r" (flags) \ + : \ + : "memory", "cc"); \ + }) + +#define restore_flags(flags) \ + ({ \ + __asm__ __volatile__( \ + "msr primask, %0 @ restore_flags\n" \ + : \ + : "r" (flags) \ + : "memory", "cc"); \ + }) + +#define irq_arch_get_irqidx() \ + ({ \ + unsigned long ipsr; \ + __asm__ __volatile__( \ + "mrs %0, ipsr @ get irqidx\n" \ + : "=r" (ipsr) ); \ + ipsr; \ + }) + +#else /*defined(__thumb__)*/ + +#define WITH_IRQ_HANDLER_ARGS +/* Regular ARM architecture in THUMB mode */ + +void irq_fnc_sti(void); +#define sti irq_fnc_sti +void irq_fnc_cli(void); +#define cli irq_fnc_cli +unsigned long irq_fnc_save_and_cli(void); +#define save_and_cli(_flags) ((_flags)=irq_fnc_save_and_cli()) +unsigned long irq_fnc_save_flags(void); +#define save_flags(_flags) ((_flags)=irq_fnc_save_flags()) +void irq_fnc_restore_flags(unsigned long flags); +#define restore_flags irq_fnc_restore_flags + +#endif /*defined(__thumb__)*/ + void __cpu_coherent_range(unsigned long start, unsigned long end); static inline void flush_icache_range(unsigned long start, unsigned long end) @@ -231,9 +295,20 @@ static inline int test_and_set_bit(int nr, volatile unsigned long *addr) return r&m?1:0; } +#if defined(__thumb2__) || defined (__ARM_ARCH_6M__) + +/* DMB, DSB, ISB */ + +#define __memory_barrier() \ + __asm__ __volatile__("dmb": : : "memory") + +#else /* old plain ARM architecture */ + #define __memory_barrier() \ __asm__ __volatile__("": : : "memory") +#endif + /*masked fields macros*/ #define __val2mfld(mask,val) (((mask)&~((mask)<<1))*(val)&(mask)) @@ -247,16 +322,63 @@ static inline unsigned char inb(unsigned int port) { return *(volatile unsigned char *)(port); } -#endif /* _ARM_CPU_DEF_H */ - - - - - - - - - - +#define _WITHIN_CPU_DEF_H +#include +#undef _WITHIN_CPU_DEF_H + +extern void **irq_context_table; +extern irq_handler_t **irq_handler_table; +extern unsigned int irq_table_size; + +/* Arithmetic functions */ +#if 0 +/* ARM v5E architecture - DSP extension */ + +#define sat_add_slsl(__x,__y) \ + __asm__ (" qadd %0,%0,%2\n" \ + : "=r"(__x) \ + : "0" ((long)__x), "r" ((long)__y) : "cc"); \ + +#define sat_sub_slsl(__x,__y) \ + __asm__ (" qsub %0,%0,%2\n" \ + : "=r"(__x) \ + : "0" ((long)__x), "r" ((long)__y) : "cc"); \ + +#elif !defined(__thumb__) +/* Regular 32-bit ARM architecture */ + +#define sat_add_slsl(__x,__y) \ + __asm__ (" adds %0,%2\n" \ + " eorvs %0,%2,#0x80000000\n" \ + " sbcvs %0,%0,%2\n" \ + : "=r"(__x) \ + : "0" ((long)__x), "r" ((long)__y) : "cc"); \ + +#define sat_sub_slsl(__x,__y) \ + __asm__ (" subs %0,%2\n" \ + " eorvs %0,%2,#0x80000000\n" \ + " sbcvs %0,%0,%2\n" \ + : "=r"(__x) \ + : "0" ((long)__x), "r" ((long)__y) : "cc"); \ + +#elif defined(__thumb2__) || defined (__ARM_ARCH_6M__) + +#define sat_add_slsl(__x,__y) \ + __asm__ (" adds %0,%2\n" \ + " itt vs\n" \ + " eorsvs %0,%3,%2\n" \ + " sbcsvs %0,%0,%2\n" \ + : "=r"(__x) \ + : "0" ((long)__x), "r" ((long)__y), "r" (0x80000000): "cc"); \ + +#define sat_sub_slsl(__x,__y) \ + __asm__ (" subs %0,%2\n" \ + " itt vs\n" \ + " eorsvs %0,%3,%2\n" \ + " sbcsvs %0,%0,%2\n" \ + : "=r"(__x) \ + : "0" ((long)__x), "r" ((long)__y), "r" (0x80000000) : "cc"); \ +#endif +#endif /* _ARM_CPU_DEF_H */