X-Git-Url: http://rtime.felk.cvut.cz/gitweb/lincan.git/blobdiff_plain/cb551cc1582f3b51cf17e80730bee3c2f0701c3f..04ac67cc3cac14cd601daacd0592121ec0b84012:/lincan/src/hms30c7202_can.c diff --git a/lincan/src/hms30c7202_can.c b/lincan/src/hms30c7202_can.c index 2bf38aa..0bc5045 100644 --- a/lincan/src/hms30c7202_can.c +++ b/lincan/src/hms30c7202_can.c @@ -1,13 +1,38 @@ -/* hms30c7202_can.c - Hynix HMS30c7202 ARM device specific code - * Linux CAN-bus device driver. - * Written by Sebastian Stolzenberg email:stolzi@sebastian-stolzenberg.de - * Based on code from Arnaud Westenberg email:arnaud@wanadoo.nl - * and Ake Hedman, eurosource, akhe@eurosource.se - * Rewritten for new CAN queues by Pavel Pisa - OCERA team member - * email:pisa@cmp.felk.cvut.cz - * This software is released under the GPL-License. - * Version lincan-0.2 9 Jul 2003 - */ +/**************************************************************************/ +/* File: hms30c7202_can.c - Hynix HMS30c7202 ARM integrated C_CAN handling*/ +/* */ +/* LinCAN - (Not only) Linux CAN bus driver */ +/* Copyright (C) 2002-2009 DCE FEE CTU Prague */ +/* Copyright (C) 2002-2009 Pavel Pisa */ +/* Copyright (C) 2004 Sebastian Stolzenberg */ +/* Funded by OCERA and FRESCOR IST projects */ +/* Based on CAN driver code by Arnaud Westenberg */ +/* and Ake Hedman, eurosource */ +/* */ +/* LinCAN is free software; you can redistribute it and/or modify it */ +/* under terms of the GNU General Public License as published by the */ +/* Free Software Foundation; either version 2, or (at your option) any */ +/* later version. LinCAN is distributed in the hope that it will be */ +/* useful, but WITHOUT ANY WARRANTY; without even the implied warranty */ +/* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU */ +/* General Public License for more details. You should have received a */ +/* copy of the GNU General Public License along with LinCAN; see file */ +/* COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, */ +/* Cambridge, MA 02139, USA. */ +/* */ +/* To allow use of LinCAN in the compact embedded systems firmware */ +/* and RT-executives (RTEMS for example), main authors agree with next */ +/* special exception: */ +/* */ +/* Including LinCAN header files in a file, instantiating LinCAN generics */ +/* or templates, or linking other files with LinCAN objects to produce */ +/* an application image/executable, does not by itself cause the */ +/* resulting application image/executable to be covered by */ +/* the GNU General Public License. */ +/* This exception does not however invalidate any other reasons */ +/* why the executable file might be covered by the GNU Public License. */ +/* Publication of enhanced or derived LinCAN files is required although. */ +/**************************************************************************/ #include @@ -31,7 +56,7 @@ * * The function hms30c7202_request_io() is used to reserve the io-memory. If your * hardware uses a dedicated memory range as hardware control registers you - * will have to add the code to reserve this memory as well. + * will have to add the code to reserve this memory as well. * %IO_RANGE is the io-memory range that gets reserved, please adjust according * your hardware. Example: #define IO_RANGE 0x100 for i82527 chips or * #define IO_RANGE 0x20 for sja1000 chips in basic CAN mode. @@ -40,14 +65,14 @@ */ int hms30c7202_request_io(struct candevice_t *candev) { - DEBUGMSG("(c%d)calling hms30c7202_request_io(...)\n", pchip->chip_nr); + DEBUGMSG("(c%d)calling hms30c7202_request_io(...)\n", candev->chip[0]->chip_idx); if(!can_request_mem_region(candev->io_addr, IO_RANGE, DEVICE_NAME )) { CANMSG("hmsc30c7202_can failed to request mem region %lx.\n", (unsigned long)candev->io_addr ); } - - if (!( candev->dev_base_addr = (long)ioremap( candev->io_addr, IO_RANGE ))) { + + if (!( candev->dev_base_addr = ioremap( candev->io_addr, IO_RANGE ))) { DEBUGMSG( "Failed to map IO-memory: 0x%lx - 0x%lx, mapped to 0x%lx\n", (unsigned long)candev->io_addr, (unsigned long)candev->io_addr + IO_RANGE - 1, @@ -55,23 +80,23 @@ int hms30c7202_request_io(struct candevice_t *candev) can_release_mem_region(candev->io_addr, IO_RANGE); return -ENODEV; } else { - + DEBUGMSG( "Mapped IO-memory: 0x%lx - 0x%lx, mapped to 0x%lx\n", (unsigned long)candev->io_addr, (unsigned long)candev->io_addr + IO_RANGE - 1, (unsigned long)candev->dev_base_addr); - + } - + candev->chip[0]->chip_base_addr=candev->dev_base_addr; - + //pchip->write_register(0, pchip->vbase_addr + CCCR); //DEBUGMSG("C-CAN Control Register : 0x%.4lx\n", // (unsigned long)(c_can_read_reg_w( pchip->vbase_addr + CCCR))); candev->chip[0]->chipspecops->start_chip(candev->chip[0]); //DEBUGMSG("C-CAN Control Register : 0x%.4lx\n", // (unsigned long)(c_can_read_reg_w( pchip->vbase_addr + CCCR))); - + //DEBUGMSG("hms30c7202_can request i/o, leaving.\n"); return 0; } @@ -92,12 +117,12 @@ int hms30c7202_request_io(struct candevice_t *candev) int hms30c7202_release_io(struct candevice_t *candev) { u16 tempReg; - + //disable IRQ generation - tempReg = hms30c7202_read_reg_w(candev->chip[0], CCCR); + tempReg = c_can_read_reg_w(candev->chip[0], CCCR); c_can_config_irqs(candev->chip[0], 0); - + /* // clear all message objects for (i=1; i<=15; i++) { ccscan_write_register( @@ -119,13 +144,13 @@ int hms30c7202_release_io(struct candevice_t *candev) */ // power down HMS30c7202 - C_CAN candev->chip[0]->chipspecops->stop_chip(candev->chip[0]); - + // release I/O memory mapping - iounmap((void*)candev->dev_base_addr); - + iounmap(candev->dev_base_addr); + // Release the memory region can_release_mem_region(candev->io_addr, IO_RANGE); - + return 0; } @@ -143,8 +168,8 @@ int hms30c7202_reset( struct candevice_t *candev) { int i=0; int enableTest=0, disableTest=0; - struct chip_t *pchip = candev->chip[0]; - + struct canchip_t *pchip = candev->chip[0]; + enableTest = pchip->chipspecops->enable_configuration(pchip); disableTest = pchip->chipspecops->disable_configuration(pchip); if( enableTest || disableTest) { @@ -152,10 +177,10 @@ int hms30c7202_reset( struct candevice_t *candev) CANMSG("Please check your hardware.\n"); return -ENODEV; } - + /* Check busoff status */ - - while ( (hms30c7202_read_reg_w(pchip, CCSR) & SR_BOFF) && (i<=15)) { + + while ( (c_can_read_reg_w(pchip, CCSR) & SR_BOFF) && (i<=15)) { udelay(20000); i++; } @@ -166,7 +191,7 @@ int hms30c7202_reset( struct candevice_t *candev) } else DEBUGMSG("Chip0 reset status ok.\n"); - + //pchip->config_irqs(pchip, CR_MIE | CR_SIE | CR_EIE); return 0; } @@ -189,24 +214,24 @@ int hms30c7202_reset( struct candevice_t *candev) * Return Value: The function always returns zero * File: src/template.c */ -int hms30c7202_init_hw_data(struct candevice_t *candev) -/*( struct chip_t *pchip, u16 chip_nr, u16 startminor, u32 baseaddr, u8 irq )*/ +int hms30c7202_init_hw_data(struct candevice_t *candev) +/*( struct canchip_t *pchip, u16 chip_nr, u16 startminor, u32 baseaddr, u8 irq )*/ { // u32 intCntrVAddr = 0; - u32 gpioVAddr = 0; + can_ioptr_t gpioVAddr = 0; u32 tempReg = 0; u32 baseaddr=candev->io_addr; - - // if ( (!( intCntrVAddr = (u32)ioremap( 0x80024000, 0xCD ) )) - // & (! ( gpioVAddr = (u32)ioremap( 0x80023000, 0xAD ) ))) { + + // if ( (!( intCntrVAddr = ioremap( 0x80024000, 0xCD ) )) + // & (! ( gpioVAddr = ioremap( 0x80023000, 0xAD ) ))) { // DEBUGMSG("Failed to map Int and GPIO memory\n"); // return -EIO; // } - if ( ! ( gpioVAddr = (u32)ioremap( 0x80023000, 0xAD ) )) { + if ( ! ( gpioVAddr = ioremap( 0x80023000, 0xAD ) )) { DEBUGMSG("Failed to map GPIO memory\n"); return -EIO; } else { - + // DEBUGMSG( "Mapped Interrupt Controller IO-memory: 0x%lx - 0x%lx to 0x%lx\n", // (unsigned long)0X80024000, // (unsigned long)0X800240CC, @@ -216,50 +241,50 @@ int hms30c7202_init_hw_data(struct candevice_t *candev) (unsigned long)0X800240AC, (unsigned long)gpioVAddr); } - + if (baseaddr == 0x8002f000) { - // tempReg = readl(intCntrVAddr); + // tempReg = can_readl(intCntrVAddr); // DEBUGMSG("Read Interrupt Enable Register : 0x%.4lx\n",(long)tempReg); // DEBUGMSG("Trying to activate CAN0 Interrupt (Bit 18)\n"); - // writel((tempReg | (1<<18)), intCntrVAddr); - // tempReg = readl(intCntrVAddr); + // can_writel((tempReg | (1<<18)), intCntrVAddr); + // tempReg = can_readl(intCntrVAddr); // DEBUGMSG("Read changed Interrupt Enable Register : 0x%.4lx\n",(long)tempReg); - tempReg = readl(gpioVAddr + 0x5C); + tempReg = can_readl(gpioVAddr + 0x5C); DEBUGMSG("Read GPIO-C Enable Register : 0x%.4lx\n",(long)tempReg); DEBUGMSG("Trying to activate CAN0 (Bit 1 = 0 for CANTx0, Bit 2 = 0 for CANRx0,)\n"); - writel(tempReg & ~0x6, gpioVAddr + 0x5C); - tempReg = readl(gpioVAddr + 0x5C); + can_writel(tempReg & ~0x6, gpioVAddr + 0x5C); + tempReg = can_readl(gpioVAddr + 0x5C); DEBUGMSG("Read changed GPIO-C Enable Register : 0x%.4lx\n",(long)tempReg); - tempReg = readl(gpioVAddr + 0x44); + tempReg = can_readl(gpioVAddr + 0x44); DEBUGMSG("Read GPIO-C Direction Register : 0x%.4lx\n",(long)tempReg); DEBUGMSG("Trying to set CAN0 directions (Bit 1 = 0 for CANTx0 as OUT, Bit 2 = 1 for CANRx0 as IN,)\n"); - writel((tempReg & ~0x2) | 0x4, gpioVAddr + 0x44); - tempReg = readl(gpioVAddr + 0x44); + can_writel((tempReg & ~0x2) | 0x4, gpioVAddr + 0x44); + tempReg = can_readl(gpioVAddr + 0x44); DEBUGMSG("Read changed GPIO-C Direction Register : 0x%.4lx\n",(long)tempReg); } else if (baseaddr == 0x80030000) { - // tempReg = readl(intCntrVAddr); - // writel((tempReg | (1<<19)), intCntrVAddr); - tempReg = readl(gpioVAddr + 0x9C); + // tempReg = can_readl(intCntrVAddr); + // can_writel((tempReg | (1<<19)), intCntrVAddr); + tempReg = can_readl(gpioVAddr + 0x9C); DEBUGMSG("Read GPIO-E Enable Register : 0x%.8lx\n",(long)tempReg); DEBUGMSG("Trying to activate CAN1 (Bit 22 = 0 for CANRx1, Bit 23 = 0 for CANTx1,)\n"); - writel(tempReg & 0xFF3FFFFF, gpioVAddr + 0x9C); - tempReg = readl(gpioVAddr + 0x9C); + can_writel(tempReg & 0xFF3FFFFF, gpioVAddr + 0x9C); + tempReg = can_readl(gpioVAddr + 0x9C); DEBUGMSG("Read changed GPIO-E Enable Register : 0x%.8lx\n",(long)tempReg); - tempReg = readl(gpioVAddr + 0x84); + tempReg = can_readl(gpioVAddr + 0x84); DEBUGMSG("Read GPIO-E Direction Register : 0x%.8lx\n",(long)tempReg); DEBUGMSG("Trying to set CAN1 directions (Bit 22 = 1 for CANRx1 as IN, Bit 23 = 0 for CANTx1 as OUT,)\n"); - writel((tempReg & ~(1<<23)) | 1<<22, gpioVAddr + 0x84); - tempReg = readl(gpioVAddr + 0x84); + can_writel((tempReg & ~(1<<23)) | 1<<22, gpioVAddr + 0x84); + tempReg = can_readl(gpioVAddr + 0x84); DEBUGMSG("Read changed GPIO-E Direction Register : 0x%.8lx\n",(long)tempReg); } //DEBUGMSG("Current Interrupt Status Register (ISR): 0x%4.4lx\n", - // (long)readl(intCntrVAddr + 4)); + // (long)can_readl(intCntrVAddr + 4)); //DEBUGMSG("Current Interrupt ID: %d\n", - // (int)(readl(intCntrVAddr + 0x90) & 0xF)); + // (int)(can_readl(intCntrVAddr + 0x90) & 0xF)); // iounmap( (void*)intCntrVAddr); - iounmap( (void*)gpioVAddr ); + iounmap( gpioVAddr ); // DEBUGMSG( "Unmapped Interrupt Controller IO-memory: 0x%lx\n", // (unsigned long)intCntrVAddr); DEBUGMSG( "Unmapped GPIO IO-memory: 0x%lx\n", @@ -268,19 +293,11 @@ int hms30c7202_init_hw_data(struct candevice_t *candev) // Initialize chip data ( only one chip ) // pcandev->pchip[ 0 ]->powner = pcandev; /*pchip->ntype = CAN_CHIPTYPE_C_CAN;*/ - + candev->nr_82527_chips=0; candev->nr_sja1000_chips=0; candev->nr_all_chips=NR_C_CAN; - // Register hardware operations - candev->hwspecops->request_io = hms30c7202_request_io; - candev->hwspecops->release_io = hms30c7202_release_io; - candev->hwspecops->reset = hms30c7202_reset; - /* private register read and write routines used */ - candev->hwspecops->write_register = NULL; /*hms30c7202_write_register;*/ - candev->hwspecops->read_register = NULL; /*hms30c7202_read_register;*/ - return 0; } @@ -302,20 +319,20 @@ int hms30c7202_init_hw_data(struct candevice_t *candev) */ int hms30c7202_init_chip_data(struct candevice_t *candev, int chipnr) { - candev->chip[chipnr]->chip_type=CHIP_TYPE; - candev->chip[chipnr]->chip_base_addr=candev->io_addr; - - candev->chip[chipnr]->clock = 16000000; - + // Register chip operations + c_can_fill_chipspecops(candev->chip[chipnr]); + /* override chip provided default value */ candev->chip[chipnr]->max_objects = NR_MSGOBJ; - + + candev->chip[chipnr]->chip_base_addr=candev->io_addr; + + candev->chip[chipnr]->clock = 16000000/2; + /*candev->chip[chipnr]->int_clk_reg = 0x0; candev->chip[chipnr]->int_bus_reg = 0x0; candev->chip[chipnr]->sja_cdr_reg = 0x0; candev->chip[chipnr]->sja_ocr_reg = 0x0;*/ - - // Register chip operations - c_can_register(candev->chip[chipnr]->chipspecops); + return 0; } @@ -328,21 +345,21 @@ int hms30c7202_init_chip_data(struct candevice_t *candev, int chipnr) * * The function hms30c7202_init_obj_data() is used to initialize the hardware * structure containing information about the different message objects on the - * CAN chip. - * The entry @obj_base_addr represents the first memory address of the message - * object. + * CAN chip. + * The entry @obj_base_addr represents the first memory address of the message + * object. * Unless the hardware uses a segmented memory map, flags can be set zero. * Return Value: The function always returns zero * File: src/template.c */ -int hms30c7202_init_obj_data(struct chip_t *chip, int objnr) +int hms30c7202_init_obj_data(struct canchip_t *chip, int objnr) { - DEBUGMSG("(c%d)calling hms30c7202_init_obj_data( ...)\n", pchip->chip_nr); + DEBUGMSG("(c%d)calling hms30c7202_init_obj_data( ...)\n", chip->chip_idx); /* It seems, that there is no purpose to setup object base address */ chip->msgobj[objnr]->obj_base_addr=0; - + /*can_msgobj_test_fl(pmsgobj,RX_MODE_EXT);*/ return 0; } @@ -353,23 +370,27 @@ int hms30c7202_init_obj_data(struct chip_t *chip, int objnr) * @address: memory address to write to * * The function hms30c7202_write_register() is used to write to hardware registers - * on the CAN chip. You should only have to edit this function if your hardware - * uses some specific write process. + * on the CAN chip. The registers are mapped on 32 bit bus on hms30c7202 + * and thus registers span is twice as one defined by C_CAN manual and defines. + * This function compensates this difference. * Return Value: The function does not return a value * File: src/template.c */ -void hms30c7202_write_reg_w(const struct chip_t *pchip, u16 data, unsigned reg) +void hms30c7202_write_register(unsigned data, can_ioptr_t address) { - int i; - u32 address = pchip->chip_base_addr + reg; + unsigned long addr=can_ioptr2ulong(address); + int i; //unsigned long usecs = 1; - //DEBUGMSG("Trying to write 0x%u16x to address 0x%lx\n",data,address); + address = can_ulong2ioptr(((addr & C_CAN_REGOFFS_MASK) << 1) | + (addr & ~C_CAN_REGOFFS_MASK)); + + //DEBUGMSG("Trying to write 0x%u16x to address 0x%lx\n",data,address); - writew(data,address); + can_writew(data,address); //udelay( usecs ); - for (i=0; i<5; i++); + for (i=0; i<5; i++); } /** @@ -377,28 +398,31 @@ void hms30c7202_write_reg_w(const struct chip_t *pchip, u16 data, unsigned reg) * @address: memory address to read from * * The function hms30c7202_read_register() is used to read from hardware registers - * on the CAN chip. You should only have to edit this function if your hardware - * uses some specific read process. + * on the CAN chip. The registers are mapped on 32 bit bus on hms30c7202 + * and thus registers span is twice as one defined by C_CAN manual and defines. + * This function compensates this difference. * Return Value: The function returns the value stored in @address * File: src/template.c */ -u16 hms30c7202_read_reg_w(const struct chip_t *pchip, unsigned reg) +unsigned hms30c7202_read_register(can_ioptr_t address) { - u16 value, i; - u32 address = pchip->chip_base_addr + reg; - //unsigned long usecs = 1; + unsigned long addr=can_ioptr2ulong(address); + u16 value, i; + + address = can_ulong2ioptr(((addr & C_CAN_REGOFFS_MASK) << 1) | + (addr & ~C_CAN_REGOFFS_MASK)); - //DEBUGMSG("Trying to read from address 0x%lx :",address); + //DEBUGMSG("Trying to read from address 0x%lx :",address); - value = readw(address); - //udelay( usecs ); - for (i=0;i<5;i++); - value = readw(address); + value = can_readw(address); //udelay( usecs ); - for (i=0;i<5;i++); + for (i=0;i<5;i++); + value = can_readw(address); + //udelay( usecs ); + for (i=0;i<5;i++); - //DEBUGMSG("0x%u16x\n",value); - return value; + //DEBUGMSG("0x%u16x\n",value); + return value; } @@ -406,10 +430,10 @@ u16 hms30c7202_read_reg_w(const struct chip_t *pchip, unsigned reg) * hms30c7202_program_irq - program interrupts * @candev: Pointer to candevice/board structure * - * The function hms30c7202_program_irq() is used for hardware that uses + * The function hms30c7202_program_irq() is used for hardware that uses * programmable interrupts. If your hardware doesn't use programmable interrupts - * you should not set the @candevices_t->flags entry to %CANDEV_PROGRAMMABLE_IRQ and - * leave this function unedited. Again this function is hardware specific so + * you should not set the @candevices_t->flags entry to %CANDEV_PROGRAMMABLE_IRQ and + * leave this function unedited. Again this function is hardware specific so * there's no example code. * Return value: The function returns zero on success or %-ENODEV on failure * File: src/template.c @@ -427,9 +451,8 @@ int hms30c7202_register(struct hwspecops_t *hwspecops) hwspecops->init_hw_data = hms30c7202_init_hw_data; hwspecops->init_chip_data = hms30c7202_init_chip_data; hwspecops->init_obj_data = hms30c7202_init_obj_data; - /* private register read and write routines used */ - hwspecops->write_register = NULL; /*hms30c7202_write_register;*/ - hwspecops->read_register = NULL; /*hms30c7202_read_register;*/ + hwspecops->write_register = hms30c7202_write_register; + hwspecops->read_register = hms30c7202_read_register; hwspecops->program_irq = hms30c7202_program_irq; return 0; }