X-Git-Url: http://rtime.felk.cvut.cz/gitweb/lincan.git/blobdiff_plain/c6d6f58c34e1b6a4c03d1e86d1abf48eeb6f5624..a2eb4407e9772cf1057e7ea093250d5d38245c1d:/lincan/src/pcccan.c

diff --git a/lincan/src/pcccan.c b/lincan/src/pcccan.c
index 6f7b576..b568912 100644
--- a/lincan/src/pcccan.c
+++ b/lincan/src/pcccan.c
@@ -4,7 +4,7 @@
  * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
  * email:pisa@cmp.felk.cvut.cz
  * This software is released under the GPL-License.
- * Version lincan-0.2  9 Jul 2003
+ * Version lincan-0.3  17 Jun 2004
  */ 
 
 /* This file contains the low level functions for the pcccan-1 card from Gespac.
@@ -20,6 +20,8 @@
 int pcccan_irq=-1;
 unsigned long pcccan_base=0x0;
 
+static CAN_DEFINE_SPINLOCK(pcccan_port_lock);
+
 /*
  * IO_RANGE is the io-memory range that gets reserved, please adjust according
  * your hardware. Example: #define IO_RANGE 0x100 for i82527 chips or
@@ -150,7 +152,6 @@ int pcccan_init_hw_data(struct candevice_t *candev)
 	return 0;
 }
 
-#define CHIP_TYPE "i82527"
 /**
  * pcccan_init_chip_data - Initialize chips
  * @candev: Pointer to candevice/board structure
@@ -166,11 +167,11 @@ int pcccan_init_hw_data(struct candevice_t *candev)
  * The @clock entry holds the chip clock value in Hz.
  * The entry @sja_cdr_reg holds hardware specific options for the Clock Divider
  * register. Options defined in the %sja1000.h file:
- * %CDR_CLKOUT_MASK, %CDR_CLK_OFF, %CDR_RXINPEN, %CDR_CBP, %CDR_PELICAN
+ * %sjaCDR_CLKOUT_MASK, %sjaCDR_CLK_OFF, %sjaCDR_RXINPEN, %sjaCDR_CBP, %sjaCDR_PELICAN
  * The entry @sja_ocr_reg holds hardware specific options for the Output Control
  * register. Options defined in the %sja1000.h file:
- * %OCR_MODE_BIPHASE, %OCR_MODE_TEST, %OCR_MODE_NORMAL, %OCR_MODE_CLOCK,
- * %OCR_TX0_LH, %OCR_TX1_ZZ.
+ * %sjaOCR_MODE_BIPHASE, %sjaOCR_MODE_TEST, %sjaOCR_MODE_NORMAL, %sjaOCR_MODE_CLOCK,
+ * %sjaOCR_TX0_LH, %sjaOCR_TX1_ZZ.
  * The entry @int_clk_reg holds hardware specific options for the Clock Out
  * register. Options defined in the %i82527.h file:
  * %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1.
@@ -185,7 +186,7 @@ int pcccan_init_hw_data(struct candevice_t *candev)
  */
 int pcccan_init_chip_data(struct candevice_t *candev, int chipnr)
 {
-	candev->chip[chipnr]->chip_type=CHIP_TYPE;
+	i82527_fill_chipspecops(candev->chip[chipnr]);
 	candev->chip[chipnr]->chip_base_addr=candev->io_addr;
 	candev->chip[chipnr]->clock = 16000000;
 	candev->chip[chipnr]->int_cpu_reg = iCPU_DSC | iCPU_DMC;
@@ -216,10 +217,9 @@ int pcccan_init_chip_data(struct candevice_t *candev, int chipnr)
  * Return Value: The function always returns zero
  * File: src/pcccan.c
  */
-int pcccan_init_obj_data(struct chip_t *chip, int objnr)
+int pcccan_init_obj_data(struct canchip_t *chip, int objnr)
 {
 	chip->msgobj[objnr]->obj_base_addr=(objnr+1)*0x10;
-	chip->msgobj[objnr]->flags=0;
 	
 	return 0;
 }
@@ -252,12 +252,13 @@ int pcccan_program_irq(struct candevice_t *candev)
  * Return Value: The function does not return a value
  * File: src/pcccan.c
  */
-void pcccan_write_register(unsigned char data, unsigned long address)
+void pcccan_write_register(unsigned data, unsigned long address)
 {
-	disable_irq(pcccan_irq);
+	can_spin_irqflags_t flags;
+	can_spin_lock_irqsave(&pcccan_port_lock,flags);
 	outb(address - pcccan_base, pcccan_base+1);
 	outb(data, pcccan_base+6);
-	enable_irq(pcccan_irq);
+	can_spin_unlock_irqrestore(&pcccan_port_lock,flags);
 }
 
 /**
@@ -273,10 +274,11 @@ void pcccan_write_register(unsigned char data, unsigned long address)
 unsigned pcccan_read_register(unsigned long address)
 {
 	unsigned ret;
-	disable_irq(pcccan_irq);
+	can_spin_irqflags_t flags;
+	can_spin_lock_irqsave(&pcccan_port_lock,flags);
 	outb(address - pcccan_base, pcccan_base+1);
 	ret=inb(pcccan_base+2);
-	enable_irq(pcccan_irq);
+	can_spin_unlock_irqrestore(&pcccan_port_lock,flags);
 	return ret;
 
 }