X-Git-Url: http://rtime.felk.cvut.cz/gitweb/lincan.git/blobdiff_plain/c6d6f58c34e1b6a4c03d1e86d1abf48eeb6f5624..a2eb4407e9772cf1057e7ea093250d5d38245c1d:/lincan/src/pc_i03.c

diff --git a/lincan/src/pc_i03.c b/lincan/src/pc_i03.c
index 1e2c933..c724068 100644
--- a/lincan/src/pc_i03.c
+++ b/lincan/src/pc_i03.c
@@ -4,7 +4,7 @@
  * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
  * email:pisa@cmp.felk.cvut.cz
  * This software is released under the GPL-License.
- * Version lincan-0.2  9 Jul 2003
+ * Version lincan-0.3  17 Jun 2004
  */ 
 
 #include "../include/can.h"
@@ -93,7 +93,7 @@ int pci03_reset(struct candevice_t *candev)
 									
 	/* Check hardware reset status */
 	i=0;
-	while ( (pci03_read_register(pci03_base_addr + SJACR) & CR_RR)
+	while ( (pci03_read_register(pci03_base_addr + SJACR) & sjaCR_RR)
 								 && (i<=15) ) {
 		udelay(20000);
 		i++;
@@ -136,7 +136,6 @@ int pci03_init_hw_data(struct candevice_t *candev)
 	return 0;
 }
 
-#define CHIP_TYPE "sja1000"
 /**
  * pci03_init_chip_data - Initialize chips
  * @candev: Pointer to candevice/board structure
@@ -152,11 +151,11 @@ int pci03_init_hw_data(struct candevice_t *candev)
  * The @clock entry holds the chip clock value in Hz.
  * The entry @sja_cdr_reg holds hardware specific options for the Clock Divider
  * register. Options defined in the %sja1000.h file:
- * %CDR_CLKOUT_MASK, %CDR_CLK_OFF, %CDR_RXINPEN, %CDR_CBP, %CDR_PELICAN
+ * %sjaCDR_CLKOUT_MASK, %sjaCDR_CLK_OFF, %sjaCDR_RXINPEN, %sjaCDR_CBP, %sjaCDR_PELICAN
  * The entry @sja_ocr_reg holds hardware specific options for the Output Control
  * register. Options defined in the %sja1000.h file:
- * %OCR_MODE_BIPHASE, %OCR_MODE_TEST, %OCR_MODE_NORMAL, %OCR_MODE_CLOCK,
- * %OCR_TX0_LH, %OCR_TX1_ZZ.
+ * %sjaOCR_MODE_BIPHASE, %sjaOCR_MODE_TEST, %sjaOCR_MODE_NORMAL, %sjaOCR_MODE_CLOCK,
+ * %sjaOCR_TX0_LH, %sjaOCR_TX1_ZZ.
  * The entry @int_clk_reg holds hardware specific options for the Clock Out
  * register. Options defined in the %i82527.h file:
  * %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1.
@@ -168,13 +167,13 @@ int pci03_init_hw_data(struct candevice_t *candev)
  */
 int pci03_init_chip_data(struct candevice_t *candev, int chipnr)
 {
+	sja1000_fill_chipspecops(candev->chip[chipnr]);
 	pci03_base_addr = candev->io_addr;
-	candev->chip[chipnr]->chip_type=CHIP_TYPE;
 	candev->chip[chipnr]->chip_base_addr=candev->io_addr;
 	candev->chip[chipnr]->clock = 16000000;
-	candev->chip[chipnr]->sja_cdr_reg = CDR_CBP | CDR_CLK_OFF;
-	candev->chip[chipnr]->sja_ocr_reg = OCR_MODE_NORMAL | 
-							OCR_TX0_HL | OCR_TX1_LZ;
+	candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CBP | sjaCDR_CLK_OFF;
+	candev->chip[chipnr]->sja_ocr_reg = sjaOCR_MODE_NORMAL | 
+							sjaOCR_TX0_HL | sjaOCR_TX1_LZ;
 
 	return 0;
 }
@@ -196,10 +195,9 @@ int pci03_init_chip_data(struct candevice_t *candev, int chipnr)
  * Return Value: The function always returns zero
  * File: src/pc-i03.c
  */
-int pci03_init_obj_data(struct chip_t *chip, int objnr)
+int pci03_init_obj_data(struct canchip_t *chip, int objnr)
 {
 	chip->msgobj[objnr]->obj_base_addr=chip->chip_base_addr;
-	chip->msgobj[objnr]->flags=0;
 	
 	return 0;
 }
@@ -232,7 +230,7 @@ int pci03_program_irq(struct candevice_t *candev)
  * Return Value: The function does not return a value
  * File: src/pc-i03.c
  */
-void pci03_write_register(unsigned char data, unsigned long address)
+void pci03_write_register(unsigned data, unsigned long address)
 {
 	unsigned int *pci03_base_ptr;
 	unsigned short address_to_write;