X-Git-Url: http://rtime.felk.cvut.cz/gitweb/lincan.git/blobdiff_plain/c61a955168179d9b11a8f420979eed5cc24869c0..a4c9ead4b64bd4de307f375c2ff313a7a07a06e0:/lincan/src/pikronisa.c

diff --git a/lincan/src/pikronisa.c b/lincan/src/pikronisa.c
index a102ab0..db0977f 100644
--- a/lincan/src/pikronisa.c
+++ b/lincan/src/pikronisa.c
@@ -4,7 +4,7 @@
  * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
  * email:pisa@cmp.felk.cvut.cz
  * This software is released under the GPL-License.
- * Version lincan-0.2  9 Jul 2003
+ * Version lincan-0.3  17 Jun 2004
  */ 
 
 #include "../include/can.h"
@@ -91,24 +91,24 @@ int pikronisa_reset(struct candevice_t *candev)
 	struct chip_t *chip=candev->chip[0];
 	unsigned cdr;
 	
-	pikronisa_write_register(MOD_RM, chip->chip_base_addr+SJAMOD);
+	pikronisa_write_register(sjaMOD_RM, chip->chip_base_addr+SJAMOD);
 	udelay(1000);
 	
 	cdr=pikronisa_read_register(chip->chip_base_addr+SJACDR);
-	pikronisa_write_register(cdr|CDR_PELICAN, chip->chip_base_addr+SJACDR);
+	pikronisa_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
 
 	pikronisa_write_register(0, chip->chip_base_addr+SJAIER);
 
 	i=20;
 	pikronisa_write_register(0, chip->chip_base_addr+SJAMOD);
-	while (pikronisa_read_register(chip->chip_base_addr+SJAMOD)&MOD_RM){
+	while (pikronisa_read_register(chip->chip_base_addr+SJAMOD)&sjaMOD_RM){
 		if(!i--) return -ENODEV;
 		udelay(1000);
 		pikronisa_write_register(0, chip->chip_base_addr+SJAMOD);
 	}
 
 	cdr=pikronisa_read_register(chip->chip_base_addr+SJACDR);
-	pikronisa_write_register(cdr|CDR_PELICAN, chip->chip_base_addr+SJACDR);
+	pikronisa_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
 
 	pikronisa_write_register(0, chip->chip_base_addr+SJAIER);
 	
@@ -162,11 +162,11 @@ int pikronisa_init_hw_data(struct candevice_t *candev)
  * The @clock entry holds the chip clock value in Hz.
  * The entry @sja_cdr_reg holds hardware specific options for the Clock Divider
  * register. Options defined in the %sja1000.h file:
- * %CDR_CLKOUT_MASK, %CDR_CLK_OFF, %CDR_RXINPEN, %CDR_CBP, %CDR_PELICAN
+ * %sjaCDR_CLKOUT_MASK, %sjaCDR_CLK_OFF, %sjaCDR_RXINPEN, %sjaCDR_CBP, %sjaCDR_PELICAN
  * The entry @sja_ocr_reg holds hardware specific options for the Output Control
  * register. Options defined in the %sja1000.h file:
- * %OCR_MODE_BIPHASE, %OCR_MODE_TEST, %OCR_MODE_NORMAL, %OCR_MODE_CLOCK,
- * %OCR_TX0_LH, %OCR_TX1_ZZ.
+ * %sjaOCR_MODE_BIPHASE, %sjaOCR_MODE_TEST, %sjaOCR_MODE_NORMAL, %sjaOCR_MODE_CLOCK,
+ * %sjaOCR_TX0_LH, %sjaOCR_TX1_ZZ.
  * The entry @int_clk_reg holds hardware specific options for the Clock Out
  * register. Options defined in the %i82527.h file:
  * %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1.
@@ -186,8 +186,8 @@ int pikronisa_init_chip_data(struct candevice_t *candev, int chipnr)
 	candev->chip[chipnr]->clock = 24000000;
 	candev->chip[chipnr]->int_clk_reg = 0x0;
 	candev->chip[chipnr]->int_bus_reg = 0x0;
-	candev->chip[chipnr]->sja_cdr_reg = CDR_CBP | CDR_CLK_OFF;
-	candev->chip[chipnr]->sja_ocr_reg = OCR_MODE_NORMAL | OCR_TX0_LH;
+	candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CBP | sjaCDR_CLK_OFF;
+	candev->chip[chipnr]->sja_ocr_reg = sjaOCR_MODE_NORMAL | sjaOCR_TX0_LH;
 
 	return 0;
 }