X-Git-Url: http://rtime.felk.cvut.cz/gitweb/lincan.git/blobdiff_plain/c6162f4f8d268b7ba1d613459dd1519f587a698e..78bcd4f474077b9c45ba5f8aad2801c93df4fde8:/lincan/include/mscan.h

diff --git a/lincan/include/mscan.h b/lincan/include/mscan.h
index 0daf98c..a85a291 100644
--- a/lincan/include/mscan.h
+++ b/lincan/include/mscan.h
@@ -33,9 +33,53 @@
 /* Publication of enhanced or derived LinCAN files is required although.  */
 /**************************************************************************/
 
+#ifndef LINCAN_MSCAN_H
+#define LINCAN_MSCAN_H
 
+
+
+#define MPC5200_DBG 0
+
+/* Debug - coarse approach */
+#if MPC5200_DBG
+	/* standard LinCAN core debug - used only for MPC5200 driver part */
+	#define DEBUGMSG(fmt,args...) can_printk(KERN_ERR "lincan (debug): " fmt,##args)
+
+	/* dump specific parts of chip memory */	
+	#define DUMPREGS(canchip) dump_regs(canchip)
+	#define DUMPBUFF(canchip, offset) dump_buff(canchip, offset)
+	#define DUMPFLT(canchip) dump_filter(canchip)
+
+	/* Debug Tx Rx operations */
+	#define DEBUGTX(fmt,args...) can_printk(KERN_ERR "lincan (debug): " fmt,##args)
+	#define DEBUGRX(fmt,args...) can_printk(KERN_ERR "lincan (debug): " fmt,##args)
+#else
+	#define DUMPREGS(canchip)
+	#define DUMPBUFF(canchip, offset)
+	#define DUMPFLT(canchip)
+	#define DEBUGTX(fmt,args...)
+	#define DEBUGRX(fmt,args...)
+#endif	/* MPC5200_DBG */
+
+
+
+
+/* MSCAN register size */
 #define reg_t uint8_t
 
+
+/* Determine which clock source to use */
+/* 0 - use IP Bus clock                */
+/* 1 - use SYS_XTAL_IN frequency       */
+#define MPC5200_CLKSRC		1
+
+#if MPC5200_CLKSRC
+	#define MPC5200_CLK_FREQ	(MPC5200_SHARK_SYS_XTAL_FREQ/12)	/* 33MHz */
+#else
+	#define MPC5200_CLK_FREQ	(MPC5200_SHARK_IPB_FREQ/4)		/* 33MHz */
+#endif
+
+
 int mscan_chip_config(struct canchip_t *chip);
 int mscan_enable_configuration(struct canchip_t *chip);
 int mscan_disable_configuration(struct canchip_t *chip);
@@ -101,7 +145,7 @@ extern inline uint16_t can_read_reg_w(const struct canchip_t *pchip, unsigned re
 #define MSCAN_RIER	0x09		/* Receiver Interrupt Enable Register */
 #define MSCAN_TFLG	0x0c		/* Transmitter Flag Register */
 #define MSCAN_TIER	0x0d		/* Transmitter Interrupt Enable Register */
-#define MSCAN_TARG	0x10		/* Transmitter Message Abort Request Register */
+#define MSCAN_TARQ	0x10		/* Transmitter Message Abort Request Register */
 #define MSCAN_TAAK	0x11		/* Transmitter Message Abort Acknowledge Register */
 #define MSCAN_TBSEL	0x14		/* Transmitter Buffer Selection */
 #define MSCAN_IDAC	0x15		/* Identifier Acceptance Control Register */
@@ -183,7 +227,7 @@ enum mscan_rflg {
 	MSCAN_RFLG_WUPIF	= 1 << 7,		/* WakeUp Interrupt Flag - rw */
 	MSCAN_RFLG_CSCIF	= 1 << 6,		/* CAN Status Change Interrupt Flag - rw */
 	MSCAN_RFLG_RSTAT	= 0x30,			/* Receiver Status Bits: 0-RxOK, 1-RxWRN, 2-RxERR, 3-BusOff - ro */
-	MSCAN_RFLG_TSTAT	= 0x0a,			/* Transmitter Status Bits: 0-TxOK, 1-TxWRN, 2-TxErr, 3-BusOff - ro */
+	MSCAN_RFLG_TSTAT	= 0x0c,			/* Transmitter Status Bits: 0-TxOK, 1-TxWRN, 2-TxErr, 3-BusOff - ro */
 	MSCAN_RFLG_OVRIF	= 1 << 1,		/* Overrun Interrupt Flag - rw */
 	MSCAN_RFLG_RXF		= 1 << 0,		/* Receive Buffer Full - rw */
 };
@@ -192,7 +236,7 @@ enum mscan_rier {
 	MSCAN_RIER_WUPIE	= 1 << 7,		/* WakeUp Interrupt Enable - rw */
 	MSCAN_RIER_CSCIE	= 1 << 6,		/* CAN Status Change Interrupt Enable - rw */
 	MSCAN_RIER_RSTATE	= 0x30,			/* Receiver Status Change Enable: 0-Never, 1-BusOff, 2-BusOff+RxErr, 3-All - rw */
-	MSCAN_RIER_TSTATE	= 0x0a,			/* Transmitter Status Change Enable: 0-Never, 1-BusOff, 2-BusOff+TxErr, 3-All - rw */
+	MSCAN_RIER_TSTATE	= 0x0c,			/* Transmitter Status Change Enable: 0-Never, 1-BusOff, 2-BusOff+TxErr, 3-All - rw */
 	MSCAN_RIER_OVRIE	= 1 << 1,		/* Overrun Interrupt Enable - rw */
 	MSCAN_RIER_RXFIE	= 1 << 0,		/* Receive Buffer Full Interrupt Enable - rw */
 };
@@ -281,3 +325,41 @@ struct mscan_msg_buffer{
 	uint8_t 	timestamp_h;		/* local timestamp - High byte - Read Only */
 	uint8_t 	timestamp_l;		/* local timestamp - Low byte - Read Only */
 };
+
+/* structure for memory layout of acceptance
+ * filter registers
+ */
+struct mscan_flt_regs{
+	uint8_t		acp_id_0;
+	uint8_t 	acp_id_1;
+	uint16_t 	spacer_0;
+
+	uint8_t 	acp_id_2;
+	uint8_t 	acp_id_3;
+	uint16_t 	spacer_1;
+
+	uint8_t 	acp_mask_0;
+	uint8_t 	acp_mask_1;
+	uint16_t 	spacer_2;
+
+	uint8_t 	acp_mask_2;
+	uint8_t 	acp_mask_3;
+	uint16_t 	spacer_3;
+
+	uint8_t		acp_id_4;
+	uint8_t 	acp_id_5;
+	uint16_t 	spacer_4;
+
+	uint8_t 	acp_id_6;
+	uint8_t 	acp_id_7;
+	uint16_t 	spacer_5;
+
+	uint8_t 	acp_mask_4;
+	uint8_t 	acp_mask_5;
+	uint16_t 	spacer_6;
+
+	uint8_t 	acp_mask_6;
+	uint8_t 	acp_mask_7;
+};
+
+#endif /* LINCAN_MSCAN_H */