X-Git-Url: http://rtime.felk.cvut.cz/gitweb/lincan.git/blobdiff_plain/9db780972e5c4a622a7f61bcc1e65d84fe52e07c..626f7414aee3ecd51ab35d093314919528f67b12:/lincan/src/pcm3680.c

diff --git a/lincan/src/pcm3680.c b/lincan/src/pcm3680.c
index 43b58f6..70cbb79 100644
--- a/lincan/src/pcm3680.c
+++ b/lincan/src/pcm3680.c
@@ -91,20 +91,20 @@ int pcm3680_reset(struct candevice_t *candev)
 	DEBUGMSG("Resetting pcm3680 hardware ...\n");
 	for(chipnr=0;chipnr<candev->nr_sja1000_chips;chipnr++) {
 		chip=candev->chip[chipnr];
-		pcm3680_write_register(MOD_RM, chip->chip_base_addr+SJAMOD);
+		pcm3680_write_register(sjaMOD_RM, chip->chip_base_addr+SJAMOD);
 		udelay(1000);
 		pcm3680_write_register(0x00, chip->chip_base_addr + SJAIER);
 		/* Write arbitrary data to reset chip */
 		pcm3680_write_register(0x01, chip->chip_base_addr + 0x100);
 		udelay(1000);
 		i=20;
-		while (pcm3680_read_register(chip->chip_base_addr+SJAMOD)&MOD_RM){
+		while (pcm3680_read_register(chip->chip_base_addr+SJAMOD)&sjaMOD_RM){
 			if(!i--) return -ENODEV;
 			udelay(1000);
 			pcm3680_write_register(0, chip->chip_base_addr+SJAMOD);
 		}
 		udelay(1000);
-		pcm3680_write_register(CDR_PELICAN, chip->chip_base_addr+SJACDR);
+		pcm3680_write_register(sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
 		pcm3680_write_register(0x00, chip->chip_base_addr + SJAIER);
 	}
 
@@ -156,11 +156,11 @@ int pcm3680_init_hw_data(struct candevice_t *candev)
  * The @clock entry holds the chip clock value in Hz.
  * The entry @sja_cdr_reg holds hardware specific options for the Clock Divider
  * register. Options defined in the %sja1000.h file:
- * %CDR_CLKOUT_MASK, %CDR_CLK_OFF, %CDR_RXINPEN, %CDR_CBP, %CDR_PELICAN
+ * %sjaCDR_CLKOUT_MASK, %sjaCDR_CLK_OFF, %sjaCDR_RXINPEN, %sjaCDR_CBP, %sjaCDR_PELICAN
  * The entry @sja_ocr_reg holds hardware specific options for the Output Control
  * register. Options defined in the %sja1000.h file:
- * %OCR_MODE_BIPHASE, %OCR_MODE_TEST, %OCR_MODE_NORMAL, %OCR_MODE_CLOCK,
- * %OCR_TX0_LH, %OCR_TX1_ZZ.
+ * %sjaOCR_MODE_BIPHASE, %sjaOCR_MODE_TEST, %sjaOCR_MODE_NORMAL, %sjaOCR_MODE_CLOCK,
+ * %sjaOCR_TX0_LH, %sjaOCR_TX1_ZZ.
  * The entry @int_clk_reg holds hardware specific options for the Clock Out
  * register. Options defined in the %i82527.h file:
  * %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1.
@@ -178,9 +178,9 @@ int pcm3680_init_chip_data(struct candevice_t *candev, int chipnr)
 	candev->chip[chipnr]->clock = 16000000;
 	candev->chip[chipnr]->int_clk_reg = 0x0;
 	candev->chip[chipnr]->int_bus_reg = 0x0;
-	candev->chip[chipnr]->sja_cdr_reg = CDR_CBP | CDR_CLK_OFF;
-	candev->chip[chipnr]->sja_ocr_reg = OCR_MODE_NORMAL |
-								OCR_TX0_LH;
+	candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CBP | sjaCDR_CLK_OFF;
+	candev->chip[chipnr]->sja_ocr_reg = sjaOCR_MODE_NORMAL |
+								sjaOCR_TX0_LH;
 
 	return 0;
 }