X-Git-Url: http://rtime.felk.cvut.cz/gitweb/lincan.git/blobdiff_plain/9db780972e5c4a622a7f61bcc1e65d84fe52e07c..626f7414aee3ecd51ab35d093314919528f67b12:/lincan/src/pccan.c

diff --git a/lincan/src/pccan.c b/lincan/src/pccan.c
index 57dcd3c..49ec50b 100644
--- a/lincan/src/pccan.c
+++ b/lincan/src/pccan.c
@@ -115,7 +115,7 @@ int pccanf_reset(struct candevice_t *candev)
 
 	/* Check hardware reset status */
 	i=0;
-	while ( (inb(candev->chip[0]->chip_base_addr+SJACR) & CR_RR)
+	while ( (inb(candev->chip[0]->chip_base_addr+SJACR) & sjaCR_RR)
 								 && (i<=15) ) {
 		udelay(20000);
 		i++;
@@ -149,7 +149,7 @@ int pccand_reset(struct candevice_t *candev)
 	for (chip_nr=0; chip_nr<2; chip_nr++) {
 		i=0;
 		while ( (inb(candev->chip[chip_nr]->chip_base_addr +
-						SJACR) & CR_RR) && (i<=15) ) {
+						SJACR) & sjaCR_RR) && (i<=15) ) {
 			udelay(20000);
 			i++;
 		}
@@ -200,7 +200,7 @@ int pccanq_reset(struct candevice_t *candev)
 	for (chip_nr=2; chip_nr<4; chip_nr++) {
 		i=0;
 		while( (inb(candev->chip[chip_nr]->chip_base_addr +
-						SJACR) & CR_RR) && (i<=15) ) {
+						SJACR) & sjaCR_RR) && (i<=15) ) {
 			udelay(20000);
 			i++;
 		}
@@ -263,9 +263,9 @@ int pccan_init_chip_data(struct candevice_t *candev, int chipnr)
 			candev->chip[chipnr]->int_clk_reg = 0;
 			candev->chip[chipnr]->int_bus_reg = 0;
 			candev->chip[chipnr]->sja_cdr_reg =
-								CDR_CLK_OFF;
+								sjaCDR_CLK_OFF;
 			candev->chip[chipnr]->sja_ocr_reg = 
-						OCR_MODE_NORMAL | OCR_TX0_LH;	
+						sjaOCR_MODE_NORMAL | sjaOCR_TX0_LH;	
 		}
 		candev->chip[chipnr]->chip_base_addr=0x1000*chipnr+0x2000+candev->io_addr;
 	}
@@ -276,9 +276,9 @@ int pccan_init_chip_data(struct candevice_t *candev, int chipnr)
 		candev->chip[chipnr]->int_cpu_reg = 0;
 		candev->chip[chipnr]->int_clk_reg = 0;
 		candev->chip[chipnr]->int_bus_reg = 0;
-		candev->chip[chipnr]->sja_cdr_reg = CDR_CLK_OFF;
+		candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CLK_OFF;
 		candev->chip[chipnr]->sja_ocr_reg = 
-						OCR_MODE_NORMAL | OCR_TX0_LH;	
+						sjaOCR_MODE_NORMAL | sjaOCR_TX0_LH;	
 	}
 
 	candev->chip[chipnr]->clock = 16000000;