X-Git-Url: http://rtime.felk.cvut.cz/gitweb/lincan.git/blobdiff_plain/9db780972e5c4a622a7f61bcc1e65d84fe52e07c..626f7414aee3ecd51ab35d093314919528f67b12:/lincan/src/ems_cpcpci.c diff --git a/lincan/src/ems_cpcpci.c b/lincan/src/ems_cpcpci.c index 6be99f3..c45c82a 100644 --- a/lincan/src/ems_cpcpci.c +++ b/lincan/src/ems_cpcpci.c @@ -137,14 +137,14 @@ void ems_cpcpci_write_register(unsigned data, unsigned long address) { address += ((address&(EMS_CPCPCI_BYTES_PER_CIRCUIT-1)) *(EMS_CPCPCI_BYTES_PER_REG-1)); - readb(data,address); + writeb(data,address); } unsigned ems_cpcpci_read_register(unsigned long address) { address += ((address&(EMS_CPCPCI_BYTES_PER_CIRCUIT-1)) *(EMS_CPCPCI_BYTES_PER_REG-1)); - return inb(address); + return readb(address); } int ems_cpcpci_reset(struct candevice_t *candev) @@ -164,24 +164,24 @@ int ems_cpcpci_reset(struct candevice_t *candev) if(!candev->chip[chip_nr]) continue; chip=candev->chip[chip_nr]; - ems_cpcpci_write_register(MOD_RM, chip->chip_base_addr+SJAMOD); + ems_cpcpci_write_register(sjaMOD_RM, chip->chip_base_addr+SJAMOD); udelay(1000); cdr=ems_cpcpci_read_register(chip->chip_base_addr+SJACDR); - ems_cpcpci_write_register(cdr|CDR_PELICAN, chip->chip_base_addr+SJACDR); + ems_cpcpci_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR); ems_cpcpci_write_register(0, chip->chip_base_addr+SJAIER); i=20; ems_cpcpci_write_register(0, chip->chip_base_addr+SJAMOD); - while (ems_cpcpci_read_register(chip->chip_base_addr+SJAMOD)&MOD_RM){ + while (ems_cpcpci_read_register(chip->chip_base_addr+SJAMOD)&sjaMOD_RM){ if(!i--) return -ENODEV; udelay(1000); ems_cpcpci_write_register(0, chip->chip_base_addr+SJAMOD); } cdr=ems_cpcpci_read_register(chip->chip_base_addr+SJACDR); - ems_cpcpci_write_register(cdr|CDR_PELICAN, chip->chip_base_addr+SJACDR); + ems_cpcpci_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR); ems_cpcpci_write_register(0, chip->chip_base_addr+SJAIER); @@ -249,7 +249,7 @@ int ems_cpcpci_init_chip_data(struct candevice_t *candev, int chipnr) candev->chip[chipnr]->int_cpu_reg = 0; candev->chip[chipnr]->int_clk_reg = 0; candev->chip[chipnr]->int_bus_reg = 0; - candev->chip[chipnr]->sja_cdr_reg = CDR_CBP | CDR_CLK_OFF; + candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CBP | sjaCDR_CLK_OFF; candev->chip[chipnr]->sja_ocr_reg = EMS_CPCPCI_OCR_DEFAULT_STD; candev->chip[chipnr]->clock = 8000000; candev->chip[chipnr]->flags |= CHIP_IRQ_PCI;