X-Git-Url: http://rtime.felk.cvut.cz/gitweb/lincan.git/blobdiff_plain/95c031e101c74ae6472a7e538f3128f67a490082..9c8ab08d7e8fca3916a7f91a3c001d151989137c:/lincan/include/c_can.h diff --git a/lincan/include/c_can.h b/lincan/include/c_can.h index 1c3bb8f..ab91541 100644 --- a/lincan/include/c_can.h +++ b/lincan/include/c_can.h @@ -1,20 +1,46 @@ -/* c_can.h - Hynix HMS30c7202 ARM generic C_CAN module handling - * Linux CAN-bus device driver. - * Written by Sebastian Stolzenberg email:stolzi@sebastian-stolzenberg.de - * Based on code from Arnaud Westenberg email:arnaud@wanadoo.nl - * and Ake Hedman, eurosource, akhe@eurosource.se - * Rewritten for new CAN queues by Pavel Pisa - OCERA team member - * email:pisa@cmp.felk.cvut.cz - * This software is released under the GPL-License. - * Version lincan-0.3 17 Jun 2004 - */ +/**************************************************************************/ +/* File: c_can.h - generic C_CAN Bosch IP core handling */ +/* The C_CAN core is found in Hynix HMS30c7202 and OKI OKI ML9620 devices */ +/* */ +/* LinCAN - (Not only) Linux CAN bus driver */ +/* Copyright (C) 2002-2009 DCE FEE CTU Prague */ +/* Copyright (C) 2002-2009 Pavel Pisa */ +/* Copyright (C) 2004 Sebastian Stolzenberg */ +/* Funded by OCERA and FRESCOR IST projects */ +/* Based on CAN driver code by Arnaud Westenberg */ +/* and Ake Hedman, eurosource */ +/* */ +/* LinCAN is free software; you can redistribute it and/or modify it */ +/* under terms of the GNU General Public License as published by the */ +/* Free Software Foundation; either version 2, or (at your option) any */ +/* later version. LinCAN is distributed in the hope that it will be */ +/* useful, but WITHOUT ANY WARRANTY; without even the implied warranty */ +/* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU */ +/* General Public License for more details. You should have received a */ +/* copy of the GNU General Public License along with LinCAN; see file */ +/* COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, */ +/* Cambridge, MA 02139, USA. */ +/* */ +/* To allow use of LinCAN in the compact embedded systems firmware */ +/* and RT-executives (RTEMS for example), main authors agree with next */ +/* special exception: */ +/* */ +/* Including LinCAN header files in a file, instantiating LinCAN generics */ +/* or templates, or linking other files with LinCAN objects to produce */ +/* an application image/executable, does not by itself cause the */ +/* resulting application image/executable to be covered by */ +/* the GNU General Public License. */ +/* This exception does not however invalidate any other reasons */ +/* why the executable file might be covered by the GNU Public License. */ +/* Publication of enhanced or derived LinCAN files is required although. */ +/**************************************************************************/ /* * optimized inline version, may it be, that it can be too fast for the chip */ extern inline void c_can_write_reg_w(const struct canchip_t *pchip, u16 data, unsigned reg) { - u32 address = pchip->chip_base_addr + reg; + can_ioptr_t address = pchip->chip_base_addr + reg; #ifndef CONFIG_OC_LINCAN_DYNAMICIO writew(data,address); #else /*CONFIG_OC_LINCAN_DYNAMICIO*/ @@ -24,7 +50,7 @@ extern inline void c_can_write_reg_w(const struct canchip_t *pchip, u16 data, un extern inline u16 c_can_read_reg_w(const struct canchip_t *pchip, unsigned reg) { - u32 address = pchip->chip_base_addr + reg; + can_ioptr_t address = pchip->chip_base_addr + reg; #ifndef CONFIG_OC_LINCAN_DYNAMICIO return readw(address); #else /*CONFIG_OC_LINCAN_DYNAMICIO*/ @@ -68,51 +94,69 @@ int c_can_register(struct chipspecops_t *chipspecops); void c_can_registerdump(struct canchip_t *pchip); +void c_can_if1_registerdump(struct canchip_t *pchip); + void c_can_irq_sync_activities(struct canchip_t *chip, struct msgobj_t *obj); -int c_can_irq_handler(int irq, struct canchip_t *chip); - -int c_can_fill_chipspecops(struct canchip_t *chip); - -/* BasicCAN mode address map */ -#define CCCR 0x0000 /* Control Register */ -#define CCSR 0x0004 /* Status Register */ -#define CCEC 0x0008 /* Error Counting Register */ -#define CCBT 0x000C /* Bit Timing Register */ -#define CCINTR 0x0010 /* Interrupt Register */ -#define CCTR 0x0014 /* Test Register */ -#define CCBRPE 0x0018 /* Baud Rate Prescaler Extension Register */ -#define CCCE 0x001C /* CAN Enable Register */ -#define CCTREQ1 0x0100 /* Transmission Request 1 Register */ -#define CCTREQ2 0x0104 /* Transmission Request 2 Register */ -#define CCND1 0x0120 /* New Data 1 Register */ -#define CCND2 0x0124 /* New Data 2 Register */ -#define CCINTP1 0x0140 /* Interrupt Pending 1 Register */ -#define CCINTP2 0x0144 /* Interrupt Pending 2 Register */ - -#define CCIF1CR 0x0020 /* Interface 1 Command Request Register */ -#define CCIF1CM 0x0024 /* IF1 Command Mask Register */ -#define CCIF1M1 0x0028 /* IF1 Mask 1 Register */ -#define CCIF1M2 0x002C /* IF1 Mask 2 Register */ -#define CCIF1A1 0x0030 /* IF1 Arbitration 1 Register */ -#define CCIF1A2 0x0034 /* IF1 Arbitration 2 Register */ -#define CCIF1DMC 0x0038 /* IF1 Message Control Register */ -#define CCIF1DA1 0x003C /* IF1 Data A 1 Register */ -#define CCIF1DA2 0x0040 /* IF1 Data A 2 Register */ -#define CCIF1DB1 0x0044 /* IF1 Data B 1 Register */ -#define CCIF1DB2 0x0048 /* IF1 Data B 2 Register */ - -#define CCIF2CR 0x0080 /* Interface 2 Command Request Register */ -#define CCIF2CM 0x0084 /* IF2 Command Mask Register */ -#define CCIF2M1 0x0088 /* IF2 Mask 1 Register */ -#define CCIF2M2 0x008C /* IF2 Mask 2 Register */ -#define CCIF2A1 0x0090 /* IF2 Arbitration 1 Register */ -#define CCIF2A2 0x0094 /* IF2 Arbitration 2 Register */ -#define CCIF2DMC 0x0098 /* IF2 Message Control Register */ -#define CCIF2DA1 0x009C /* IF2 Data A 1 Register */ -#define CCIF2DA2 0x00A0 /* IF2 Data A 2 Register */ -#define CCIF2DB1 0x00A4 /* IF2 Data B 1 Register */ -#define CCIF2DB2 0x00A8 /* IF2 Data B 2 Register */ +int c_can_irq_handler(int irq, struct canchip_t *pchip); + +int c_can_fill_chipspecops(struct canchip_t *pchip); + +/* The CCCE register is not implemented in version 1.2 of C_CAN */ +#undef C_CAN_WITH_CCCE + +/* The mask of C_CAN registers offsets */ +#define C_CAN_REGOFFS_MASK 0xFF + +/* SSEE C_CAN Memory map */ +/* BasicCAN offsets are multiplied by two */ +#define CCCR 0x00 /* Control Register */ +#define CCSR 0x02 /* Status Register */ +#define CCEC 0x04 /* Error Counting Register */ +#define CCBT 0x06 /* Bit Timing Register */ +#define CCINTR 0x08 /* Interrupt Register */ +#define CCTR 0x0A /* Test Register */ +#define CCBRPE 0x0C /* Baud Rate Prescaler Extension Register */ + +#ifdef C_CAN_WITH_CCCE +#define CCCE 0x0E /* CAN Enable Register */ +#endif /*C_CAN_WITH_CCCE*/ + +#define CCIF1CR 0x10 /* Interface 1 Command Request Register */ +#define CCIF1CM 0x12 /* IF1 Command Mask Register */ +#define CCIF1M1 0x14 /* IF1 Mask 1 Register */ +#define CCIF1M2 0x16 /* IF1 Mask 2 Register */ +#define CCIF1A1 0x18 /* IF1 Arbitration 1 Register */ +#define CCIF1A2 0x1A /* IF1 Arbitration 2 Register */ +#define CCIF1DMC 0x1C /* IF1 Message Control Register */ +#define CCIF1DA1 0x1E /* IF1 Data A 1 Register */ +#define CCIF1DA2 0x20 /* IF1 Data A 2 Register */ +#define CCIF1DB1 0x22 /* IF1 Data B 1 Register */ +#define CCIF1DB2 0x24 /* IF1 Data B 2 Register */ + +#define CCIF2CR 0x40 /* Interface 2 Command Request Register */ +#define CCIF2CM 0x42 /* IF2 Command Mask Register */ +#define CCIF2M1 0x44 /* IF2 Mask 1 Register */ +#define CCIF2M2 0x46 /* IF2 Mask 2 Register */ +#define CCIF2A1 0x48 /* IF2 Arbitration 1 Register */ +#define CCIF2A2 0x4A /* IF2 Arbitration 2 Register */ +#define CCIF2DMC 0x4C /* IF2 Message Control Register */ +#define CCIF2DA1 0x4E /* IF2 Data A 1 Register */ +#define CCIF2DA2 0x50 /* IF2 Data A 2 Register */ +#define CCIF2DB1 0x52 /* IF2 Data B 1 Register */ +#define CCIF2DB2 0x54 /* IF2 Data B 2 Register */ + +#define CCTREQ1 0x80 /* Transmission Request 1 Register */ +#define CCTREQ2 0x82 /* Transmission Request 2 Register */ + +#define CCND1 0x90 /* New Data 1 Register */ +#define CCND2 0x92 /* New Data 2 Register */ + +#define CCINTP1 0xA0 /* Interrupt Pending 1 Register */ +#define CCINTP2 0xA2 /* Interrupt Pending 2 Register */ + +#define CCIMV1 0xB0 /* Message Valid 1 Register */ +#define CCIMV2 0xB2 /* Message Valid 2 Register */ /* Control register */ enum c_can_BASIC_CR