X-Git-Url: http://rtime.felk.cvut.cz/gitweb/lincan.git/blobdiff_plain/6250b3805fb7e368adf1e3f7ca39c8cc617bccff..6234a9dc385e5a9258a84227b2eab09bbb099c27:/lincan/src/pccan.c diff --git a/lincan/src/pccan.c b/lincan/src/pccan.c index 4d877c6..289fa84 100644 --- a/lincan/src/pccan.c +++ b/lincan/src/pccan.c @@ -108,14 +108,14 @@ int pccanf_reset(struct candevice_t *candev) DEBUGMSG("Resetting pccanf/s hardware ...\n"); while (i < 1000000) { i++; - outb(0x00,candev->res_addr); + can_outb(0x00,candev->res_addr); } - outb(0x01,candev->res_addr); - outb(0x00,candev->chip[0]->chip_base_addr+SJACR); + can_outb(0x01,candev->res_addr); + can_outb(0x00,candev->chip[0]->chip_base_addr+SJACR); /* Check hardware reset status */ i=0; - while ( (inb(candev->chip[0]->chip_base_addr+SJACR) & sjaCR_RR) + while ( (can_inb(candev->chip[0]->chip_base_addr+SJACR) & sjaCR_RR) && (i<=15) ) { udelay(20000); i++; @@ -138,17 +138,17 @@ int pccand_reset(struct candevice_t *candev) DEBUGMSG("Resetting pccan-d hardware ...\n"); while (i < 1000000) { i++; - outb(0x00,candev->res_addr); + can_outb(0x00,candev->res_addr); } - outb(0x01,candev->res_addr); - outb(0x00,candev->chip[0]->chip_base_addr+SJACR); - outb(0x00,candev->chip[1]->chip_base_addr+SJACR); + can_outb(0x01,candev->res_addr); + can_outb(0x00,candev->chip[0]->chip_base_addr+SJACR); + can_outb(0x00,candev->chip[1]->chip_base_addr+SJACR); /* Check hardware reset status */ i=0; for (chip_nr=0; chip_nr<2; chip_nr++) { i=0; - while ( (inb(candev->chip[chip_nr]->chip_base_addr + + while ( (can_inb(candev->chip[chip_nr]->chip_base_addr + SJACR) & sjaCR_RR) && (i<=15) ) { udelay(20000); i++; @@ -174,17 +174,17 @@ int pccanq_reset(struct candevice_t *candev) DEBUGMSG("Resetting pccan-q hardware ...\n"); while (i < 100000) { i++; - outb(0x00,candev->res_addr); + can_outb(0x00,candev->res_addr); } outb_p(0x01,candev->res_addr); - outb(0x00,candev->chip[2]->chip_base_addr+SJACR); - outb(0x00,candev->chip[3]->chip_base_addr+SJACR); + can_outb(0x00,candev->chip[2]->chip_base_addr+SJACR); + can_outb(0x00,candev->chip[3]->chip_base_addr+SJACR); /* Check hardware reset status */ for (chip_nr=0; chip_nr<2; chip_nr++) { i=0; - while( (inb(candev->chip[chip_nr]->chip_base_addr + + while( (can_inb(candev->chip[chip_nr]->chip_base_addr + iCPU) & iCPU_RST) && (i<=15) ) { udelay(20000); i++; @@ -199,7 +199,7 @@ int pccanq_reset(struct candevice_t *candev) } for (chip_nr=2; chip_nr<4; chip_nr++) { i=0; - while( (inb(candev->chip[chip_nr]->chip_base_addr + + while( (can_inb(candev->chip[chip_nr]->chip_base_addr + SJACR) & sjaCR_RR) && (i<=15) ) { udelay(20000); i++; @@ -267,11 +267,11 @@ int pccan_init_chip_data(struct candevice_t *candev, int chipnr) candev->chip[chipnr]->sja_ocr_reg = sjaOCR_MODE_NORMAL | sjaOCR_TX0_LH; } - candev->chip[chipnr]->chip_base_addr=0x1000*chipnr+0x2000+candev->io_addr; + candev->chip[chipnr]->chip_base_addr=can_ioport2ioptr(0x1000*chipnr+0x2000+candev->io_addr); } else { sja1000_fill_chipspecops(candev->chip[chipnr]); - candev->chip[chipnr]->chip_base_addr=0x1000*chipnr+0x4000+candev->io_addr; + candev->chip[chipnr]->chip_base_addr=can_ioport2ioptr(0x1000*chipnr+0x4000+candev->io_addr); candev->chip[chipnr]->flags = 0; candev->chip[chipnr]->int_cpu_reg = 0; candev->chip[chipnr]->int_clk_reg = 0; @@ -330,22 +330,22 @@ int pccan_program_irq(struct candevice_t *candev) } } } - outb(irq_reg_value,0x6000+candev->io_addr); + can_outb(irq_reg_value,0x6000+candev->io_addr); DEBUGMSG("Configured pccan hardware interrupts\n"); - outb(0x80,0x6000+candev->io_addr+0x02); + can_outb(0x80,0x6000+candev->io_addr+0x02); DEBUGMSG("Selected pccan on-board 16 MHz oscillator\n"); return 0; } -inline void pccan_write_register(unsigned data, unsigned long address) +inline void pccan_write_register(unsigned data, can_ioptr_t address) { - outb(data,address); + can_outb(data,address); } -unsigned pccan_read_register(unsigned long address) +unsigned pccan_read_register(can_ioptr_t address) { - return inb(address); + return can_inb(address); } int pccanf_register(struct hwspecops_t *hwspecops)