X-Git-Url: http://rtime.felk.cvut.cz/gitweb/lincan.git/blobdiff_plain/4ee1fa3f095f7da94c8996d3f499273ff84c9023..b18e586453cf962a4032890f34d05a9fd362cf02:/lincan/include/mscan.h diff --git a/lincan/include/mscan.h b/lincan/include/mscan.h new file mode 100644 index 0000000..0daf98c --- /dev/null +++ b/lincan/include/mscan.h @@ -0,0 +1,283 @@ +/**************************************************************************/ +/* File: mscan.h - Freescale MPC5200 MSCAN controller support */ +/* */ +/* LinCAN - (Not only) Linux CAN bus driver */ +/* Copyright (C) 2002-2009 DCE FEE CTU Prague */ +/* Copyright (C) 2002-2009 Pavel Pisa */ +/* Copyright (C) 2007-2008 Martin Petera */ +/* Funded by OCERA and FRESCOR IST projects */ +/* Based on CAN driver code by Arnaud Westenberg */ +/* */ +/* LinCAN is free software; you can redistribute it and/or modify it */ +/* under terms of the GNU General Public License as published by the */ +/* Free Software Foundation; either version 2, or (at your option) any */ +/* later version. LinCAN is distributed in the hope that it will be */ +/* useful, but WITHOUT ANY WARRANTY; without even the implied warranty */ +/* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU */ +/* General Public License for more details. You should have received a */ +/* copy of the GNU General Public License along with LinCAN; see file */ +/* COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, */ +/* Cambridge, MA 02139, USA. */ +/* */ +/* To allow use of LinCAN in the compact embedded systems firmware */ +/* and RT-executives (RTEMS for example), main authors agree with next */ +/* special exception: */ +/* */ +/* Including LinCAN header files in a file, instantiating LinCAN generics */ +/* or templates, or linking other files with LinCAN objects to produce */ +/* an application image/executable, does not by itself cause the */ +/* resulting application image/executable to be covered by */ +/* the GNU General Public License. */ +/* This exception does not however invalidate any other reasons */ +/* why the executable file might be covered by the GNU Public License. */ +/* Publication of enhanced or derived LinCAN files is required although. */ +/**************************************************************************/ + + +#define reg_t uint8_t + +int mscan_chip_config(struct canchip_t *chip); +int mscan_enable_configuration(struct canchip_t *chip); +int mscan_disable_configuration(struct canchip_t *chip); + +int mscan_baud_rate(struct canchip_t *chip, int rate, int clock, int sjw, int sampl_pt, int flags); +int mscan_set_btregs(struct canchip_t *chip, unsigned short bcr0, unsigned short bcr1); + +int mscan_start_chip(struct canchip_t *chip); +int mscan_stop_chip(struct canchip_t *chip); +int mscan_attach_to_chip(struct canchip_t *chip); +int mscan_release_chip(struct canchip_t *chip); + +int mscan_standard_mask(struct canchip_t *chip, unsigned short code, unsigned short mask); +int mscan_extended_mask(struct canchip_t *chip, unsigned long code, unsigned long mask); +/* int mscan_message15_mask(int irq, struct canchip_t *chip); */ + +int mscan_pre_read_config(struct canchip_t *chip, struct msgobj_t *obj); +int mscan_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj, struct canmsg_t *msg); +int mscan_send_msg(struct canchip_t *chip, struct msgobj_t *obj, struct canmsg_t *msg); +int mscan_remote_request(struct canchip_t *chip, struct msgobj_t *obj); + +int mscan_irq_handler(int irq, struct canchip_t *chip); +/* int mscan_irq_accept(int irq, struct canchip_t *chip); */ +int mscan_config_irqs(struct canchip_t *chip, short irqs); + +int mscan_clear_objects(struct canchip_t *chip); +int mscan_check_tx_stat(struct canchip_t *chip); +int mscan_wakeup_tx(struct canchip_t *chip, struct msgobj_t *obj); +int mscan_filtch_rq(struct canchip_t *chip, struct msgobj_t * obj); + +int mscan_register(struct chipspecops_t *chipspecops); +int mscan_fill_chipspecops(struct canchip_t *chip); + +int mscan_reset_chip(struct canchip_t * chip); + +extern inline void can_write_reg_w(const struct canchip_t *pchip, uint16_t data, unsigned reg) +{ + can_ioptr_t address = pchip->chip_base_addr + reg; + #ifndef CONFIG_OC_LINCAN_DYNAMICIO + writew(data,address); + #else /*CONFIG_OC_LINCAN_DYNAMICIO*/ + pchip->write_register(data, address); + #endif /*CONFIG_OC_LINCAN_DYNAMICIO*/ +} + +extern inline uint16_t can_read_reg_w(const struct canchip_t *pchip, unsigned reg) +{ + can_ioptr_t address = pchip->chip_base_addr + reg; + #ifndef CONFIG_OC_LINCAN_DYNAMICIO + return readw(address); + #else /*CONFIG_OC_LINCAN_DYNAMICIO*/ + return pchip->read_register(address); + #endif /*CONFIG_OC_LINCAN_DYNAMICIO*/ +} + + +/* BasicCAN mode address map */ +#define MSCAN_CTL0 0x00 /* Control Register 0 */ +#define MSCAN_CTL1 0x01 /* Control Register 1 */ +#define MSCAN_BTR0 0x04 /* Bus Timing Register 0 */ +#define MSCAN_BTR1 0x05 /* Bus Timing Register 1 */ +#define MSCAN_RFLG 0x08 /* Receive Flag Register */ +#define MSCAN_RIER 0x09 /* Receiver Interrupt Enable Register */ +#define MSCAN_TFLG 0x0c /* Transmitter Flag Register */ +#define MSCAN_TIER 0x0d /* Transmitter Interrupt Enable Register */ +#define MSCAN_TARG 0x10 /* Transmitter Message Abort Request Register */ +#define MSCAN_TAAK 0x11 /* Transmitter Message Abort Acknowledge Register */ +#define MSCAN_TBSEL 0x14 /* Transmitter Buffer Selection */ +#define MSCAN_IDAC 0x15 /* Identifier Acceptance Control Register */ +/* Reserved 0x18, 0x19 */ +#define MSCAN_RXERR 0x1c /* Receive Error Counter Register */ +#define MSCAN_TXERR 0x1d /* Transmitt Error Counter Register */ + +/* Acceptance Filters */ +#define MSCAN_IDAR0 0x20 /* Identifier Acceptance Register 0 */ +#define MSCAN_IDAR1 0x21 /* Identifier Acceptance Register 1 */ +#define MSCAN_IDAR2 0x24 /* Identifier Acceptance Register 2 */ +#define MSCAN_IDAR3 0x25 /* Identifier Acceptance Register 3 */ +#define MSCAN_IDMR0 0x28 /* Identifier Mask Register 0 */ +#define MSCAN_IDMR1 0x29 /* Identifier Mask Register 1 */ +#define MSCAN_IDMR2 0x2c /* Identifier Mask Register 2 */ +#define MSCAN_IDMR3 0x2d /* Identifier Mask Register 3 */ + +#define MSCAN_IDAR4 0x30 /* Identifier Acceptance Register 4 */ +#define MSCAN_IDAR5 0x31 /* Identifier Acceptance Register 5 */ +#define MSCAN_IDAR6 0x34 /* Identifier Acceptance Register 6 */ +#define MSCAN_IDAR7 0x35 /* Identifier Acceptance Register 7 */ +#define MSCAN_IDMR4 0x38 /* Identifier Mask Register 4 */ +#define MSCAN_IDMR5 0x39 /* Identifier Mask Register 5 */ +#define MSCAN_IDMR6 0x3c /* Identifier Mask Register 6 */ +#define MSCAN_IDMR7 0x3d /* Identifier Mask Register 7 */ + +/* Buffers */ +#define MSCAN_RXFG 0x40 /* Foregroung Receive Buffer 0x40-0x5f */ +#define MSCAN_TXFG 0x60 /* Foregroung Receive Buffer 0x60-0x7f */ + + +/* BaudRate minimal and maximal TSEG values */ +#define MSCAN_TSEG1_MIN 4 /* means 1 Tq clock cycle */ +#define MSCAN_TSEG1_MAX 16 /* means 16 Tq clock cycles */ +#define MSCAN_TSEG2_MIN 2 /* means 1 Tq clock cycle */ +#define MSCAN_TSEG2_MAX 8 /* means 8 Tq clock cycles */ +#define MSCAN_TSEG_MIN (MSCAN_TSEG1_MIN + MSCAN_TSEG2_MIN) +#define MSCAN_TSEG_MAX (MSCAN_TSEG1_MAX + MSCAN_TSEG2_MAX) + +#define MSCAN_BRP_MIN 1 +#define MSCAN_BRP_MAX 64 + +enum mscan_ctl0 { + MSCAN_CTL0_RXFRM = 1 << 7, /* Received Frame Flag - rw */ + MSCAN_CTL0_RXACT = 1 << 6, /* Receiver Active Status - ro */ + MSCAN_CTL0_CSWAI = 1 << 5, /* CAN Stops in Wait Mode - rw */ + MSCAN_CTL0_SYNCH = 1 << 4, /* Synchronized Status - ro */ + MSCAN_CTL0_TIME = 1 << 3, /* Timer Enable - rw */ + MSCAN_CTL0_WUPE = 1 << 2, /* WakeUp Enable - rw */ + MSCAN_CTL0_SLPRQ = 1 << 1, /* Sleep Request - rw */ + MSCAN_CTL0_INITRQ = 1 << 0, /* Initialization Mode Request - rw */ +}; + +enum mscan_ctl1 { + MSCAN_CTL1_CANE = 1 << 7, /* MSCAN Enable rw */ + MSCAN_CTL1_CLKSRC = 1 << 6, /* MSCAN Clock Source rw */ + MSCAN_CTL1_LOOPB = 1 << 5, /* Loob-Back Self Test Mode rw */ + MSCAN_CTL1_LISTEN = 1 << 4, /* Listen-Only Mode rw */ + MSCAN_CTL1_WUPM = 1 << 2, /* WakeUp Mode rw */ + MSCAN_CTL1_SLPAK = 1 << 1, /* Sleep Mode Acknowledge - ro */ + MSCAN_CTL1_INITAK = 1 << 0, /* Initialization Mode Acknowledge - ro */ + + MSCAN_CTL1_RSVD = 1 << 3, /* Reserved */ +}; + +enum mscan_btr0 { + MSCAN_BTR0_SJW = 0xa0, /* Synchronization Jump Width: 0 to 3 (1 to 4 Tq) */ + MSCAN_BTR0_BRP = 0x3f, /* Baud Rate Prescaler: 0 to 63 (1 to 64) */ +}; + +enum mscan_btr1 { + MSCAN_BTR1_SAMP = 1 << 7, /* Sampling: 0-One sample, 1-Three samples per bit */ + MSCAN_BTR1_TSEG2 = 0x70, /* TSEG2: 3 bits */ + MSCAN_BTR1_TSEG1 = 0x0f, /* TSEG1: 4 bits */ +}; + +/* Interupt & Interrupt Enable Registers */ +enum mscan_rflg { + MSCAN_RFLG_WUPIF = 1 << 7, /* WakeUp Interrupt Flag - rw */ + MSCAN_RFLG_CSCIF = 1 << 6, /* CAN Status Change Interrupt Flag - rw */ + MSCAN_RFLG_RSTAT = 0x30, /* Receiver Status Bits: 0-RxOK, 1-RxWRN, 2-RxERR, 3-BusOff - ro */ + MSCAN_RFLG_TSTAT = 0x0a, /* Transmitter Status Bits: 0-TxOK, 1-TxWRN, 2-TxErr, 3-BusOff - ro */ + MSCAN_RFLG_OVRIF = 1 << 1, /* Overrun Interrupt Flag - rw */ + MSCAN_RFLG_RXF = 1 << 0, /* Receive Buffer Full - rw */ +}; + +enum mscan_rier { + MSCAN_RIER_WUPIE = 1 << 7, /* WakeUp Interrupt Enable - rw */ + MSCAN_RIER_CSCIE = 1 << 6, /* CAN Status Change Interrupt Enable - rw */ + MSCAN_RIER_RSTATE = 0x30, /* Receiver Status Change Enable: 0-Never, 1-BusOff, 2-BusOff+RxErr, 3-All - rw */ + MSCAN_RIER_TSTATE = 0x0a, /* Transmitter Status Change Enable: 0-Never, 1-BusOff, 2-BusOff+TxErr, 3-All - rw */ + MSCAN_RIER_OVRIE = 1 << 1, /* Overrun Interrupt Enable - rw */ + MSCAN_RIER_RXFIE = 1 << 0, /* Receive Buffer Full Interrupt Enable - rw */ +}; + +enum mscan_tflg { + MSCAN_TFLG_TXE = 0x07, /* Transmitter Buffer Empty */ + + MSCAN_TFLG_RSVD = 0xf8, /* Reserved */ +}; + +enum mscan_tier { + MSCAN_TIER_TXE = 0x07, /* Transmitter Empty Interrupt Enable */ + + MSCAN_TIER_RSVD = 0xf8, /* Reserved */ +}; +/* IRQ end */ + +enum mscan_tarq { + MSCAN_TARQ_ABTRQ = 0x07, /* Abort Request */ + + MSCAN_TARQ_RSVD = 0xf8, /* Reserved */ +}; + +enum mscan_taak { + MSCAN_TAAK_ABTAK = 0x07, /* Abort Acknowledge */ + + MSCAN_TAAK_RSVD = 0xf8, /* Reserved */ +}; + +enum mscan_tbsel { + MSCAN_TBSEL_TX = 0x07, /* Transmitt Buffer Select - prioritize lower */ + + MSCAN_TBSEL_RSVD = 0xf8, /* Reserved */ +}; + +enum mscan_idac { + MSCAN_IDAC_IDAM = 0x30, /* Identifier Acceptance Mode: 0-Two 32bit, 1-Four 16-bit. 2-Eight 8bit, 3-Closed */ + MSCAN_IDAC_IDHIT = 0x07, /* Identifier Acceptance Hit Indicator */ + + MSCAN_IDAC_RSVD = 0xa8, /* Reserved */ +}; + +/* Message Buffer Organization */ +#define MSCAN_MSGBUFF_ID0 0x00 /* Identifier Register 0 */ +#define MSCAN_MSGBUFF_ID1 0x01 /* Identifier Register 1 */ +#define MSCAN_MSGBUFF_ID2 0x04 /* Identifier Register 2 */ +#define MSCAN_MSGBUFF_ID3 0x05 /* Identifier Register 3 */ + +#define MSCAN_MSGBUFF_DATA0 0x08 /* Data Segment Register 0 */ +#define MSCAN_MSGBUFF_DATA1 0x09 /* Data Segment Register 1 */ +#define MSCAN_MSGBUFF_DATA2 0x0c /* Data Segment Register 2 */ +#define MSCAN_MSGBUFF_DATA3 0x0d /* Data Segment Register 3 */ +#define MSCAN_MSGBUFF_DATA4 0x10 /* Data Segment Register 4 */ +#define MSCAN_MSGBUFF_DATA5 0x11 /* Data Segment Register 5 */ +#define MSCAN_MSGBUFF_DATA6 0x14 /* Data Segment Register 6 */ +#define MSCAN_MSGBUFF_DATA7 0x15 /* Data Segment Register 7 */ + +#define MSCAN_MSGBUFF_DLEN 0x18 /* Data Length Register */ +#define MSCAN_MSGBUFF_TXPRIO 0x19 /* Transmitt Buffer Priority - Not Applicable for Rx buffers */ +#define MSCAN_MSGBUFF_TSH 0x1c /* Time Stamp Register High */ +#define MSCAN_MSGBUFF_TSL 0x1d /* Time Stamp Register Low */ + +struct mscan_msg_buffer{ + + uint8_t id_0; /* CAN identifier: ID_EXT {28:21} OR ID_STD {10:3} */ + uint8_t id_1; /* CAN identifier: ID_EXT {20:18},SRR,IDE,ID_EXT{17:15} OR ID_STD{2:0},RTR,IDE, reserved */ + uint16_t spacer_0; /* spacer for compatibility */ + uint8_t id_2; /* CAN identifier: IDE_EXT{14:7} OR reserved for ID_STD */ + uint8_t id_3; /* CAN identifier: ID_EXT{6:0},RTR OR reserved for ID_STD */ + uint16_t spacer_1; /* spacer for compatibility */ + uint8_t data_0; /* CAN data byte 0 */ + uint8_t data_1; /* CAN data byte 1 */ + uint16_t spacer_2; /* spacer for compatibility */ + uint8_t data_2; /* CAN data byte 2 */ + uint8_t data_3; /* CAN data byte 3 */ + uint16_t spacer_3; /* spacer for compatibility */ + uint8_t data_4; /* CAN data byte 4 */ + uint8_t data_5; /* CAN data byte 5 */ + uint16_t spacer_4; /* spacer for compatibility */ + uint8_t data_6; /* CAN data byte 6 */ + uint8_t data_7; /* CAN data byte 7 */ + uint16_t spacer_5; /* spacer for compatibility */ + uint8_t data_len; /* CAN data length: 0xf0 reserved, DLC{3:0} */ + uint8_t local_prio; /* MSCAN TX local priority - unused fro TX buffer */ + uint16_t spacer_6; /* spacer for compatibility */ + uint8_t timestamp_h; /* local timestamp - High byte - Read Only */ + uint8_t timestamp_l; /* local timestamp - Low byte - Read Only */ +};