X-Git-Url: http://rtime.felk.cvut.cz/gitweb/lincan.git/blobdiff_plain/4dc78b4651f006bf0404c8ec7db85651bcee7c2e..04ac67cc3cac14cd601daacd0592121ec0b84012:/lincan/src/mscan.c diff --git a/lincan/src/mscan.c b/lincan/src/mscan.c index 74c086a..5b65df9 100644 --- a/lincan/src/mscan.c +++ b/lincan/src/mscan.c @@ -83,31 +83,31 @@ static int mscan_abort_msg(struct canchip_t * chip, reg_t buffer_mask); mscan_get_flags(chip, 0xff, MSCAN_CTL1), mscan_get_flags(chip, 0xff, MSCAN_BTR0), mscan_get_flags(chip, 0xff, MSCAN_BTR1)); - + CANMSG("RFLG 0x%02x\tRIER 0x%02x\tTFLG 0x%02x\tTIER 0x%02x\n", mscan_get_flags(chip, 0xff, MSCAN_RFLG), mscan_get_flags(chip, 0xff, MSCAN_RIER), mscan_get_flags(chip, 0xff, MSCAN_TFLG), mscan_get_flags(chip, 0xff, MSCAN_TIER)); - + CANMSG("TARQ 0x%02x\tTAAK 0x%02x\tTBSEL 0x%02x\tIDAC 0x%02x\n", mscan_get_flags(chip, 0xff, MSCAN_TARQ), mscan_get_flags(chip, 0xff, MSCAN_TAAK), mscan_get_flags(chip, 0xff, MSCAN_TBSEL), mscan_get_flags(chip, 0xff, MSCAN_IDAC)); - + CANMSG("RXERR 0x%02x\tTXERR 0x%02x\n", mscan_get_flags(chip, 0xff, MSCAN_RXERR), mscan_get_flags(chip, 0xff, MSCAN_TXERR)); - + } - + static void dump_buff(struct canchip_t * chip, unsigned offset_addr) { volatile struct mscan_msg_buffer * buff = (struct mscan_msg_buffer *)(chip->chip_base_addr + offset_addr); - + CANMSG("MSCAN buffer dump\n"); - + /* structural access */ CANMSG("Data0 0x%02x Data1 0x%02x Data2 0x%02x Data3 0x%02x Data4 0x%02x Data5 0x%02x Data6 0x%02x Data7 0x%02x\n", buff->data_0, buff->data_1, buff->data_2, buff->data_3, buff->data_4, buff->data_5, buff->data_6, buff->data_7); @@ -115,7 +115,7 @@ static int mscan_abort_msg(struct canchip_t * chip, reg_t buffer_mask); buff->data_len, buff->local_prio); CANMSG("IDR0 0x%02x\tIDR1 0x%02x\tIDR2 0x%02x\tIDR3 0x%02x\n", buff->id_0, buff->id_1, buff->id_2, buff->id_3); - + } static void dump_filter(struct canchip_t * chip) @@ -140,7 +140,7 @@ static int mscan_abort_msg(struct canchip_t * chip, reg_t buffer_mask); /* macro for standardized CAN Bus Status change report */ -#define MSCAN_STAT_CHANGE(msg,idx) CANMSG("MSCAN chip %d %s\n", idx, msg) +#define MSCAN_STAT_CHANGE(msg,idx) CANMSG("MSCAN chip %d %s\n", idx, msg) /* Enable folowing IRQs * MSCAN_TIER_TXE - Transmit Empty Interrupt - Set and Cleared during TX proccess not during init @@ -150,7 +150,7 @@ static int mscan_abort_msg(struct canchip_t * chip, reg_t buffer_mask); * MSCAN_RIER_OVRIE - Overrun * MSCAN_RIER_CSCIE - CAN Status Change */ -uint16_t mscan_IRQs = MSCAN_RIER_RXFIE | +uint16_t mscan_IRQs = MSCAN_RIER_RXFIE | MSCAN_RIER_RSTATE | MSCAN_RIER_TSTATE | MSCAN_RIER_OVRIE | MSCAN_RIER_CSCIE; /* TX interrupt flag is held shifted */ /* 1 - enable interrupt, 0 - interrupt is masked */ @@ -174,7 +174,7 @@ int mscan_chip_config(struct canchip_t *chip) int err; DEBUGMSG("Configuring chip...\n"); - + if ((err = mscan_enable_configuration(chip))) return err; @@ -212,7 +212,7 @@ int mscan_enable_configuration(struct canchip_t *chip) /* Sleep mode - disable CAN activity after completing current operation */ /* if controler not synced to bus, skip sleep mode */ - if (!mscan_sleep_mode_active(chip) && + if (!mscan_sleep_mode_active(chip) && mscan_get_flags(chip, MSCAN_CTL0_SYNCH, MSCAN_CTL0)) if (mscan_enter_sleep_mode(chip)) { @@ -220,7 +220,7 @@ int mscan_enable_configuration(struct canchip_t *chip) DUMPREGS(chip); DEBUGMSG("Forcig INIT\n"); } - + /* now we can enter Init mode */ if(mscan_enter_init_mode(chip)) @@ -377,7 +377,7 @@ int mscan_baud_rate(struct canchip_t *chip, int bitrate, int clock, int sjw, int btr0 = (best_brp & MSCAN_BTR0_BRP) | ((sjw << 6) & MSCAN_BTR0_SJW); btr1 = (tseg1 & MSCAN_BTR1_TSEG1) | ((tseg2 << 4) & MSCAN_BTR1_TSEG2); - mscan_set_btregs(chip, btr0, btr1); + mscan_set_btregs(chip, btr0, btr1); mscan_disable_configuration(chip); @@ -389,17 +389,17 @@ int mscan_set_btregs(struct canchip_t *chip, unsigned short bcr0, unsigned short { /* DEBUGMSG("Seting BCR0 and BCR1.\n"); */ reg_t btr0, btr1; - + btr0 = (reg_t)bcr0; btr1 = (reg_t)bcr1; btr1 &= ~MSCAN_BTR1_SAMP; /* use one-point sample, not three smaples per bit */ DEBUGMSG("BTR0 0x%02x BTR1 0x%02x\n", btr0, btr1); - + can_write_reg(chip, btr0, MSCAN_BTR0); can_write_reg(chip, btr1, MSCAN_BTR1); - + /* DEBUGMSG("BCR0 and BCR1 successfully set.\n"); */ return 0; } @@ -447,11 +447,11 @@ int mscan_attach_to_chip(struct canchip_t *chip) /* Transmitt Abort Request Register (TARQ) is clean after INIT mode - no need to clear it explicitly */ /* Control Register 0 (CTL0) is clean after INIT too (excepts fro WUPE, SLRQ and INITRQ) */ - - /* initialize chip by entering Sleep & Init mode */ + + /* initialize chip by entering Sleep & Init mode */ if (mscan_enable_configuration(chip)) return -ENODEV; - + /* reset Control Register 1 (CTL1) */ ctl1 = MSCAN_CTL1_CANE | (MPC5200_CLKSRC ? MSCAN_CTL1_CLKSRC : 0x00) ; @@ -460,7 +460,7 @@ int mscan_attach_to_chip(struct canchip_t *chip) /* MSCAN_CTL1_WUPM | WakeUp mode not used */ /* MSCAN_CTL1_SLPAK | ReadOnly */ /* MSCAN_CTL1_INITAK | ReadOnly */ - + can_write_reg(chip, ctl1, MSCAN_CTL1); @@ -490,7 +490,7 @@ int mscan_release_chip(struct canchip_t *chip) { /* IRQ unmapped in lincan driver core */ can_disable_irq(chip->chip_irq); - + mscan_clear_objects(chip); /* Cannot be called in INIT mode */ @@ -498,7 +498,7 @@ int mscan_release_chip(struct canchip_t *chip) /* disable chip */ mscan_clear_flags(chip, MSCAN_CTL1_CANE, MSCAN_CTL1); - + DEBUGMSG("Chip released [%02d]\n", chip->chip_idx); return 0; } @@ -514,7 +514,7 @@ int mscan_standard_mask(struct canchip_t *chip, unsigned short code, unsigned sh reg_t idr0, idr1, mr0, mr1; /* ID register 0,1, Mask register 0, 1 */ - if (code & 0x1ffff800) + if (code & 0x1ffff800) return mscan_extended_mask(chip, code, mask); @@ -553,7 +553,7 @@ int mscan_extended_mask(struct canchip_t *chip, unsigned long code, unsigned lon { /* code - contains 11bit ID and as LSB the RTR flag */ /* code - contains 11bit mask and RTR mask as LSB */ - + reg_t idr0, idr1, idr2, idr3; /* ID registers 0,1,2,3 */ reg_t mr0, mr1, mr2, mr3; /* Mask registers 0,1,2,3 */ @@ -561,9 +561,9 @@ int mscan_extended_mask(struct canchip_t *chip, unsigned long code, unsigned lon /* we use two 32-bit acceptance filters */ mscan_clear_flags(chip, MSCAN_IDAC_IDAM, MSCAN_IDAC); - + idr0 = (reg_t)((code & 0x7fa00000) >> 22); /* EXT_ID {29:21} */ - + idr1 = (reg_t)((code & 0x00380000) >> 14); /* EXT_ID {20:18} */ idr1|= 0x18; /* SRR and IDE */ idr1|= (reg_t)((code & 0x00070000) >> 16); /* EXT_ID {17:15} */ @@ -573,7 +573,7 @@ int mscan_extended_mask(struct canchip_t *chip, unsigned long code, unsigned lon mr0 = (reg_t)((mask & 0x7fa00000) >> 22); /* EXT_ID {29:21} */ - + mr1 = (reg_t)((mask & 0x00380000) >> 14); /* EXT_ID {20:18} */ /* SRR=0 and IDE=0 - do not ignore */ mr1|= (reg_t)((mask & 0x00070000) >> 16); /* EXT_ID {17:15} */ @@ -606,7 +606,7 @@ int mscan_extended_mask(struct canchip_t *chip, unsigned long code, unsigned lon DEBUGMSG("Set extended_mask [id:0x%08x RTR=%lu, m:0x%08x RTR=%lu]\n", (uint32_t)(code >> 1), code & 0x00000001, (uint32_t)(mask >> 1), mask & 0x00000001); DUMPFLT(chip); - + return 0; } @@ -619,7 +619,7 @@ int mscan_pre_read_config(struct canchip_t *chip, struct msgobj_t *obj) DEBUGRX("Pre read config\n"); /* MSCAN has only one buffer, which is already initialized */ - + return 0; } @@ -632,7 +632,7 @@ int mscan_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj, struct can_spin_lock(&mscan_prewr_lock); can_preempt_disable(); DEBUGTX("Pre write config\n"); - + /* find free buffer */ txf = mscan_get_flags(chip, MSCAN_TFLG_TXE, MSCAN_TFLG); for (buff_no = 0; buff_no < 3 && !(txf & (0x01 << buff_no)); buff_no++) { } @@ -671,13 +671,13 @@ pwrite_exit_fail: int mscan_send_msg(struct canchip_t *chip, struct msgobj_t *obj, struct canmsg_t *msg) { DEBUGTX("Send Message\n"); - + /* turn on IRQ for this buffer */ can_write_reg(chip, msg->cob, MSCAN_TIER); /* clear TX Buffer Empty flag (by writing '1') to initiate trasmition */ can_write_reg(chip, msg->cob, MSCAN_TFLG); - + return 0; } @@ -710,11 +710,11 @@ int mscan_irq_handler(int irq, struct canchip_t *chip) tx_irq = (MSCAN_TFLG_TXE << 8); /* to spare few tacts in IRQ loop */ irq_reg = mscan_get_irq_flags(chip); - DEBUGMSG("IRQ Handler chip %d (%d)\n", chip->chip_idx, irq); + DEBUGMSG("IRQ Handler chip %d (%d)\n", chip->chip_idx, irq); do { - if(!loop_cnt--) + if(!loop_cnt--) goto irqhnd_exit_stuck; DEBUGMSG("IRR: 0x%04x\n", irq_reg); @@ -731,7 +731,7 @@ int mscan_irq_handler(int irq, struct canchip_t *chip) mscan_set_flags(chip, MSCAN_RFLG_RXF, MSCAN_RFLG); } - + /* Can Status change - due to RX/TX error counters */ if(irq_reg & MSCAN_RFLG_CSCIF) { @@ -757,7 +757,7 @@ int mscan_irq_handler(int irq, struct canchip_t *chip) MSCAN_STAT_CHANGE("RX: ERROR PASSIVE", chip->chip_idx); /* Show warning only */ break; - + case 1: /* bus - warning */ MSCAN_STAT_CHANGE("RX: Bus Warning", chip->chip_idx); /* Show warning only */ @@ -770,7 +770,7 @@ int mscan_irq_handler(int irq, struct canchip_t *chip) } rxstat = irq_rstat; /* update static RX status field */ } - + /* Transmit bus off/error/warning */ if (irq_tstat ^ txstat) { @@ -788,7 +788,7 @@ int mscan_irq_handler(int irq, struct canchip_t *chip) MSCAN_STAT_CHANGE("TX: ERROR PASSIVE", chip->chip_idx); /* Show warning only */ break; - + case 1: /* bus - warning */ MSCAN_STAT_CHANGE("TX: Bus Warning", chip->chip_idx); /* Show warning only */ @@ -808,9 +808,9 @@ int mscan_irq_handler(int irq, struct canchip_t *chip) /* Message Overrun/Overwritten */ if (irq_reg & MSCAN_RFLG_OVRIF) - { + { CANMSG("Error: MESSAGE OVERRUN/OVERWRITTEN"); - + /* notify only injured RXqueue-end */ mscan_notifyRXends(chip->msgobj[0], CANQUEUE_NOTIFY_ERROR); @@ -829,7 +829,7 @@ int mscan_irq_handler(int irq, struct canchip_t *chip) can_spin_unlock(&mscan_prewr_lock); - /* sends message */ + /* sends message */ mscan_wakeup_tx(chip, chip->msgobj[0]); } @@ -837,7 +837,7 @@ int mscan_irq_handler(int irq, struct canchip_t *chip) /* omit RSTAT and TSTAT - they're used only in CSCIF handler */ } while(irq_reg & - mscan_IRQs & + mscan_IRQs & ~(MSCAN_RFLG_RSTAT | MSCAN_RFLG_TSTAT)); @@ -892,10 +892,10 @@ int mscan_clear_objects(struct canchip_t *chip) /* clear TX buffers, need to set CANTBSEL register */ can_write_reg(chip, 0x01, MSCAN_TBSEL); mscan_clear_buffer(chip, MSCAN_TXFG); - + can_write_reg(chip, 0x02, MSCAN_TBSEL); mscan_clear_buffer(chip, MSCAN_TXFG); - + can_write_reg(chip, 0x04, MSCAN_TBSEL); mscan_clear_buffer(chip, MSCAN_TXFG); @@ -924,7 +924,7 @@ int mscan_wakeup_tx(struct canchip_t *chip, struct msgobj_t *obj) { can_preempt_disable(); DEBUGMSG("WakeUP TX\n"); - + can_msgobj_set_fl(obj, TX_REQUEST); while(!can_msgobj_test_and_set_fl(obj, TX_LOCK)) { can_msgobj_clear_fl(obj, TX_REQUEST); @@ -968,11 +968,11 @@ int mscan_filtch_rq(struct canchip_t *chip, struct msgobj_t * obj) /* MSCAN uses oposite logic (compared to IP) for LAFM: 1-ignore bit, 0-use bit as mask */ mask = (~filter.mask) << 1; - + /* RTR is LSB of mask */ if (filter.flags & MSG_RTR) mask |= 0x00000001; - + if (filter.flags & MSG_EXT) /* Extended ID */ return mscan_extended_mask(chip, filter.id, mask); else /* Standard ID */ @@ -994,7 +994,7 @@ void mscan_irq_read_handler(struct canchip_t *chip, struct msgobj_t *obj) } mscan_msg_from_rxbuffer(chip, &(obj->rx_msg)); - + /* fill CAN message timestamp */ can_filltimestamp(&obj->rx_msg.timestamp); @@ -1085,7 +1085,7 @@ int mscan_fill_chipspecops(struct canchip_t *chip) chip->max_objects = 1; chip->write_register = chip->hostdevice->hwspecops->write_register; chip->read_register = chip->hostdevice->hwspecops->read_register; - + /* chip->flags; chip->baudrate; @@ -1292,7 +1292,7 @@ static int mscan_update_samplept(int sampl_pt, int tseg, int *tseg1, int *tseg2) * difference between tseg and tsegall is: * tsegall = tseg + 1 */ - + *tseg2 = tseg + 1 - (sampl_pt * (tseg + 1)) / 1000; if (*tseg2 < MSCAN_TSEG2_MIN) *tseg2 = MSCAN_TSEG2_MIN; @@ -1386,7 +1386,7 @@ static void mscan_clear_flags(struct canchip_t * chip, reg_t flags, unsigned reg static uint16_t mscan_get_irq_flags(struct canchip_t * chip) { /* Transmit Buffer Empty only if enabled */ - return ((mscan_get_flags(chip, MSCAN_TIER_TXE, MSCAN_TIER) & + return ((mscan_get_flags(chip, MSCAN_TIER_TXE, MSCAN_TIER) & mscan_get_flags(chip, MSCAN_TFLG_TXE, MSCAN_TFLG)) << 8) | (mscan_get_flags(chip, (reg_t)(mscan_IRQs & 0xff), MSCAN_RFLG)); } @@ -1417,7 +1417,7 @@ static int mscan_abort_msg(struct canchip_t * chip, reg_t buffer_mask) goto abortmsg_exit_ok; } - + /* set TARQ - Transmitt Abort Request */ mscan_set_flags(chip, m, MSCAN_TARQ);