X-Git-Url: http://rtime.felk.cvut.cz/gitweb/lincan.git/blobdiff_plain/4cf24de229090b1ab6279570a564d224e13dd706..HEAD:/lincan/src/nsi.c diff --git a/lincan/src/nsi.c b/lincan/src/nsi.c index 3fefebc..aac7eff 100644 --- a/lincan/src/nsi.c +++ b/lincan/src/nsi.c @@ -1,25 +1,39 @@ -/* nsi.c - * Linux CAN-bus device driver. - * Written by Arnaud Westenberg email:arnaud@wanadoo.nl - * This software is released under the GPL-License. - * Version 0.7 6 Aug 2001 - */ - -#include -#if defined (CONFIG_MODVERSIONS) && !defined (MODVERSIONS) -#define MODVERSIONS -#endif - -#if defined (MODVERSIONS) -#include -#endif - -#include -#include -#include -#include -#include - +/**************************************************************************/ +/* File: nsi.c - CAN104 PC/104 card by NSI */ +/* */ +/* LinCAN - (Not only) Linux CAN bus driver */ +/* Copyright (C) 2002-2009 DCE FEE CTU Prague */ +/* Copyright (C) 2002-2009 Pavel Pisa */ +/* Funded by OCERA and FRESCOR IST projects */ +/* Based on CAN driver code by Arnaud Westenberg */ +/* */ +/* LinCAN is free software; you can redistribute it and/or modify it */ +/* under terms of the GNU General Public License as published by the */ +/* Free Software Foundation; either version 2, or (at your option) any */ +/* later version. LinCAN is distributed in the hope that it will be */ +/* useful, but WITHOUT ANY WARRANTY; without even the implied warranty */ +/* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU */ +/* General Public License for more details. You should have received a */ +/* copy of the GNU General Public License along with LinCAN; see file */ +/* COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, */ +/* Cambridge, MA 02139, USA. */ +/* */ +/* To allow use of LinCAN in the compact embedded systems firmware */ +/* and RT-executives (RTEMS for example), main authors agree with next */ +/* special exception: */ +/* */ +/* Including LinCAN header files in a file, instantiating LinCAN generics */ +/* or templates, or linking other files with LinCAN objects to produce */ +/* an application image/executable, does not by itself cause the */ +/* resulting application image/executable to be covered by */ +/* the GNU General Public License. */ +/* This exception does not however invalidate any other reasons */ +/* why the executable file might be covered by the GNU Public License. */ +/* Publication of enhanced or derived LinCAN files is required although. */ +/**************************************************************************/ + +#include "../include/can.h" +#include "../include/can_sysdep.h" #include "../include/main.h" #include "../include/nsi.h" #include "../include/i82527.h" @@ -27,6 +41,8 @@ int nsican_irq=-1; unsigned long nsican_base=0x0; +static CAN_DEFINE_SPINLOCK(nsican_port_lock); + /* IO_RANGE is the io-memory range that gets reserved, please adjust according * your hardware. Example: #define IO_RANGE 0x100 for i82527 chips or * #define IO_RANGE 0x20 for sja1000 chips. @@ -36,30 +52,28 @@ unsigned long nsican_base=0x0; /* The function template_request_io is used to reserve the io-memory. If your * hardware uses a dedicated memory range as hardware control registers you * will have to add the code to reserve this memory as well. - * The reserved memory starts at io_addr, wich is the module parameter io. + * The reserved memory starts at candev->io_addr, wich is the module parameter io. */ -int nsi_request_io(unsigned long io_addr) +int nsi_request_io(struct candevice_t *candev) { - if (check_region(io_addr,IO_RANGE)) { - CANMSG("Unable to open port: 0x%lx\n",io_addr); + if (!can_request_io_region(candev->io_addr,IO_RANGE,DEVICE_NAME)) { + CANMSG("Unable to open port: 0x%lx\n",candev->io_addr); return -ENODEV; - } - else { - request_region(io_addr,IO_RANGE,DEVICE_NAME); - DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", io_addr, - io_addr + IO_RANGE - 1); + } else { + DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", candev->io_addr, + candev->io_addr + IO_RANGE - 1); } return 0; } -/* The function template_release_io is used to free the previously reserved +/* The function template_release_io is used to free the previously reserved * io-memory. In case you reserved more memory, don't forget to free it here. */ -int nsi_release_io(unsigned long io_addr) +int nsi_release_io(struct candevice_t *candev) { - release_region(io_addr,IO_RANGE); + can_release_io_region(candev->io_addr,IO_RANGE); return 0; } @@ -68,23 +82,23 @@ int nsi_release_io(unsigned long io_addr) * hardware specific so I haven't included example code. Don't forget to check * the reset status of the chip before returning. */ -int nsi_reset(int card) +int nsi_reset(struct candevice_t *candev) { - int i; + int i; DEBUGMSG("Resetting nsi hardware ...\n"); /* we don't use template_write_register because we don't use the two first register of the card but the third in order to make a hard reset */ - outb (1, nsican_base + candevices_p[card]->res_addr); - outb (0, nsican_base + candevices_p[card]->res_addr); + can_outb (1, nsican_base + candev->res_addr); + can_outb (0, nsican_base + candev->res_addr); for (i = 1; i < 1000; i++) udelay (1000); - - - /* Check hardware reset status */ + + + /* Check hardware reset status */ i=0; while ( (nsi_read_register(nsican_base+iCPU) & iCPU_RST) && (i<=15)) { - udelay(20000); + mdelay(20); i++; } if (i>=15) { @@ -103,19 +117,20 @@ int nsi_reset(int card) * RESET_ADDR represents the io-address of the hardware reset register. * NR_82527 represents the number of intel 82527 chips on the board. * NR_SJA1000 represents the number of philips sja1000 chips on the board. - * The flags entry can currently only be PROGRAMMABLE_IRQ to indicate that + * The flags entry can currently only be CANDEV_PROGRAMMABLE_IRQ to indicate that * the hardware uses programmable interrupts. */ #define RESET_ADDR 0x02 #define NR_82527 1 #define NR_SJA1000 0 -int nsi_init_hw_data(int card) +int nsi_init_hw_data(struct candevice_t *candev) { - candevices_p[card]->res_addr=RESET_ADDR; - candevices_p[card]->nr_82527_chips=1; - candevices_p[card]->nr_sja1000_chips=0; - candevices_p[card]->flags |= PROGRAMMABLE_IRQ; + candev->res_addr=RESET_ADDR; + candev->nr_82527_chips=1; + candev->nr_sja1000_chips=0; + candev->nr_all_chips=1; + candev->flags |= CANDEV_PROGRAMMABLE_IRQ; return 0; } @@ -125,23 +140,22 @@ int nsi_init_hw_data(int card) * CHIP_TYPE represents the type of CAN chip. CHIP_TYPE can be "i82527" or * "sja1000". * The chip_base_addr entry represents the start of the 'official' memory map - * of the installed chip. It's likely that this is the same as the io_addr + * of the installed chip. It's likely that this is the same as the candev->io_addr * argument supplied at module loading time. * The clock argument holds the chip clock value in Hz. */ -#define CHIP_TYPE "i82527" -int nsi_init_chip_data(int card, int chipnr) +int nsi_init_chip_data(struct candevice_t *candev, int chipnr) { - candevices_p[card]->chip[chipnr]->chip_type=CHIP_TYPE; - candevices_p[card]->chip[chipnr]->chip_base_addr= - candevices_p[card]->io_addr; - candevices_p[card]->chip[chipnr]->clock = 16000000; - nsican_irq=candevices_p[card]->chip[chipnr]->chip_irq; - nsican_base=candevices_p[card]->chip[chipnr]->chip_base_addr; - candevices_p[card]->chip[chipnr]->int_cpu_reg = iCPU_DSC; - candevices_p[card]->chip[chipnr]->int_clk_reg = iCLK_SL1; - candevices_p[card]->chip[chipnr]->int_bus_reg = iBUS_CBY; + i82527_fill_chipspecops(candev->chip[chipnr]); + candev->chip[chipnr]->chip_base_addr= + can_ioport2ioptr(candev->io_addr); + candev->chip[chipnr]->clock = 16000000; + nsican_irq=candev->chip[chipnr]->chip_irq; + nsican_base=candev->chip[chipnr]->chip_base_addr; + candev->chip[chipnr]->int_cpu_reg = iCPU_DSC; + candev->chip[chipnr]->int_clk_reg = iCLK_SL1; + candev->chip[chipnr]->int_bus_reg = iBUS_CBY; return 0; } @@ -151,28 +165,27 @@ int nsi_init_chip_data(int card, int chipnr) * CAN chip. In case of the sja1000 there's only one message object but on the * i82527 chip there are 15. * The code below is for a i82527 chip and initializes the object base addresses - * The entry obj_base_addr represents the first memory address of the message + * The entry obj_base_addr represents the first memory address of the message * object. In case of the sja1000 obj_base_addr is taken the same as the chips * base address. * Unless the hardware uses a segmented memory map, flags can be set zero. */ -int nsi_init_obj_data(int chipnr, int objnr) +int nsi_init_obj_data(struct canchip_t *chip, int objnr) { - chips_p[chipnr]->msgobj[objnr]->obj_base_addr= - chips_p[chipnr]->chip_base_addr+(objnr+1)*0x10; - chips_p[chipnr]->msgobj[objnr]->flags=0; - + chip->msgobj[objnr]->obj_base_addr= + chip->chip_base_addr+(objnr+1)*0x10; + return 0; } /* The function template_program_irq is used for hardware that uses programmable * interrupts. If your hardware doesn't use programmable interrupts you should - * not set the candevices_t->flags entry to PROGRAMMABLE_IRQ and leave this + * not set the candevices_t->flags entry to CANDEV_PROGRAMMABLE_IRQ and leave this * function unedited. Again this function is hardware specific so there's no * example code. */ -int nsi_program_irq(int card) +int nsi_program_irq(struct candevice_t *candev) { return 0; } @@ -181,35 +194,36 @@ int nsi_program_irq(int card) * on the CAN chip. You should only have to edit this function if your hardware * uses some specific write process. */ -void nsi_write_register(unsigned char data, unsigned long address) +void nsi_write_register(unsigned data, can_ioptr_t address) { /* address is an absolute address */ /* the nsi card has two registers, the address register at 0x0 and the data register at 0x01 */ - /* write the relative address on the eight LSB bits + /* write the relative address on the eight LSB bits and the data on the eight MSB bits in one time */ - outw(address-nsican_base + (256 * data), nsican_base); + can_outw(address-nsican_base + (256 * data), nsican_base); } /* The function template_read_register is used to read from hardware registers * on the CAN chip. You should only have to edit this function if your hardware * uses some specific read process. */ -unsigned nsi_read_register(unsigned long address) +unsigned nsi_read_register(can_ioptr_t address) { /* this is the same thing that the function write_register. - We use the two register, we write the address where we + We use the two register, we write the address where we want to read in a first time. In a second time we read the data */ - unsigned char ret; - - disable_irq(nsican_irq); - outb(address-nsican_base, nsican_base); - ret=inb(nsican_base+1); - enable_irq(nsican_irq); - return ret; + unsigned char ret; + can_spin_irqflags_t flags; + + can_spin_lock_irqsave(&nsican_port_lock,flags); + can_outb(address-nsican_base, nsican_base); + ret=can_inb(nsican_base+1); + can_spin_unlock_irqrestore(&nsican_port_lock,flags); + return ret; }