X-Git-Url: http://rtime.felk.cvut.cz/gitweb/lincan.git/blobdiff_plain/3a2bb63f0bb8de2aafb346b53b945c59b3f87a41..9c8ab08d7e8fca3916a7f91a3c001d151989137c:/lincan/src/i82527.c diff --git a/lincan/src/i82527.c b/lincan/src/i82527.c index 682374a..caed3d9 100644 --- a/lincan/src/i82527.c +++ b/lincan/src/i82527.c @@ -1,18 +1,43 @@ -/* i82527.c - * Linux CAN-bus device driver. - * Written by Arnaud Westenberg email:arnaud@wanadoo.nl - * Rewritten for new CAN queues by Pavel Pisa - OCERA team member - * email:pisa@cmp.felk.cvut.cz - * This software is released under the GPL-License. - * Version lincan-0.3 17 Jun 2004 - */ +/**************************************************************************/ +/* File: i82527.c - Intel i82527 CAN controller support */ +/* */ +/* LinCAN - (Not only) Linux CAN bus driver */ +/* Copyright (C) 2002-2009 DCE FEE CTU Prague */ +/* Copyright (C) 2002-2009 Pavel Pisa */ +/* Funded by OCERA and FRESCOR IST projects */ +/* Based on CAN driver code by Arnaud Westenberg */ +/* */ +/* LinCAN is free software; you can redistribute it and/or modify it */ +/* under terms of the GNU General Public License as published by the */ +/* Free Software Foundation; either version 2, or (at your option) any */ +/* later version. LinCAN is distributed in the hope that it will be */ +/* useful, but WITHOUT ANY WARRANTY; without even the implied warranty */ +/* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU */ +/* General Public License for more details. You should have received a */ +/* copy of the GNU General Public License along with LinCAN; see file */ +/* COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, */ +/* Cambridge, MA 02139, USA. */ +/* */ +/* To allow use of LinCAN in the compact embedded systems firmware */ +/* and RT-executives (RTEMS for example), main authors agree with next */ +/* special exception: */ +/* */ +/* Including LinCAN header files in a file, instantiating LinCAN generics */ +/* or templates, or linking other files with LinCAN objects to produce */ +/* an application image/executable, does not by itself cause the */ +/* resulting application image/executable to be covered by */ +/* the GNU General Public License. */ +/* This exception does not however invalidate any other reasons */ +/* why the executable file might be covered by the GNU Public License. */ +/* Publication of enhanced or derived LinCAN files is required although. */ +/**************************************************************************/ #include "../include/can.h" #include "../include/can_sysdep.h" #include "../include/main.h" #include "../include/i82527.h" -void i82527_irq_rtr_handler(struct chip_t *chip, struct msgobj_t *obj, +void i82527_irq_rtr_handler(struct canchip_t *chip, struct msgobj_t *obj, struct rtr_id *rtr_search, unsigned long message_id); @@ -23,7 +48,7 @@ extern int mo15mask; /* helper functions for segmented cards read and write configuration and status registers above 0xf offset */ -void i82527_seg_write_reg(const struct chip_t *chip, unsigned char data, unsigned address) +void i82527_seg_write_reg(const struct canchip_t *chip, unsigned char data, unsigned address) { if((address > 0xf) && (chip->flags & CHIP_SEGMENTED)) canobj_write_reg(chip, chip->msgobj[(address>>4)-1],data, address & 0xf); @@ -31,7 +56,7 @@ void i82527_seg_write_reg(const struct chip_t *chip, unsigned char data, unsigne can_write_reg(chip, data, address); } -unsigned i82527_seg_read_reg(const struct chip_t *chip, unsigned address) +unsigned i82527_seg_read_reg(const struct canchip_t *chip, unsigned address) { if((address > 0xf) && (chip->flags & CHIP_SEGMENTED)) return canobj_read_reg(chip, chip->msgobj[(address>>4)-1], address & 0xf); @@ -39,7 +64,7 @@ unsigned i82527_seg_read_reg(const struct chip_t *chip, unsigned address) return can_read_reg(chip, address); } -int i82527_enable_configuration(struct chip_t *chip) +int i82527_enable_configuration(struct canchip_t *chip) { unsigned short flags=0; @@ -49,7 +74,7 @@ int i82527_enable_configuration(struct chip_t *chip) return 0; } -int i82527_disable_configuration(struct chip_t *chip) +int i82527_disable_configuration(struct canchip_t *chip) { unsigned short flags=0; @@ -59,7 +84,7 @@ int i82527_disable_configuration(struct chip_t *chip) return 0; } -int i82527_chip_config(struct chip_t *chip) +int i82527_chip_config(struct canchip_t *chip) { can_write_reg(chip,chip->int_cpu_reg,iCPU); // Configure cpu interface can_write_reg(chip,(iCTL_CCE|iCTL_INI),iCTL); // Enable configuration @@ -121,7 +146,7 @@ int i82527_chip_config(struct chip_t *chip) * param sampl_pt sample point in % (0-100) sets (TSEG1+2)/(TSEG1+TSEG2+3) ratio * param flags fields BTR1_SAM, OCMODE, OCPOL, OCTP, OCTN, CLK_OFF, CBP */ -int i82527_baud_rate(struct chip_t *chip, int rate, int clock, int sjw, +int i82527_baud_rate(struct canchip_t *chip, int rate, int clock, int sjw, int sampl_pt, int flags) { int best_error = 1000000000, error; @@ -131,7 +156,8 @@ int i82527_baud_rate(struct chip_t *chip, int rate, int clock, int sjw, if (i82527_enable_configuration(chip)) return -ENODEV; - clock /=2; + if(chip->int_cpu_reg & iCPU_DSC) + clock /=2; /* tseg even = round down, odd = round up */ for (tseg=(0+0+2)*2; tseg<=(MAX_TSEG2+MAX_TSEG1+2)*2+1; tseg++) { @@ -185,7 +211,7 @@ int i82527_baud_rate(struct chip_t *chip, int rate, int clock, int sjw, return 0; } -int i82527_standard_mask(struct chip_t *chip, unsigned short code, unsigned short mask) +int i82527_standard_mask(struct canchip_t *chip, unsigned short code, unsigned short mask) { unsigned char mask0, mask1; @@ -200,7 +226,7 @@ int i82527_standard_mask(struct chip_t *chip, unsigned short code, unsigned shor return 0; } -int i82527_extended_mask(struct chip_t *chip, unsigned long code, unsigned long mask) +int i82527_extended_mask(struct canchip_t *chip, unsigned long code, unsigned long mask) { unsigned char mask0, mask1, mask2, mask3; @@ -219,7 +245,7 @@ int i82527_extended_mask(struct chip_t *chip, unsigned long code, unsigned long return 0; } -int i82527_message15_mask(struct chip_t *chip, unsigned long code, unsigned long mask) +int i82527_message15_mask(struct canchip_t *chip, unsigned long code, unsigned long mask) { unsigned char mask0, mask1, mask2, mask3; @@ -240,14 +266,14 @@ int i82527_message15_mask(struct chip_t *chip, unsigned long code, unsigned long } -int i82527_clear_objects(struct chip_t *chip) +int i82527_clear_objects(struct canchip_t *chip) { int i=0,id=0,data=0; struct msgobj_t *obj; DEBUGMSG("Cleared all message objects on chip\n"); - for (i=1; i<=15; i++) { + for (i=0; imax_objects; i++) { obj=chip->msgobj[i]; canobj_write_reg(chip,obj,(INTPD_RES|RXIE_RES|TXIE_RES|MVAL_RES),iMSGCTL0); canobj_write_reg(chip,obj,(NEWD_RES|MLST_RES|TXRQ_RES|RMPD_RES), iMSGCTL1); @@ -271,14 +297,14 @@ int i82527_clear_objects(struct chip_t *chip) return 0; } -int i82527_config_irqs(struct chip_t *chip, short irqs) +int i82527_config_irqs(struct canchip_t *chip, short irqs) { can_write_reg(chip,irqs,iCTL); DEBUGMSG("Configured hardware interrupt delivery\n"); return 0; } -int i82527_pre_read_config(struct chip_t *chip, struct msgobj_t *obj) +int i82527_pre_read_config(struct canchip_t *chip, struct msgobj_t *obj) { unsigned long id=obj->rx_preconfig_id; @@ -306,7 +332,7 @@ int i82527_pre_read_config(struct chip_t *chip, struct msgobj_t *obj) return 0; } -int i82527_pre_write_config(struct chip_t *chip, struct msgobj_t *obj, +int i82527_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj, struct canmsg_t *msg) { int i=0,id0=0,id1=0,id2=0,id3=0; @@ -346,7 +372,7 @@ int i82527_pre_write_config(struct chip_t *chip, struct msgobj_t *obj, return 0; } -int i82527_send_msg(struct chip_t *chip, struct msgobj_t *obj, +int i82527_send_msg(struct canchip_t *chip, struct msgobj_t *obj, struct canmsg_t *msg) { canobj_write_reg(chip,obj,(MVAL_SET|TXIE_SET|RXIE_RES|INTPD_RES),iMSGCTL0); @@ -361,7 +387,7 @@ int i82527_send_msg(struct chip_t *chip, struct msgobj_t *obj, return 0; } -int i82527_check_tx_stat(struct chip_t *chip) +int i82527_check_tx_stat(struct canchip_t *chip) { if (can_read_reg(chip,iSTAT) & iSTAT_TXOK) { can_write_reg(chip,0x0,iSTAT); @@ -373,7 +399,7 @@ int i82527_check_tx_stat(struct chip_t *chip) } } -int i82527_remote_request(struct chip_t *chip, struct msgobj_t *obj) +int i82527_remote_request(struct canchip_t *chip, struct msgobj_t *obj) { canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0); canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_SET|MLST_RES|NEWD_RES),iMSGCTL1); @@ -381,7 +407,7 @@ int i82527_remote_request(struct chip_t *chip, struct msgobj_t *obj) return 0; } -int i82527_set_btregs(struct chip_t *chip, unsigned short btr0, +int i82527_set_btregs(struct canchip_t *chip, unsigned short btr0, unsigned short btr1) { if (i82527_enable_configuration(chip)) @@ -395,7 +421,7 @@ int i82527_set_btregs(struct chip_t *chip, unsigned short btr0, return 0; } -int i82527_start_chip(struct chip_t *chip) +int i82527_start_chip(struct canchip_t *chip) { unsigned short flags = 0; @@ -405,7 +431,7 @@ int i82527_start_chip(struct chip_t *chip) return 0; } -int i82527_stop_chip(struct chip_t *chip) +int i82527_stop_chip(struct canchip_t *chip) { unsigned short flags = 0; @@ -415,8 +441,21 @@ int i82527_stop_chip(struct chip_t *chip) return 0; } +int i82527_attach_to_chip(struct canchip_t *chip) +{ + return 0; +} + +int i82527_release_chip(struct canchip_t *chip) +{ + i82527_stop_chip(chip); + can_write_reg(chip, (iCTL_CCE|iCTL_INI), iCTL); + + return 0; +} + static inline -void i82527_irq_write_handler(struct chip_t *chip, struct msgobj_t *obj) +void i82527_irq_write_handler(struct canchip_t *chip, struct msgobj_t *obj) { int cmd; @@ -458,7 +497,7 @@ void i82527_irq_write_handler(struct chip_t *chip, struct msgobj_t *obj) } static inline -void i82527_irq_read_handler(struct chip_t *chip, struct msgobj_t *obj, int objnum) +void i82527_irq_read_handler(struct canchip_t *chip, struct msgobj_t *obj, int objnum) { int i; unsigned long message_id; @@ -565,7 +604,7 @@ void i82527_irq_read_handler(struct chip_t *chip, struct msgobj_t *obj, int objn static inline -void i82527_irq_update_filter(struct chip_t *chip, struct msgobj_t *obj) +void i82527_irq_update_filter(struct canchip_t *chip, struct msgobj_t *obj) { struct canfilt_t filt; @@ -582,13 +621,16 @@ void i82527_irq_update_filter(struct chip_t *chip, struct msgobj_t *obj) i82527_pre_read_config(chip, obj); - CANMSG("i82527_irq_update_filter: obj at 0x%08lx\n",obj->obj_base_addr); + CANMSG("i82527_irq_update_filter: obj at 0x%08lx\n", + can_ioptr2ulong(obj->obj_base_addr)); } } -void i82527_irq_sync_activities(struct chip_t *chip, struct msgobj_t *obj) +int i82527_irq_sync_activities(struct canchip_t *chip, struct msgobj_t *obj) { + int job_done=0; + while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)) { if(can_msgobj_test_and_clear_fl(obj,TX_REQUEST)) { @@ -602,6 +644,10 @@ void i82527_irq_sync_activities(struct chip_t *chip, struct msgobj_t *obj) } } + job_done=1; + + mb(); + can_msgobj_clear_fl(obj,TX_LOCK); if(can_msgobj_test_fl(obj,TX_REQUEST)) continue; @@ -609,16 +655,19 @@ void i82527_irq_sync_activities(struct chip_t *chip, struct msgobj_t *obj) continue; break; } + + return job_done; } -can_irqreturn_t i82527_irq_handler(int irq, void *dev_id, struct pt_regs *regs) +int i82527_irq_handler(int irq, struct canchip_t *chip) { unsigned char msgcfg; unsigned irq_register; + unsigned status_register; unsigned object; - struct chip_t *chip=(struct chip_t *)dev_id; struct msgobj_t *obj; + int loop_cnt=CHIP_MAX_IRQLOOP; /*put_reg=device->hwspecops->write_register;*/ /*get_reg=device->hwspecops->read_register;*/ @@ -627,26 +676,33 @@ can_irqreturn_t i82527_irq_handler(int irq, void *dev_id, struct pt_regs *regs) if(!irq_register) { DEBUGMSG("i82527: spurious IRQ\n"); - return CAN_IRQ_NONE; + return CANCHIP_IRQ_NONE; } do { + if(!loop_cnt--) { + CANMSG("i82527_irq_handler IRQ %d stuck\n",irq); + CANMSG("i82527_irq_register 0x%x\n",irq_register); + return CANCHIP_IRQ_STUCK; + } + DEBUGMSG("i82527: iIRQ 0x%02x\n",irq_register); if (irq_register == 0x01) { - DEBUGMSG("Status register: 0x%x\n",can_read_reg(chip, iSTAT)); + status_register=can_read_reg(chip, iSTAT); + CANMSG("Status register: 0x%x\n",status_register); continue; - /*return CAN_IRQ_NONE;*/ + /*return CANCHIP_IRQ_NONE;*/ } if (irq_register == 0x02) object = 14; - else if(irq_register < 14) + else if(irq_register <= 13+3) object = irq_register-3; else - return CAN_IRQ_NONE; + return CANCHIP_IRQ_NONE; obj=chip->msgobj[object]; @@ -655,19 +711,29 @@ can_irqreturn_t i82527_irq_handler(int irq, void *dev_id, struct pt_regs *regs) can_msgobj_set_fl(obj,TX_REQUEST); /* calls i82527_irq_write_handler synchronized with other invocations */ - i82527_irq_sync_activities(chip, obj); + if(i82527_irq_sync_activities(chip, obj)<=0){ + /* The interrupt has to be cleared anyway */ + canobj_write_reg(chip,obj,(MVAL_UNC|TXIE_UNC|RXIE_UNC|INTPD_RES),iMSGCTL0); + + /* + * Rerun for case, that parallel activity on SMP or fully-preemptive + * kernel result in preparation and finished sending of message + * between above if and canobj_write_reg. + */ + i82527_irq_sync_activities(chip, obj); + } } else { i82527_irq_read_handler(chip, obj, object); } - + } while((irq_register=i82527_seg_read_reg(chip, iIRQ)) != 0); - return CAN_IRQ_HANDLED; + return CANCHIP_IRQ_HANDLED; } -void i82527_irq_rtr_handler(struct chip_t *chip, struct msgobj_t *obj, +void i82527_irq_rtr_handler(struct canchip_t *chip, struct msgobj_t *obj, struct rtr_id *rtr_search, unsigned long message_id) { short int i=0; @@ -699,7 +765,7 @@ void i82527_irq_rtr_handler(struct chip_t *chip, struct msgobj_t *obj, * Return Value: negative value reports error. * File: src/i82527.c */ -int i82527_wakeup_tx(struct chip_t *chip, struct msgobj_t *obj) +int i82527_wakeup_tx(struct canchip_t *chip, struct msgobj_t *obj) { can_preempt_disable(); @@ -713,7 +779,7 @@ int i82527_wakeup_tx(struct chip_t *chip, struct msgobj_t *obj) return 0; } -int i82527_filtch_rq(struct chip_t *chip, struct msgobj_t *obj) +int i82527_filtch_rq(struct canchip_t *chip, struct msgobj_t *obj) { can_preempt_disable(); @@ -745,13 +811,16 @@ int i82527_register(struct chipspecops_t *chipspecops) chipspecops->enable_configuration = i82527_enable_configuration; chipspecops->disable_configuration = i82527_disable_configuration; chipspecops->set_btregs = i82527_set_btregs; + chipspecops->attach_to_chip = i82527_attach_to_chip; + chipspecops->release_chip = i82527_release_chip; chipspecops->start_chip = i82527_start_chip; chipspecops->stop_chip = i82527_stop_chip; chipspecops->irq_handler = i82527_irq_handler; + chipspecops->irq_accept = NULL; return 0; } -int i82527_fill_chipspecops(struct chip_t *chip) +int i82527_fill_chipspecops(struct canchip_t *chip) { chip->chip_type="i82527"; chip->max_objects=15;