X-Git-Url: http://rtime.felk.cvut.cz/gitweb/lincan.git/blobdiff_plain/3129fcd8094edcb910b708463fdf1a234f11fb55..23eabc9a14c6b6892b92991109a6f86603309dc5:/lincan/src/pc_i03.c diff --git a/lincan/src/pc_i03.c b/lincan/src/pc_i03.c index daec69c..cd461af 100644 --- a/lincan/src/pc_i03.c +++ b/lincan/src/pc_i03.c @@ -1,19 +1,39 @@ -/* pc-i03.c - * Linux CAN-bus device driver. - * Written by Arnaud Westenberg email:arnaud@wnadoo.nl - * Rewritten for new CAN queues by Pavel Pisa - OCERA team member - * email:pisa@cmp.felk.cvut.cz - * This software is released under the GPL-License. - * Version lincan-0.2 9 Jul 2003 - */ - -#include - -#include -#include -#include -#include +/**************************************************************************/ +/* File: pc_i03.c - PC-I03 ISA card by IXXAT */ +/* */ +/* LinCAN - (Not only) Linux CAN bus driver */ +/* Copyright (C) 2002-2009 DCE FEE CTU Prague */ +/* Copyright (C) 2002-2009 Pavel Pisa */ +/* Funded by OCERA and FRESCOR IST projects */ +/* Based on CAN driver code by Arnaud Westenberg */ +/* */ +/* LinCAN is free software; you can redistribute it and/or modify it */ +/* under terms of the GNU General Public License as published by the */ +/* Free Software Foundation; either version 2, or (at your option) any */ +/* later version. LinCAN is distributed in the hope that it will be */ +/* useful, but WITHOUT ANY WARRANTY; without even the implied warranty */ +/* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU */ +/* General Public License for more details. You should have received a */ +/* copy of the GNU General Public License along with LinCAN; see file */ +/* COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, */ +/* Cambridge, MA 02139, USA. */ +/* */ +/* To allow use of LinCAN in the compact embedded systems firmware */ +/* and RT-executives (RTEMS for example), main authors agree with next */ +/* special exception: */ +/* */ +/* Including LinCAN header files in a file, instantiating LinCAN generics */ +/* or templates, or linking other files with LinCAN objects to produce */ +/* an application image/executable, does not by itself cause the */ +/* resulting application image/executable to be covered by */ +/* the GNU General Public License. */ +/* This exception does not however invalidate any other reasons */ +/* why the executable file might be covered by the GNU Public License. */ +/* Publication of enhanced or derived LinCAN files is required although. */ +/**************************************************************************/ +#include "../include/can.h" +#include "../include/can_sysdep.h" #include "../include/main.h" #include "../include/pc-i03.h" #include "../include/sja1000.h" @@ -22,7 +42,7 @@ * we need it global, else we have to change many internal functions. * pc-i03_base_addr is initialized in pc-i03_init_chip_data(). */ -unsigned int pci03_base_addr; +unsigned int pci03_base_addr; /* * IO_RANGE is the io-memory range that gets reserved, please adjust according @@ -38,7 +58,7 @@ unsigned int pci03_base_addr; * * The function pci03_request_io() is used to reserve the io-memory. If your * hardware uses a dedicated memory range as hardware control registers you - * will have to add the code to reserve this memory as well. + * will have to add the code to reserve this memory as well. * %IO_RANGE is the io-memory range that gets reserved, please adjust according * your hardware. Example: #define IO_RANGE 0x100 for i82527 chips or * #define IO_RANGE 0x20 for sja1000 chips in basic CAN mode. @@ -79,8 +99,8 @@ int pci03_release_io(struct candevice_t *candev) * pci03_reset - hardware reset routine * @candev: Pointer to candevice/board structure * - * The function pci03_reset() is used to give a hardware reset. This is - * rather hardware specific so I haven't included example code. Don't forget to + * The function pci03_reset() is used to give a hardware reset. This is + * rather hardware specific so I haven't included example code. Don't forget to * check the reset status of the chip before returning. * Return Value: The function returns zero on success or %-ENODEV on failure * File: src/pc-i03.c @@ -92,15 +112,15 @@ int pci03_reset(struct candevice_t *candev) DEBUGMSG("Resetting pc-i03 hardware ...\n"); pci03_write_register(0x01,pci03_base_addr + 0x100); // Write arbitrary data to reset mem - udelay(20000); + mdelay(20); pci03_write_register(0x00, pci03_base_addr + SJACR); - + /* Check hardware reset status */ i=0; - while ( (pci03_read_register(pci03_base_addr + SJACR) & CR_RR) + while ( (pci03_read_register(pci03_base_addr + SJACR) & sjaCR_RR) && (i<=15) ) { - udelay(20000); + mdelay(20); i++; } if (i>=15) { @@ -127,12 +147,12 @@ int pci03_reset(struct candevice_t *candev) * %RESET_ADDR represents the io-address of the hardware reset register. * %NR_82527 represents the number of intel 82527 chips on the board. * %NR_SJA1000 represents the number of philips sja1000 chips on the board. - * The flags entry can currently only be %PROGRAMMABLE_IRQ to indicate that + * The flags entry can currently only be %CANDEV_PROGRAMMABLE_IRQ to indicate that * the hardware uses programmable interrupts. * Return Value: The function always returns zero * File: src/pc-i03.c */ -int pci03_init_hw_data(struct candevice_t *candev) +int pci03_init_hw_data(struct candevice_t *candev) { candev->res_addr=RESET_ADDR; candev->nr_82527_chips=NR_82527; @@ -141,7 +161,6 @@ int pci03_init_hw_data(struct candevice_t *candev) return 0; } -#define CHIP_TYPE "sja1000" /** * pci03_init_chip_data - Initialize chips * @candev: Pointer to candevice/board structure @@ -157,15 +176,15 @@ int pci03_init_hw_data(struct candevice_t *candev) * The @clock entry holds the chip clock value in Hz. * The entry @sja_cdr_reg holds hardware specific options for the Clock Divider * register. Options defined in the %sja1000.h file: - * %CDR_CLKOUT_MASK, %CDR_CLK_OFF, %CDR_RXINPEN, %CDR_CBP, %CDR_PELICAN + * %sjaCDR_CLKOUT_MASK, %sjaCDR_CLK_OFF, %sjaCDR_RXINPEN, %sjaCDR_CBP, %sjaCDR_PELICAN * The entry @sja_ocr_reg holds hardware specific options for the Output Control * register. Options defined in the %sja1000.h file: - * %OCR_MODE_BIPHASE, %OCR_MODE_TEST, %OCR_MODE_NORMAL, %OCR_MODE_CLOCK, - * %OCR_TX0_LH, %OCR_TX1_ZZ. + * %sjaOCR_MODE_BIPHASE, %sjaOCR_MODE_TEST, %sjaOCR_MODE_NORMAL, %sjaOCR_MODE_CLOCK, + * %sjaOCR_TX0_LH, %sjaOCR_TX1_ZZ. * The entry @int_clk_reg holds hardware specific options for the Clock Out * register. Options defined in the %i82527.h file: * %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1. - * The entry @int_bus_reg holds hardware specific options for the Bus + * The entry @int_bus_reg holds hardware specific options for the Bus * Configuration register. Options defined in the %i82527.h file: * %iBUS_DR0, %iBUS_DR1, %iBUS_DT1, %iBUS_POL, %iBUS_CBY. * Return Value: The function always returns zero @@ -173,13 +192,13 @@ int pci03_init_hw_data(struct candevice_t *candev) */ int pci03_init_chip_data(struct candevice_t *candev, int chipnr) { + sja1000_fill_chipspecops(candev->chip[chipnr]); pci03_base_addr = candev->io_addr; - candev->chip[chipnr]->chip_type=CHIP_TYPE; candev->chip[chipnr]->chip_base_addr=candev->io_addr; candev->chip[chipnr]->clock = 16000000; - candev->chip[chipnr]->sja_cdr_reg = CDR_CBP | CDR_CLK_OFF; - candev->chip[chipnr]->sja_ocr_reg = OCR_MODE_NORMAL | - OCR_TX0_HL | OCR_TX1_LZ; + candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CBP | sjaCDR_CLK_OFF; + candev->chip[chipnr]->sja_ocr_reg = sjaOCR_MODE_NORMAL | + sjaOCR_TX0_HL | sjaOCR_TX1_LZ; return 0; } @@ -194,18 +213,17 @@ int pci03_init_chip_data(struct candevice_t *candev, int chipnr) * CAN chip. In case of the sja1000 there's only one message object but on the * i82527 chip there are 15. * The code below is for a i82527 chip and initializes the object base addresses - * The entry @obj_base_addr represents the first memory address of the message + * The entry @obj_base_addr represents the first memory address of the message * object. In case of the sja1000 @obj_base_addr is taken the same as the chips * base address. * Unless the hardware uses a segmented memory map, flags can be set zero. * Return Value: The function always returns zero * File: src/pc-i03.c */ -int pci03_init_obj_data(struct chip_t *chip, int objnr) +int pci03_init_obj_data(struct canchip_t *chip, int objnr) { chip->msgobj[objnr]->obj_base_addr=chip->chip_base_addr; - chip->msgobj[objnr]->flags=0; - + return 0; } @@ -213,10 +231,10 @@ int pci03_init_obj_data(struct chip_t *chip, int objnr) * pci03_program_irq - program interrupts * @candev: Pointer to candevice/board structure * - * The function pci03_program_irq() is used for hardware that uses + * The function pci03_program_irq() is used for hardware that uses * programmable interrupts. If your hardware doesn't use programmable interrupts - * you should not set the @candevices_t->flags entry to %PROGRAMMABLE_IRQ and - * leave this function unedited. Again this function is hardware specific so + * you should not set the @candevices_t->flags entry to %CANDEV_PROGRAMMABLE_IRQ and + * leave this function unedited. Again this function is hardware specific so * there's no example code. * Return value: The function returns zero on success or %-ENODEV on failure * File: src/pc-i03.c @@ -237,7 +255,7 @@ int pci03_program_irq(struct candevice_t *candev) * Return Value: The function does not return a value * File: src/pc-i03.c */ -void pci03_write_register(unsigned char data, unsigned long address) +void pci03_write_register(unsigned data, can_ioptr_t address) { unsigned int *pci03_base_ptr; unsigned short address_to_write; @@ -262,7 +280,7 @@ void pci03_write_register(unsigned char data, unsigned long address) * Return Value: The function returns the value stored in @address * File: src/pc-i03.c */ -unsigned pci03_read_register(unsigned long address) +unsigned pci03_read_register(can_ioptr_t address) { unsigned int *pci03_base_ptr; unsigned short address_to_read;