X-Git-Url: http://rtime.felk.cvut.cz/gitweb/lincan.git/blobdiff_plain/2a4663dd0b20d96d1ffe20993dd0c63ed2ca9f20..9c8ab08d7e8fca3916a7f91a3c001d151989137c:/lincan/src/msmcan.c diff --git a/lincan/src/msmcan.c b/lincan/src/msmcan.c index 42513ad..f24bfa5 100644 --- a/lincan/src/msmcan.c +++ b/lincan/src/msmcan.c @@ -1,11 +1,36 @@ -/* msmcan.c - * Linux CAN-bus device driver. - * Written by Arnaud Westenberg email:arnaud@wanadoo.nl - * Rewritten for new CAN queues by Pavel Pisa - OCERA team member - * email:pisa@cmp.felk.cvut.cz - * This software is released under the GPL-License. - * Version lincan-0.3 17 Jun 2004 - */ +/**************************************************************************/ +/* File: msmcan.c - MICROSPACE IO space indexed i82527 PC104 card */ +/* */ +/* LinCAN - (Not only) Linux CAN bus driver */ +/* Copyright (C) 2002-2009 DCE FEE CTU Prague */ +/* Copyright (C) 2002-2009 Pavel Pisa */ +/* Funded by OCERA and FRESCOR IST projects */ +/* Based on CAN driver code by Arnaud Westenberg */ +/* */ +/* LinCAN is free software; you can redistribute it and/or modify it */ +/* under terms of the GNU General Public License as published by the */ +/* Free Software Foundation; either version 2, or (at your option) any */ +/* later version. LinCAN is distributed in the hope that it will be */ +/* useful, but WITHOUT ANY WARRANTY; without even the implied warranty */ +/* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU */ +/* General Public License for more details. You should have received a */ +/* copy of the GNU General Public License along with LinCAN; see file */ +/* COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, */ +/* Cambridge, MA 02139, USA. */ +/* */ +/* To allow use of LinCAN in the compact embedded systems firmware */ +/* and RT-executives (RTEMS for example), main authors agree with next */ +/* special exception: */ +/* */ +/* Including LinCAN header files in a file, instantiating LinCAN generics */ +/* or templates, or linking other files with LinCAN objects to produce */ +/* an application image/executable, does not by itself cause the */ +/* resulting application image/executable to be covered by */ +/* the GNU General Public License. */ +/* This exception does not however invalidate any other reasons */ +/* why the executable file might be covered by the GNU Public License. */ +/* Publication of enhanced or derived LinCAN files is required although. */ +/**************************************************************************/ #include "../include/can.h" #include "../include/can_sysdep.h" @@ -13,7 +38,7 @@ #include "../include/msmcan.h" #include "../include/i82527.h" -static can_spinlock_t msmcan_port_lock=SPIN_LOCK_UNLOCKED; +static CAN_DEFINE_SPINLOCK(msmcan_port_lock); /* IO_RANGE is the io-memory range that gets reserved, please adjust according * your hardware. Example: #define IO_RANGE 0x100 for i82527 chips or @@ -56,12 +81,12 @@ int msmcan_release_io(struct candevice_t *candev) */ int msmcan_reset(struct candevice_t *candev) { - struct chip_t *chip=candev->chip[0]; + struct canchip_t *chip=candev->chip[0]; DEBUGMSG("Resetting msmcan hardware ...\n"); /* we don't use template_write_register because we don't use the two first registers of the card but the third in order to make a hard reset */ - /* outb (1, msmcan_base + candev->res_addr); */ + /* can_outb (1, msmcan_base + candev->res_addr); */ /* terrible MSMCAN reset design - best to comment out */ @@ -128,7 +153,7 @@ int msmcan_init_chip_data(struct candevice_t *candev, int chipnr) i82527_fill_chipspecops(candev->chip[chipnr]); /* device uses indexed access */ candev->chip[chipnr]->chip_base_addr= - candev->io_addr << 16; + can_ioport2ioptr(candev->io_addr << 16); candev->chip[chipnr]->clock = 16000000; /* The CLKOUT has to be enabled to reset MSMCAN MAX1232 watchdog */ candev->chip[chipnr]->int_cpu_reg = iCPU_DSC | iCPU_CEN; @@ -148,7 +173,7 @@ int msmcan_init_chip_data(struct candevice_t *candev, int chipnr) * base address. * Unless the hardware uses a segmented memory map, flags can be set zero. */ -int msmcan_init_obj_data(struct chip_t *chip, int objnr) +int msmcan_init_obj_data(struct canchip_t *chip, int objnr) { chip->msgobj[objnr]->obj_base_addr= @@ -172,17 +197,18 @@ int msmcan_program_irq(struct candevice_t *candev) * on the CAN chip. You should only have to edit this function if your hardware * uses some specific write process. */ -void msmcan_write_register(unsigned data, unsigned long address) +void msmcan_write_register(unsigned data, can_ioptr_t address) { /* address is combination of base address shifted left by 16 and index */ can_spin_irqflags_t flags; + unsigned long addr=can_ioptr2ulong(address); /* the msmcan card has two registers, the data register at 0x0 and the address register at 0x01 */ can_spin_lock_irqsave(&msmcan_port_lock,flags); - outb(address & 0xff, (address>>16)+1); - outb(data, address>>16); + can_outb(addr & 0xff, (addr>>16)+1); + can_outb(data, addr>>16); can_spin_unlock_irqrestore(&msmcan_port_lock,flags); } @@ -190,7 +216,7 @@ void msmcan_write_register(unsigned data, unsigned long address) * on the CAN chip. You should only have to edit this function if your hardware * uses some specific read process. */ -unsigned msmcan_read_register(unsigned long address) +unsigned msmcan_read_register(can_ioptr_t address) { /* this is the same thing that the function write_register. We use the two register, we write the address where we @@ -198,11 +224,11 @@ unsigned msmcan_read_register(unsigned long address) data */ unsigned char ret; can_spin_irqflags_t flags; - + unsigned long addr=can_ioptr2ulong(address); can_spin_lock_irqsave(&msmcan_port_lock,flags); - outb(address & 0xff, (address>>16)+1); - ret=inb(address>>16); + can_outb(addr & 0xff, (addr>>16)+1); + ret=can_inb(addr>>16); can_spin_unlock_irqrestore(&msmcan_port_lock,flags); return ret; }