X-Git-Url: http://rtime.felk.cvut.cz/gitweb/lincan.git/blobdiff_plain/1dc12dbb2a85083785e71adc487084f117869120..831ccb1f14f7472962fc2d185f32e18105209bd7:/lincan/src/c_can.c?ds=sidebyside

diff --git a/lincan/src/c_can.c b/lincan/src/c_can.c
index beb26d0..cddac82 100644
--- a/lincan/src/c_can.c
+++ b/lincan/src/c_can.c
@@ -19,10 +19,10 @@
 extern int stdmask;
 extern int extmask;
 
-can_spinlock_t c_can_spwlock = SPIN_LOCK_UNLOCKED;	// Spin lock for write operations
-can_spinlock_t c_can_sprlock = SPIN_LOCK_UNLOCKED;	// Spin lock for read operations
-can_spinlock_t c_can_if1lock = SPIN_LOCK_UNLOCKED;	// spin lock for the if1 register
-can_spinlock_t c_can_if2lock = SPIN_LOCK_UNLOCKED;	// spin lcok for the if2 register
+CAN_DEFINE_SPINLOCK(c_can_spwlock);	// Spin lock for write operations
+CAN_DEFINE_SPINLOCK(c_can_sprlock);	// Spin lock for read operations
+CAN_DEFINE_SPINLOCK(c_can_if1lock);	// spin lock for the if1 register
+CAN_DEFINE_SPINLOCK(c_can_if2lock);	// spin lcok for the if2 register
 
 /**
  * c_can_enable_configuration - enable chip configuration mode
@@ -96,10 +96,10 @@ int c_can_chip_config(struct canchip_t *pchip)
 		return -1;
 
 	if (pchip->baudrate == 0)
-		pchip->baudrate = 1000;
+		pchip->baudrate = 1000000;
 
 	if (c_can_baud_rate
-	    (pchip, pchip->baudrate * 1000, pchip->clock, 0, 75, 0)) {
+	    (pchip, pchip->baudrate, pchip->clock, 0, 75, 0)) {
 		CANMSG("Error configuring baud rate\n");
 		return -ENODEV;
 	}
@@ -143,8 +143,8 @@ int c_can_if1_busycheck(struct canchip_t *pchip)
 	unsigned short comreg = 0;
 
 	comreg = c_can_read_reg_w(pchip, CCIF1CR);
-	while ((comreg & IFXCR_BUSY) && (i <= 10)) {
-		udelay(100);	//100 microseconds
+	while ((comreg & IFXCR_BUSY) && (i <= 100)) {
+		udelay(1);	//1 microseconds
 		i++;
 		comreg = c_can_read_reg_w(pchip, CCIF1CR);
 	}
@@ -167,8 +167,8 @@ int c_can_if2_busycheck(struct canchip_t *pchip)
 	unsigned short comreg = 0;
 
 	comreg = c_can_read_reg_w(pchip, CCIF2CR);
-	while ((comreg & IFXCR_BUSY) && (i <= 10)) {
-		udelay(100);	//100 microseconds
+	while ((comreg & IFXCR_BUSY) && (i <= 100)) {
+		udelay(1);	//1 microseconds
 		i++;
 		comreg = c_can_read_reg_w(pchip, CCIF2CR);
 	}
@@ -296,6 +296,11 @@ int c_can_mask(struct msgobj_t *pmsgobj, u32 mask, u16 usedirbit)
 	if (c_can_if1_busycheck(pmsgobj->hostchip))
 		return -ENODEV;
 
+	//set indication, that mask is used
+	tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1DMC);
+	c_can_write_reg_w(pmsgobj->hostchip, tempreg | IFXMC_UMASK,
+		CCIF1DMC);
+
 	//writing acceptance mask for extended or standart mode
 	if (can_msgobj_test_fl(pmsgobj, RX_MODE_EXT)) {
 		if (usedirbit)
@@ -317,6 +322,7 @@ int c_can_mask(struct msgobj_t *pmsgobj, u32 mask, u16 usedirbit)
 					  ((mask << 2) & 0x1FFC), CCIF1M2);
 		c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF1M1);
 	}
+
 	//seting Message Valid Bit to one
 	tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1A2);
 	c_can_write_reg_w(pmsgobj->hostchip, tempreg | IFXARB2_MVAL, CCIF1A2);
@@ -810,7 +816,7 @@ int c_can_wakeup_tx(struct canchip_t *chip, struct msgobj_t *obj)
 
 	can_msgobj_set_fl(obj, TX_REQUEST);
 
-	/* calls i82527_irq_write_handler synchronized with other invocations
+	/* calls c_can_irq_write_handler synchronized with other invocations
 	   from kernel and IRQ context */
 	c_can_irq_sync_activities(chip, obj);