X-Git-Url: http://rtime.felk.cvut.cz/gitweb/lincan.git/blobdiff_plain/161458aa55efa998db8f00bb9f16e1ee02fb77a2..074e90ee2a9a0a573bc987097650e9c1ec233337:/lincan/src/pip.c

diff --git a/lincan/src/pip.c b/lincan/src/pip.c
index add0fee..345dd78 100644
--- a/lincan/src/pip.c
+++ b/lincan/src/pip.c
@@ -1,17 +1,38 @@
-/* pip.c
- * Linux CAN-bus device driver.
- * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
- * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
- * email:pisa@cmp.felk.cvut.cz
- * Adapted for actual PIP5 Version and PIP7 and PIP8 by
- * Stefan Peter, MPL AG, Switzerland
- * email:support@mpl.ch
- * This software is released under the GPL-License.
- * Version lincan-0.3  17 Jun 2004
- */
-/* This is the CAN driver for the PIP5,PIP6,PIP7 and PIP8 
- * Packaged Industrial PCs of MPL AG, Switzerland. 
- */
+/**************************************************************************/
+/* File: pip.c - support for PIP5,PIP6,PIP7 and PIP8 boards for           */
+/*               Packaged Industrial PCs supportof MPL AG, Switzerland    */
+/*                                                                        */
+/* LinCAN - (Not only) Linux CAN bus driver                               */
+/* Copyright (C) 2002-2009 DCE FEE CTU Prague <http://dce.felk.cvut.cz>   */
+/* Copyright (C) 2002-2009 Pavel Pisa <pisa@cmp.felk.cvut.cz>             */
+/* Copyright (C) 2005-2006 Stefan Peter, MPL AG, Switzerland              */
+/* Funded by OCERA and FRESCOR IST projects                               */
+/* Based on CAN driver code by Arnaud Westenberg <arnaud@wanadoo.nl>      */
+/*                                                                        */
+/* LinCAN is free software; you can redistribute it and/or modify it      */
+/* under terms of the GNU General Public License as published by the      */
+/* Free Software Foundation; either version 2, or (at your option) any    */
+/* later version.  LinCAN is distributed in the hope that it will be      */
+/* useful, but WITHOUT ANY WARRANTY; without even the implied warranty    */
+/* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU    */
+/* General Public License for more details. You should have received a    */
+/* copy of the GNU General Public License along with LinCAN; see file     */
+/* COPYING. If not, write to the Free Software Foundation, 675 Mass Ave,  */
+/* Cambridge, MA 02139, USA.                                              */
+/*                                                                        */
+/* To allow use of LinCAN in the compact embedded systems firmware        */
+/* and RT-executives (RTEMS for example), main authors agree with next    */
+/* special exception:                                                     */
+/*                                                                        */
+/* Including LinCAN header files in a file, instantiating LinCAN generics */
+/* or templates, or linking other files with LinCAN objects to produce    */
+/* an application image/executable, does not by itself cause the          */
+/* resulting application image/executable to be covered by                */
+/* the GNU General Public License.                                        */
+/* This exception does not however invalidate any other reasons           */
+/* why the executable file might be covered by the GNU Public License.    */
+/* Publication of enhanced or derived LinCAN files is required although.  */
+/**************************************************************************/
 
 
 #include "../include/can.h"
@@ -71,14 +92,14 @@ int pip_reset(struct candevice_t *candev)
 	DEBUGMSG("Resetting %s hardware ...\n", candev->hwname);
 	while (i < 1000000) {
 		i++;
-		outb(0x01, candev->res_addr);
+		can_outb(0x01, candev->res_addr);
 	}
-	outb(0x0, candev->res_addr);
+	can_outb(0x0, candev->res_addr);
 
 	/* Check hardware reset status */
 	i = 0;
-	while ((inb(candev->io_addr + iCPU) & iCPU_RST) && (i <= 15)) {
-		udelay(20000);
+	while ((can_inb(candev->io_addr + iCPU) & iCPU_RST) && (i <= 15)) {
+		mdelay(20);
 		i++;
 	}
 	if (i >= 15) {
@@ -106,7 +127,7 @@ int pip_init_hw_data(struct candevice_t *candev)
 int pip_init_chip_data(struct candevice_t *candev, int chipnr)
 {
 	i82527_fill_chipspecops(candev->chip[chipnr]);
-	candev->chip[chipnr]->chip_base_addr = candev->io_addr;
+	candev->chip[chipnr]->chip_base_addr = can_ioport2ioptr(candev->io_addr);
 	candev->chip[chipnr]->clock = 8000000;
 	candev->chip[chipnr]->int_cpu_reg = 0;
 	candev->chip[chipnr]->int_clk_reg = iCLK_SL1;
@@ -131,7 +152,7 @@ int pip_program_irq(struct candevice_t *candev)
 	unsigned char can_addr = 0, can_reg = 0;
 	DEBUGMSG("pip_program_irq\n");
 	/* Reset can controller */
-	outb(0x01, candev->res_addr);
+	can_outb(0x01, candev->res_addr);
 	if (strcmp(candev->hwname, "pip5") == 0) {
 		irq_mask = PIP5_IRQ_MAP;
 	} else if (strcmp(candev->hwname, "pip6") == 0) {
@@ -175,26 +196,26 @@ int pip_program_irq(struct candevice_t *candev)
 			return -ENODEV;
 		}
 	}
-	can_reg = inb(PIP_CANRES_REG);
+	can_reg = can_inb(PIP_CANRES_REG);
 	DEBUGMSG("PIP_CANRES was 0x%x\n", can_reg);
 	can_reg = (candev->chip[0]->chip_irq << 4) | can_addr;
 	DEBUGMSG("Setting PIP_CANRES_REG to 0x%x\n", can_reg);
-	outb((candev->chip[0]->chip_irq << 4) | can_addr, PIP_CANRES_REG);
+	can_outb((candev->chip[0]->chip_irq << 4) | can_addr, PIP_CANRES_REG);
 	/* re-enable the chip */
-	outb(0x00, candev->res_addr);
+	can_outb(0x00, candev->res_addr);
 
 	return 0;
 }
 
 
-void pip_write_register(unsigned data, unsigned long address)
+void pip_write_register(unsigned data, can_ioptr_t address)
 {
-	outb(data, address);
+	can_outb(data, address);
 }
 
-unsigned pip_read_register(unsigned long address)
+unsigned pip_read_register(can_ioptr_t address)
 {
-	return inb(address);
+	return can_inb(address);
 }
 
 /* !!! Don't change these functions !!! */