}
+void CAN_set_bittiming(struct canchip_t *chip, uint32_t brp, uint32_t sjw, uint32_t tseg1, uint32_t tseg2){
+
+ uint8_t SAM = 0; // 0 = the bus is sampled once
+
+ brp--;
+ sjw--;
+ tseg1--;
+ tseg2--;
+
+ can_disable_irq(chip->chip_irq);
+ // enter reset mode
+ can_write_reg(chip, 1, CAN_MOD_o);
+
+
+ can_write_reg(chip, ((SAM<<23)|(tseg2<<20)|(tseg1<<16)|(sjw<<14)|(brp<<0)), CAN_BTR_o);
+
+
+ // return to normal operating
+ can_write_reg(chip, 0, CAN_MOD_o);
+
+ can_enable_irq(chip->chip_irq);
+}
+
void CAN_setBusTiming(struct canchip_t *chip){
uint32_t PCLK_CAN;