/* Check hardware reset status */
i=0;
- while ( (inb(candev->chip[0]->chip_base_addr+SJACR) & CR_RR)
+ while ( (inb(candev->chip[0]->chip_base_addr+SJACR) & sjaCR_RR)
&& (i<=15) ) {
udelay(20000);
i++;
for (chip_nr=0; chip_nr<2; chip_nr++) {
i=0;
while ( (inb(candev->chip[chip_nr]->chip_base_addr +
- SJACR) & CR_RR) && (i<=15) ) {
+ SJACR) & sjaCR_RR) && (i<=15) ) {
udelay(20000);
i++;
}
for (chip_nr=2; chip_nr<4; chip_nr++) {
i=0;
while( (inb(candev->chip[chip_nr]->chip_base_addr +
- SJACR) & CR_RR) && (i<=15) ) {
+ SJACR) & sjaCR_RR) && (i<=15) ) {
udelay(20000);
i++;
}
candev->chip[chipnr]->int_clk_reg = 0;
candev->chip[chipnr]->int_bus_reg = 0;
candev->chip[chipnr]->sja_cdr_reg =
- CDR_CLK_OFF;
+ sjaCDR_CLK_OFF;
candev->chip[chipnr]->sja_ocr_reg =
- OCR_MODE_NORMAL | OCR_TX0_LH;
+ sjaOCR_MODE_NORMAL | sjaOCR_TX0_LH;
}
candev->chip[chipnr]->chip_base_addr=0x1000*chipnr+0x2000+candev->io_addr;
}
candev->chip[chipnr]->int_cpu_reg = 0;
candev->chip[chipnr]->int_clk_reg = 0;
candev->chip[chipnr]->int_bus_reg = 0;
- candev->chip[chipnr]->sja_cdr_reg = CDR_CLK_OFF;
+ candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CLK_OFF;
candev->chip[chipnr]->sja_ocr_reg =
- OCR_MODE_NORMAL | OCR_TX0_LH;
+ sjaOCR_MODE_NORMAL | sjaOCR_TX0_LH;
}
candev->chip[chipnr]->clock = 16000000;