More updates in the C_CAN support, but locking not reworked still.

[lincan.git] / lincan / include / c_can.h

diff --git a/lincan/include/c_can.h b/lincan/include/c_can.h
index 1c3bb8ff8c04d711ec7f873482b5586cf46fe38e..f5d9d10bfa045e79487501ab0d7887cd3ada439f 100644 (file)
--- a/lincan/include/c_can.h
+++ b/lincan/include/c_can.h
@@ -68,51 +68,69 @@ int c_can_register(struct chipspecops_t *chipspecops);
 
 void c_can_registerdump(struct canchip_t *pchip);
 
+void c_can_if1_registerdump(struct canchip_t *pchip);
+
 void c_can_irq_sync_activities(struct canchip_t *chip, struct msgobj_t *obj);
 
-int c_can_irq_handler(int irq, struct canchip_t *chip);
-
-int c_can_fill_chipspecops(struct canchip_t *chip);
-
-/* BasicCAN mode address map */
-#define CCCR      0x0000       /* Control Register */
-#define CCSR           0x0004  /* Status Register */
-#define CCEC           0x0008  /* Error Counting Register */
-#define CCBT           0x000C  /* Bit Timing Register */
-#define CCINTR         0x0010  /* Interrupt Register */
-#define CCTR           0x0014  /* Test Register */
-#define CCBRPE         0x0018  /* Baud Rate Prescaler Extension Register */
-#define CCCE           0x001C  /* CAN Enable Register */
-#define CCTREQ1        0x0100  /* Transmission Request 1 Register */
-#define CCTREQ2        0x0104  /* Transmission Request 2 Register */
-#define CCND1     0x0120       /* New Data 1 Register */
-#define CCND2     0x0124       /* New Data 2 Register */
-#define CCINTP1        0x0140  /* Interrupt Pending 1 Register */
-#define CCINTP2        0x0144  /* Interrupt Pending 2 Register */
-
-#define CCIF1CR        0x0020  /* Interface 1 Command Request Register */
-#define CCIF1CM        0x0024  /* IF1 Command Mask Register */
-#define CCIF1M1        0x0028  /* IF1 Mask 1 Register */
-#define CCIF1M2        0x002C  /* IF1 Mask 2 Register */
-#define CCIF1A1        0x0030  /* IF1 Arbitration 1 Register */
-#define CCIF1A2        0x0034  /* IF1 Arbitration 2 Register */
-#define CCIF1DMC       0x0038  /* IF1 Message Control Register */
-#define CCIF1DA1       0x003C  /* IF1 Data A 1 Register */
-#define CCIF1DA2       0x0040  /* IF1 Data A 2 Register */
-#define CCIF1DB1       0x0044  /* IF1 Data B 1 Register */
-#define CCIF1DB2       0x0048  /* IF1 Data B 2 Register */
-
-#define CCIF2CR        0x0080  /* Interface 2 Command Request Register */
-#define CCIF2CM        0x0084  /* IF2 Command Mask Register */
-#define CCIF2M1        0x0088  /* IF2 Mask 1 Register */
-#define CCIF2M2        0x008C  /* IF2 Mask 2 Register */
-#define CCIF2A1        0x0090  /* IF2 Arbitration 1 Register */
-#define CCIF2A2        0x0094  /* IF2 Arbitration 2 Register */
-#define CCIF2DMC       0x0098  /* IF2 Message Control Register */
-#define CCIF2DA1       0x009C  /* IF2 Data A 1 Register */
-#define CCIF2DA2       0x00A0  /* IF2 Data A 2 Register */
-#define CCIF2DB1       0x00A4  /* IF2 Data B 1 Register */
-#define CCIF2DB2       0x00A8  /* IF2 Data B 2 Register */
+int c_can_irq_handler(int irq, struct canchip_t *pchip);
+
+int c_can_fill_chipspecops(struct canchip_t *pchip);
+
+/* The CCCE register is not implemented in version 1.2 of C_CAN */
+#undef C_CAN_WITH_CCCE
+
+/* The mask of C_CAN registers offsets */
+#define C_CAN_REGOFFS_MASK     0xFF
+
+/* SSEE C_CAN Memory map */
+/* BasicCAN offsets are multiplied by two */
+#define CCCR           0x00    /* Control Register */
+#define CCSR           0x02    /* Status Register */
+#define CCEC           0x04    /* Error Counting Register */
+#define CCBT           0x06    /* Bit Timing Register */
+#define CCINTR         0x08    /* Interrupt Register */
+#define CCTR           0x0A    /* Test Register */
+#define CCBRPE                 0x0C    /* Baud Rate Prescaler Extension Register */
+
+#ifdef C_CAN_WITH_CCCE
+#define CCCE           0x0E    /* CAN Enable Register */
+#endif /*C_CAN_WITH_CCCE*/
+
+#define CCIF1CR                0x10    /* Interface 1 Command Request Register */
+#define CCIF1CM                0x12    /* IF1 Command Mask Register */
+#define CCIF1M1                0x14    /* IF1 Mask 1 Register */
+#define CCIF1M2                0x16    /* IF1 Mask 2 Register */
+#define CCIF1A1                0x18    /* IF1 Arbitration 1 Register */
+#define CCIF1A2                0x1A    /* IF1 Arbitration 2 Register */
+#define CCIF1DMC       0x1C    /* IF1 Message Control Register */
+#define CCIF1DA1       0x1E    /* IF1 Data A 1 Register */
+#define CCIF1DA2       0x20    /* IF1 Data A 2 Register */
+#define CCIF1DB1       0x22    /* IF1 Data B 1 Register */
+#define CCIF1DB2       0x24    /* IF1 Data B 2 Register */
+
+#define CCIF2CR                0x40    /* Interface 2 Command Request Register */
+#define CCIF2CM                0x42    /* IF2 Command Mask Register */
+#define CCIF2M1                0x44    /* IF2 Mask 1 Register */
+#define CCIF2M2                0x46    /* IF2 Mask 2 Register */
+#define CCIF2A1                0x48    /* IF2 Arbitration 1 Register */
+#define CCIF2A2                0x4A    /* IF2 Arbitration 2 Register */
+#define CCIF2DMC       0x4C    /* IF2 Message Control Register */
+#define CCIF2DA1       0x4E    /* IF2 Data A 1 Register */
+#define CCIF2DA2       0x50    /* IF2 Data A 2 Register */
+#define CCIF2DB1       0x52    /* IF2 Data B 1 Register */
+#define CCIF2DB2       0x54    /* IF2 Data B 2 Register */
+
+#define CCTREQ1        0x80    /* Transmission Request 1 Register */
+#define CCTREQ2        0x82    /* Transmission Request 2 Register */
+
+#define CCND1          0x90    /* New Data 1 Register */
+#define CCND2          0x92    /* New Data 2 Register */
+
+#define CCINTP1        0xA0    /* Interrupt Pending 1 Register */
+#define CCINTP2                0xA2    /* Interrupt Pending 2 Register */
+
+#define CCIMV1         0xB0    /* Message Valid 1 Register   */
+#define CCIMV2         0xB2    /* Message Valid 2 Register   */
 
 /* Control register */
 enum c_can_BASIC_CR