Changes to prepare work area for C_CAN testing and rethinking

[lincan.git] / lincan / src / c_can.c

diff --git a/lincan/src/c_can.c b/lincan/src/c_can.c
index 0efc91fcb538b42204a0549d694fff01f6cb0e60..e51181b0233c778678676b27ca6b2e87647f96f6 100644 (file)
--- a/lincan/src/c_can.c
+++ b/lincan/src/c_can.c
@@ -215,8 +215,6 @@ int c_can_baud_rate(struct canchip_t *pchip, int rate, int clock,
    if (c_can_enable_configuration(pchip))
      return -ENODEV;
 
-   clock /=2;
-
        /* tseg even = round down, odd = round up */
    for (tseg=(0+0+2)*2; tseg<=(MAX_TSEG2+MAX_TSEG1+2)*2+1; tseg++)
      {
@@ -237,7 +235,7 @@ int c_can_baud_rate(struct canchip_t *pchip, int rate, int clock,
    if (best_error && (rate/best_error < 10))
      {
        CANMSG("baud rate %d is not possible with %d Hz clock\n",
-              rate, 2*clock);
+              rate, clock);
        CANMSG("%d bps. brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d\n",
               best_rate, best_brp, best_tseg, tseg1, tseg2);
        return -EINVAL;
@@ -467,11 +465,6 @@ int c_can_config_irqs(struct canchip_t *pchip,
 
    DEBUGMSG("(c%d)calling c_can_config_irqs(...)\n", pchip->chip_idx);
 
-   /*
-    CANMSG("c_can_config_irqs not implemented\n");
-    return -ENOSYS;
-    */
-
    tempreg = c_can_read_reg_w(pchip, CCCR);
    //DEBUGMSG("-> CAN Control Register: 0x%.4lx\n",(long)tempreg);
    c_can_write_reg_w(pchip, tempreg | (irqs & 0xe), CCCR);
@@ -704,11 +697,10 @@ int c_can_start_chip(struct canchip_t *pchip)
        return -1;
      }
 
-   //   flags = c_can_read_reg_w(pchip, CCCE) | CE_EN;
-   //   c_can_write_reg_w(pchip, flags, CCCE);
-   //
+#ifdef C_CAN_WITH_CCCE
    flags = c_can_read_reg_w(pchip, CCCE) | CE_EN;
    c_can_write_reg_w(pchip, flags, CCCE);
+#endif
 
    DEBUGMSG("-> ok\n");
 #ifdef REGDUMP
@@ -735,8 +727,10 @@ int c_can_stop_chip(struct canchip_t *pchip)
        return -1;
      }
 
+#ifdef C_CAN_WITH_CCCE
    flags = c_can_read_reg_w(pchip, CCCE) & ~CE_EN;
    c_can_write_reg_w(pchip, flags, CCCE);
+#endif
 
    DEBUGMSG("-> ok\n");
    return 0;
@@ -820,8 +814,10 @@ void c_can_registerdump(struct canchip_t *pchip)
          (long)(c_can_read_reg_w( pchip, CCTR)));
    CANMSG("Baud Rate Presc. Register:    0x%.4lx\n",
          (long)(c_can_read_reg_w( pchip, CCBRPE)));
+#ifdef C_CAN_WITH_CCCE
    CANMSG("CAN Enable Register:          0x%.4lx\n",
          (long)(c_can_read_reg_w( pchip, CCCE)));
+#endif
    CANMSG("Transm. Req. 1 Register:      0x%.4lx\n",
          (long)(c_can_read_reg_w( pchip, CCTREQ1)));
    CANMSG("Transm. Req. 2 Register:      0x%.4lx\n",
@@ -884,6 +880,37 @@ void c_can_registerdump(struct canchip_t *pchip)
    CANMSG("------------------------------------\n");
 }
 
+
+void c_can_if1_registerdump(struct canchip_t *pchip)
+{
+   CANMSG("----------------------------------------\n");
+   CANMSG("Error Counting Register:      0x%.4lx\n",
+         (long)(c_can_read_reg_w( pchip, CCEC)));
+   CANMSG("---------C-CAN IF1 Register Dump--------\n");
+   CANMSG("IF1 Command Req. Register:    0x%.4lx\n",
+         (long)(c_can_read_reg_w( pchip, CCIF1CR)));
+   CANMSG("IF1 Command Mask Register:    0x%.4lx\n",
+         (long)(c_can_read_reg_w( pchip, CCIF1CM)));
+   CANMSG("IF1 Mask 1 Register:          0x%.4lx\n",
+         (long)(c_can_read_reg_w( pchip, CCIF1M1)));
+   CANMSG("IF1 Mask 2 Register:          0x%.4lx\n",
+         (long)(c_can_read_reg_w( pchip, CCIF1M2)));
+   CANMSG("IF1 Arbitration 1 Register:   0x%.4lx\n",
+         (long)(c_can_read_reg_w( pchip, CCIF1A1)));
+   CANMSG("IF1 Arbitration 2 Register:   0x%.4lx\n",
+         (long)(c_can_read_reg_w( pchip, CCIF1A2)));
+   CANMSG("IF1 Message Control Register: 0x%.4lx\n",
+         (long)(c_can_read_reg_w( pchip, CCIF1DMC)));
+   CANMSG("IF1 Data A1 Register:         0x%.4lx\n",
+         (long)(c_can_read_reg_w( pchip, CCIF1DA1)));
+   CANMSG("IF1 Data A2 Register:         0x%.4lx\n",
+         (long)(c_can_read_reg_w( pchip, CCIF1DA2)));
+   CANMSG("IF1 Data B1 Register:         0x%.4lx\n",
+         (long)(c_can_read_reg_w( pchip, CCIF1DB1)));
+   CANMSG("IF1 Data B2 Register:         0x%.4lx\n",
+         (long)(c_can_read_reg_w( pchip, CCIF1DB2)));
+}
+
 ///////////////////////////////////////////////////////////////////////
 
 int c_can_register(struct chipspecops_t *chipspecops)
@@ -916,7 +943,13 @@ int c_can_register(struct chipspecops_t *chipspecops)
 int c_can_fill_chipspecops(struct canchip_t *chip)
 {
        chip->chip_type="c_can";
-       chip->max_objects = 32;
+       if(MAX_MSGOBJS >= 32) {
+               chip->max_objects = 32;
+       } else {
+               CANMSG("C_CAN requires 32 message objects per chip,"
+                      " but only %d is compiled maximum\n",MAX_MSGOBJS);
+               chip->max_objects = MAX_MSGOBJS;
+       }
        c_can_register(chip->chipspecops);
        return 0;
 }