int i=0;
DEBUGMSG("Resetting smartcan hardware ...\n");
- outb(0x00,candev->res_addr);
+ can_outb(0x00,candev->res_addr);
while (i < 1000000) {
i++;
- outb(0x01,candev->res_addr);
+ can_outb(0x01,candev->res_addr);
}
- outb(0x00,candev->res_addr);
+ can_outb(0x00,candev->res_addr);
/* Check hardware reset status */
i=0;
- outb(candev->io_addr+iCPU,candev->io_addr);
- while ( (inb(candev->io_addr+1)&0x80) && (i<=15) ) {
+ can_outb(candev->io_addr+iCPU,candev->io_addr);
+ while ( (can_inb(candev->io_addr+1)&0x80) && (i<=15) ) {
udelay(20000);
i++;
}
int smartcan_init_chip_data(struct candevice_t *candev, int chipnr)
{
i82527_fill_chipspecops(candev->chip[chipnr]);
- candev->chip[chipnr]->chip_base_addr=candev->io_addr;
+ candev->chip[chipnr]->chip_base_addr=can_ioport2ioptr(candev->io_addr);
candev->chip[chipnr]->clock = 16000000;
candev->chip[chipnr]->int_cpu_reg = iCPU_DSC;
candev->chip[chipnr]->int_clk_reg = iCLK_SL1;
}
-void smartcan_write_register(unsigned data, unsigned long address)
+void smartcan_write_register(unsigned data, can_ioptr_t address)
{
can_spin_irqflags_t flags;
can_spin_lock_irqsave(&smartcan_port_lock,flags);
- outb(address-smartcan_base,smartcan_base);
- outb(data,smartcan_base+1);
+ can_outb(address-smartcan_base,smartcan_base);
+ can_outb(data,smartcan_base+1);
can_spin_unlock_irqrestore(&smartcan_port_lock,flags);
}
-unsigned smartcan_read_register(unsigned long address)
+unsigned smartcan_read_register(can_ioptr_t address)
{
unsigned ret;
can_spin_irqflags_t flags;
can_spin_lock_irqsave(&smartcan_port_lock,flags);
- outb(address-smartcan_base,smartcan_base);
- ret=inb(smartcan_base+1);
+ can_outb(address-smartcan_base,smartcan_base);
+ ret=can_inb(smartcan_base+1);
can_spin_unlock_irqrestore(&smartcan_port_lock,flags);
return ret;
}