--- /dev/null
+/* pccan.c
+ * Linux CAN-bus device driver.
+ * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
+ * This software is released under the GPL-License.
+ * Version 0.7 6 Aug 2001
+ */
+
+#include <linux/autoconf.h>
+#if defined (CONFIG_MODVERSIONS) && !defined (MODVERSIONS)
+#define MODVERSIONS
+#endif
+
+#if defined (MODVERSIONS)
+#include <linux/modversions.h>
+#endif
+
+#include <linux/ioport.h>
+#include <linux/delay.h>
+#include <asm/irq.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+
+#include "../include/main.h"
+#include "../include/pccan.h"
+#include "../include/i82527.h"
+#include "../include/sja1000.h"
+
+int pccanf_request_io(unsigned long io_addr)
+{
+ if (check_region(io_addr+0x4000,0x20)) {
+ CANMSG("Unable to open port: 0x%lx\n",io_addr+0x4000);
+ return -ENODEV;
+ }
+ else if (check_region(io_addr+0x6000,0x04)) {
+ CANMSG("Unable to open port: 0x%lx\n",io_addr+0x6000);
+ return -ENODEV;
+ }
+ else {
+ request_region(io_addr+0x4000,0x20,DEVICE_NAME);
+ DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", io_addr+0x4000, io_addr+0x4000+0x20-1);
+ request_region(io_addr+0x6000,0x04,DEVICE_NAME);
+ DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", io_addr+0x6000, io_addr+0x6000+0x04-1);
+ }
+ return 0;
+}
+
+int pccand_request_io(unsigned long io_addr)
+{
+ if (pccanf_request_io(io_addr))
+ return -ENODEV;
+
+ if (check_region(io_addr+0x5000,0x20)) {
+ CANMSG("Unable to open port: 0x%lx\n",io_addr+0x5000);
+ return -ENODEV;
+ }
+ else {
+ request_region(io_addr+0x5000,0x20,DEVICE_NAME);
+ DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", io_addr+0x5000, io_addr+0x5000+0x20-1);
+ }
+ return 0;
+}
+
+int pccanq_request_io(unsigned long io_addr)
+{
+ if (pccand_request_io(io_addr))
+ return -ENODEV;
+
+ if (check_region(io_addr+0x2000,0x40)) {
+ CANMSG("Unable to open port: 0x%lx\n",io_addr+0x2000);
+ return -ENODEV;
+ }
+ else if (check_region(io_addr+0x2400,0x40)) {
+ CANMSG("Unable to open port: 0x%lx\n",io_addr+0x2400);
+ return -ENODEV;
+ }
+ else if (check_region(io_addr+0x2800,0x40)) {
+ CANMSG("Unable to open port: 0x%lx\n",io_addr+0x2800);
+ return -ENODEV;
+ }
+ else if (check_region(io_addr+0x2C00,0x40)) {
+ CANMSG("Unable to open port: 0x%lx\n",io_addr+0x2C00);
+ return -ENODEV;
+ }
+ else if (check_region(io_addr+0x3000,0x40)) {
+ CANMSG("Unable to open port: 0x%lx\n",io_addr+0x3000);
+ return -ENODEV;
+ }
+ else if (check_region(io_addr+0x3400,0x40)) {
+ CANMSG("Unable to open port: 0x%lx\n",io_addr+0x3400);
+ return -ENODEV;
+ }
+ else if (check_region(io_addr+0x3800,0x40)) {
+ CANMSG("Unable to open port: 0x%lx\n",io_addr+0x3800);
+ return -ENODEV;
+ }
+ else if (check_region(io_addr+0x3C00,0x40)) {
+ CANMSG("Unable to open port: 0x%lx\n",io_addr+0x3C00);
+ return -ENODEV;
+ }
+ else {
+ request_region(io_addr+0x2000,0x40,DEVICE_NAME);
+ DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", io_addr+0x2000, io_addr+0x2000+0x40-1);
+ request_region(io_addr+0x2400,0x40,DEVICE_NAME);
+ DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", io_addr+0x2400, io_addr+0x2400+0x40-1);
+ request_region(io_addr+0x2800,0x40,DEVICE_NAME);
+ DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", io_addr+0x2800, io_addr+0x2800+0x40-1);
+ request_region(io_addr+0x2C00,0x40,DEVICE_NAME);
+ DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", io_addr+0x2C00, io_addr+0x2C00+0x40-1);
+ request_region(io_addr+0x3000,0x40,DEVICE_NAME);
+ DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", io_addr+0x3000, io_addr+0x3000+0x40-1);
+ request_region(io_addr+0x3400,0x40,DEVICE_NAME);
+ DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", io_addr+0x3400, io_addr+0x3400+0x40-1);
+ request_region(io_addr+0x3800,0x40,DEVICE_NAME);
+ DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", io_addr+0x3800, io_addr+0x3800+0x40-1);
+ request_region(io_addr+0x3C00,0x40,DEVICE_NAME);
+ DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", io_addr+0x3C00, io_addr+0x3C00+0x40-1);
+ }
+
+ return 0;
+}
+
+int pccanf_release_io(unsigned long io_addr)
+{
+ release_region(io_addr+0x4000,0x20);
+ release_region(io_addr+0x6000,0x04);
+
+ return 0;
+}
+
+int pccand_release_io(unsigned long io_addr)
+{
+ pccanf_release_io(io_addr);
+ release_region(io_addr+0x5000,0x20);
+
+ return 0;
+}
+
+int pccanq_release_io(unsigned long io_addr)
+{
+ pccand_release_io(io_addr);
+ release_region(io_addr+0x2000,0x40);
+ release_region(io_addr+0x2400,0x40);
+ release_region(io_addr+0x2800,0x40);
+ release_region(io_addr+0x2C00,0x40);
+ release_region(io_addr+0x3000,0x40);
+ release_region(io_addr+0x3400,0x40);
+ release_region(io_addr+0x3800,0x40);
+ release_region(io_addr+0x3C00,0x40);
+
+ return 0;
+}
+
+int pccanf_reset(int card)
+{
+ int i=0;
+
+ DEBUGMSG("Resetting pccanf/s hardware ...\n");
+ while (i < 1000000) {
+ i++;
+ outb(0x00,candevices_p[card]->res_addr);
+ }
+ outb(0x01,candevices_p[card]->res_addr);
+ outb(0x00,candevices_p[card]->chip[0]->chip_base_addr+SJACR);
+
+ /* Check hardware reset status */
+ i=0;
+ while ( (inb(candevices_p[card]->chip[0]->chip_base_addr+SJACR) & CR_RR)
+ && (i<=15) ) {
+ udelay(20000);
+ i++;
+ }
+ if (i>=15) {
+ CANMSG("Reset status timeout!\n");
+ CANMSG("Please check your hardware.\n");
+ return -ENODEV;
+ }
+ else
+ DEBUGMSG("Chip[0] reset status ok.\n");
+
+ return 0;
+}
+
+int pccand_reset(int card)
+{
+ int i=0,chip_nr=0;
+
+ DEBUGMSG("Resetting pccan-d hardware ...\n");
+ while (i < 1000000) {
+ i++;
+ outb(0x00,candevices_p[card]->res_addr);
+ }
+ outb(0x01,candevices_p[card]->res_addr);
+ outb(0x00,candevices_p[card]->chip[0]->chip_base_addr+SJACR);
+ outb(0x00,candevices_p[card]->chip[1]->chip_base_addr+SJACR);
+
+ /* Check hardware reset status */
+ i=0;
+ for (chip_nr=0; chip_nr<2; chip_nr++) {
+ i=0;
+ while ( (inb(candevices_p[card]->chip[chip_nr]->chip_base_addr +
+ SJACR) & CR_RR) && (i<=15) ) {
+ udelay(20000);
+ i++;
+ }
+ if (i>=15) {
+ CANMSG("Reset status timeout!\n");
+ CANMSG("Please check your hardware.\n");
+ return -ENODEV;
+ }
+ else
+ DEBUGMSG("Chip%d reset status ok.\n",chip_nr);
+ }
+ return 0;
+}
+
+int pccanq_reset(int card)
+{
+ int i=0,chip_nr=0;
+
+ for (i=0; i<4; i++)
+ disable_irq(candevices_p[card]->chip[i]->chip_irq);
+
+ DEBUGMSG("Resetting pccan-q hardware ...\n");
+ while (i < 100000) {
+ i++;
+ outb(0x00,candevices_p[card]->res_addr);
+ }
+ outb_p(0x01,candevices_p[card]->res_addr);
+
+ outb(0x00,candevices_p[card]->chip[2]->chip_base_addr+SJACR);
+ outb(0x00,candevices_p[card]->chip[3]->chip_base_addr+SJACR);
+
+ /* Check hardware reset status */
+ for (chip_nr=0; chip_nr<2; chip_nr++) {
+ i=0;
+ while( (inb(candevices_p[card]->chip[chip_nr]->chip_base_addr +
+ iCPU) & iCPU_RST) && (i<=15) ) {
+ udelay(20000);
+ i++;
+ }
+ if (i>=15) {
+ CANMSG("Reset status timeout!\n");
+ CANMSG("Please check your hardware.\n");
+ return -ENODEV;
+ }
+ else
+ DEBUGMSG("Chip%d reset status ok.\n",chip_nr);
+ }
+ for (chip_nr=2; chip_nr<4; chip_nr++) {
+ i=0;
+ while( (inb(candevices_p[card]->chip[chip_nr]->chip_base_addr +
+ SJACR) & CR_RR) && (i<=15) ) {
+ udelay(20000);
+ i++;
+ }
+ if (i>=15) {
+ CANMSG("Reset status timeout!\n");
+ CANMSG("Please check your hardware.\n");
+ return -ENODEV;
+ }
+ else
+ DEBUGMSG("Chip%d reset status ok.\n",chip_nr);
+ }
+
+ for (i=0; i<4; i++)
+ enable_irq(candevices_p[card]->chip[i]->chip_irq);
+
+ return 0;
+}
+
+int pccan_init_hw_data(int card)
+{
+ candevices_p[card]->res_addr=candevices_p[card]->io_addr+0x6001;
+ candevices_p[card]->flags |= PROGRAMMABLE_IRQ;
+
+ if (!strcmp(candevices_p[card]->hwname,"pccan-q")) {
+ candevices_p[card]->nr_82527_chips=2;
+ candevices_p[card]->nr_sja1000_chips=2;
+ }
+ if (!strcmp(candevices_p[card]->hwname,"pccan-f") |
+ !strcmp(candevices_p[card]->hwname,"pccan-s")) {
+ candevices_p[card]->nr_82527_chips=0;
+ candevices_p[card]->nr_sja1000_chips=1;
+ }
+ if (!strcmp(candevices_p[card]->hwname,"pccan-d")) {
+ candevices_p[card]->nr_82527_chips=0;
+ candevices_p[card]->nr_sja1000_chips=2;
+ }
+
+ return 0;
+}
+
+int pccan_init_chip_data(int card, int chipnr)
+{
+ if (!strcmp(candevices_p[card]->hwname,"pccan-q")) {
+ if (chipnr<2) {
+ candevices_p[card]->chip[chipnr]->chip_type="i82527";
+ candevices_p[card]->chip[chipnr]->flags = SEGMENTED;
+ candevices_p[card]->chip[chipnr]->int_cpu_reg=iCPU_DSC;
+ candevices_p[card]->chip[chipnr]->int_clk_reg=iCLK_SL1;
+ candevices_p[card]->chip[chipnr]->int_bus_reg=iBUS_CBY;
+ candevices_p[card]->chip[chipnr]->sja_cdr_reg = 0;
+ candevices_p[card]->chip[chipnr]->sja_ocr_reg = 0;
+ }
+ else{
+ candevices_p[card]->chip[chipnr]->chip_type="sja1000";
+ candevices_p[card]->chip[chipnr]->flags = 0;
+ candevices_p[card]->chip[chipnr]->int_cpu_reg = 0;
+ candevices_p[card]->chip[chipnr]->int_clk_reg = 0;
+ candevices_p[card]->chip[chipnr]->int_bus_reg = 0;
+ candevices_p[card]->chip[chipnr]->sja_cdr_reg =
+ CDR_CLK_OFF;
+ candevices_p[card]->chip[chipnr]->sja_ocr_reg =
+ OCR_MODE_NORMAL | OCR_TX0_LH;
+ }
+ candevices_p[card]->chip[chipnr]->chip_base_addr=0x1000*chipnr+0x2000+candevices_p[card]->io_addr;
+ }
+ else {
+ candevices_p[card]->chip[chipnr]->chip_type="sja1000";
+ candevices_p[card]->chip[chipnr]->chip_base_addr=0x1000*chipnr+0x4000+candevices_p[card]->io_addr;
+ candevices_p[card]->chip[chipnr]->flags = 0;
+ candevices_p[card]->chip[chipnr]->int_cpu_reg = 0;
+ candevices_p[card]->chip[chipnr]->int_clk_reg = 0;
+ candevices_p[card]->chip[chipnr]->int_bus_reg = 0;
+ candevices_p[card]->chip[chipnr]->sja_cdr_reg = CDR_CLK_OFF;
+ candevices_p[card]->chip[chipnr]->sja_ocr_reg =
+ OCR_MODE_NORMAL | OCR_TX0_LH;
+ }
+
+ candevices_p[card]->chip[chipnr]->clock = 16000000;
+
+ return 0;
+}
+
+int pccan_init_obj_data(int chipnr, int objnr)
+{
+ if (!strcmp(chips_p[chipnr]->chip_type,"sja1000")) {
+ chips_p[chipnr]->msgobj[objnr]->obj_base_addr=chips_p[chipnr]->chip_base_addr;
+ chips_p[chipnr]->msgobj[objnr]->flags=0;
+ }
+ else {
+ chips_p[chipnr]->msgobj[objnr]->obj_base_addr=chips_p[chipnr]->chip_base_addr+(objnr+1)*0x10+(int)((objnr+1)/4)*0x3c0;
+ chips_p[chipnr]->msgobj[objnr]->flags=0;
+ }
+
+ return 0;
+}
+
+int pccan_program_irq(int card)
+{
+ #define IRQ9 0x01
+ #define IRQ3 0x02
+ #define IRQ5 0x03
+
+ unsigned char irq_reg_value=0;
+ int i;
+
+ for (i=0; i<4; i++) {
+ switch (candevices_p[card]->chip[i]->chip_irq) {
+ case 0: {
+ break;
+ }
+ case 3: {
+ irq_reg_value |= (IRQ3<<(i*2));
+ break;
+ }
+ case 5: {
+ irq_reg_value |= (IRQ5<<(i*2));
+ break;
+ }
+ case 9: {
+ irq_reg_value |= (IRQ9<<(i*2));
+ break;
+ }
+ default: {
+ CANMSG("Supplied interrupt is not supported by the hardware\n");
+ return -ENODEV;
+ }
+ }
+ }
+ outb(irq_reg_value,0x6000+candevices_p[card]->io_addr);
+ DEBUGMSG("Configured pccan hardware interrupts\n");
+ outb(0x80,0x6000+candevices_p[card]->io_addr+0x02);
+ DEBUGMSG("Selected pccan on-board 16 MHz oscillator\n");
+
+ return 0;
+}
+
+inline void pccan_write_register(unsigned char data, unsigned long address)
+{
+ outb(data,address);
+}
+
+unsigned pccan_read_register(unsigned long address)
+{
+ return inb(address);
+}
+
+int pccanf_register(struct hwspecops_t *hwspecops)
+{
+ hwspecops->request_io = pccanf_request_io;
+ hwspecops->release_io = pccanf_release_io;
+ hwspecops->reset = pccanf_reset;
+ hwspecops->init_hw_data = pccan_init_hw_data;
+ hwspecops->init_chip_data = pccan_init_chip_data;
+ hwspecops->init_obj_data = pccan_init_obj_data;
+ hwspecops->write_register = pccan_write_register;
+ hwspecops->read_register = pccan_read_register;
+ hwspecops->program_irq = pccan_program_irq;
+ return 0;
+}
+
+
+int pccand_register(struct hwspecops_t *hwspecops)
+{
+ hwspecops->request_io = pccand_request_io;
+ hwspecops->release_io = pccand_release_io;
+ hwspecops->reset = pccand_reset;
+ hwspecops->init_hw_data = pccan_init_hw_data;
+ hwspecops->init_chip_data = pccan_init_chip_data;
+ hwspecops->init_obj_data = pccan_init_obj_data;
+ hwspecops->write_register = pccan_write_register;
+ hwspecops->read_register = pccan_read_register;
+ hwspecops->program_irq = pccan_program_irq;
+ return 0;
+}
+
+
+int pccanq_register(struct hwspecops_t *hwspecops)
+{
+ hwspecops->request_io = pccanq_request_io;
+ hwspecops->release_io = pccanq_release_io;
+ hwspecops->reset = pccanq_reset;
+ hwspecops->init_hw_data = pccan_init_hw_data;
+ hwspecops->init_chip_data = pccan_init_chip_data;
+ hwspecops->init_obj_data = pccan_init_obj_data;
+ hwspecops->write_register = pccan_write_register;
+ hwspecops->read_register = pccan_read_register;
+ hwspecops->program_irq = pccan_program_irq;
+ return 0;
+}
projects / lincan.git / blobdiff