LinCAN sources go through big white-space cleanup.

[lincan.git] / lincan / src / esdpci200.c

diff --git a/lincan/src/esdpci200.c b/lincan/src/esdpci200.c
index 292ae9071b6820433ac219de25afd54361ca04b0..09c44fafdc7bcbd7d50fd8e53acf6b903a2eb364 100644 (file)
--- a/lincan/src/esdpci200.c
+++ b/lincan/src/esdpci200.c
@@ -59,14 +59,14 @@
 #define PLX9052_CNTRL  0x50    /* control register, for software reset */
 
 /* The ESD PCI/200 uses (per default) just LINTi1 (Local Interrupt 1)
- * on the PLX. This means that both CAN channels' (SJA1000's) /INT pins 
+ * on the PLX. This means that both CAN channels' (SJA1000's) /INT pins
  * are OR'ed to the LINTi1 pin (actually ANDed in the 74HC08 since both
  * the SJA1000's /INT pins and the LINTi1 pin are active low).
  *
  * The board does have an option to route the 2nd channel to LINTi2,
  * apparently just one or two resistors need to be added.
  *
- * LINTi2 is floating per default, so don't set its interrupt enable flag 
+ * LINTi2 is floating per default, so don't set its interrupt enable flag
  * 'PLX9052_INTCSR_LI2EN', it'll just interrupt all the time.
  */
 #define PLX9052_INTCSR_LI1EN 0x00000001 /* Local Interrupt 1 enable */
@@ -81,7 +81,7 @@
 
 // Standard value: Pushpull  (OCTP1|OCTN1|OCPOL1|OCTP0|OCTN0|OCM1)
 #define ESDPCI200_OCR_DEFAULT_STD 0xFA
-/* Setting the OCR register to 0xFA is a good idea. 
+/* Setting the OCR register to 0xFA is a good idea.
    This means  normal output mode , push-pull and the correct polarity. */
 
 
@@ -113,7 +113,7 @@ void esdpci200_connect_irq(struct candevice_t *candev)
         /* enable interrupts for the SJA1000's, enable PCI interrupts */
        outl(   PLX9052_INTCSR_LI1EN | PLX9052_INTCSR_PIEN,
                candev->res_addr+PLX9052_INTCSR);
-       DEBUGMSG("enabled interrupts on the PLX\n"); 
+       DEBUGMSG("enabled interrupts on the PLX\n");
 }
 
 int esdpci200_irq_handler(int irq, struct canchip_t *chip)
@@ -126,8 +126,8 @@ int esdpci200_irq_handler(int irq, struct canchip_t *chip)
        //DEBUGMSG("Starting to handle an IRQ\n");
        it_reg = inl(candev->res_addr+PLX9052_INTCSR);
        rmb();
-       if((it_reg & (PLX9052_INTCSR_LI1S | PLX9052_INTCSR_LI1EN) ) 
-               == (PLX9052_INTCSR_LI1S | PLX9052_INTCSR_LI1EN) ) 
+       if((it_reg & (PLX9052_INTCSR_LI1S | PLX9052_INTCSR_LI1EN) )
+               == (PLX9052_INTCSR_LI1S | PLX9052_INTCSR_LI1EN) )
        {       /*interrupt enabled and active */
                int chipnum;
                for(chipnum=0; chipnum < candev->nr_sja1000_chips; chipnum++)
@@ -144,7 +144,7 @@ int esdpci200_irq_handler(int irq, struct canchip_t *chip)
                        }
                }
                if( retcode != CANCHIP_IRQ_HANDLED )
-               {/* None of the chips felt they were responsible for this IRQ... 
+               {/* None of the chips felt they were responsible for this IRQ...
                    so it appears we have problems with the IRQ */
                        it_reg &= ~(PLX9052_INTCSR_LI1EN);
                        //Either we have a problem with IRQ malfunctions, or our IRQ is shared with some other device.
@@ -190,7 +190,7 @@ int esdpci200_request_io(struct candevice_t *candev)
        /*MEM window for SJA1000 chips*/
        bar2_addr = pci_resource_start(pcidev,2);
        candev->io_addr = bar2_addr;
-       if( ! (remap_addr=ioremap(bar2_addr, 
+       if( ! (remap_addr=ioremap(bar2_addr,
                pci_resource_len(pcidev,2)))) /*MEM window for SJA1000 chips*/
        {
                CANMSG("Unable to access I/O memory at: 0x%lx\n", (unsigned long)bar2_addr);
@@ -198,7 +198,7 @@ int esdpci200_request_io(struct candevice_t *candev)
        }
 
        can_base_addr_fixup(candev, remap_addr);
-       CANMSG("esdpci200_sja IO-memory: 0x%lx - 0x%lx (VMA 0x%lx)\n", 
+       CANMSG("esdpci200_sja IO-memory: 0x%lx - 0x%lx (VMA 0x%lx)\n",
                (unsigned long) bar2_addr,
                (unsigned long) (bar2_addr + pci_resource_len(pcidev,2) - 1),
                (long) remap_addr);
@@ -278,15 +278,15 @@ int esdpci200_reset(struct candevice_t *candev)
                esdpci200_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
 
                esdpci200_write_register(0, chip->chip_base_addr+SJAIER);
-               
+
                esdpci200_read_register(chip->chip_base_addr+SJAIR);
        }
-       
+
 
        esdpci200_connect_irq(candev);
 
        return 0;
-}      
+}
 
 int esdpci200_init_hw_data(struct candevice_t *candev)
 {
@@ -330,7 +330,7 @@ int esdpci200_init_hw_data(struct candevice_t *candev)
 
        /* Physical address of SJA1000 window, stored for debugging only */
        candev->io_addr = pci_resource_start(pcidev,2);
-       
+
        candev->aux_base_addr=NULL; /* mapped dynamically in esdpci200_request_io() */
        candev->dev_base_addr=NULL; /* mapped dynamically in esdpci200_request_io() */
        /*candev->flags |= CANDEV_PROGRAMMABLE_IRQ;*/
@@ -352,7 +352,7 @@ int esdpci200_init_chip_data(struct candevice_t *candev, int chipnr)
 {
 
        if(candev->sysdevptr.pcidev==NULL)
-               return -ENODEV; 
+               return -ENODEV;
 
        CANMSG("initializing esdpci200 chip operations\n");
 
@@ -372,13 +372,13 @@ int esdpci200_init_chip_data(struct candevice_t *candev, int chipnr)
        candev->chip[chipnr]->chip_irq=candev->sysdevptr.pcidev->irq;
        candev->chip[chipnr]->flags |= CHIP_IRQ_PCI;
        if( chipnr > 0 ) /* only one IRQ used for both channels.
-                           CHIP_IRQ_CUSTOM req'd for RTAI, since 
-                           registering two handlers for the same IRQ 
+                           CHIP_IRQ_CUSTOM req'd for RTAI, since
+                           registering two handlers for the same IRQ
                            returns an error */
                candev->chip[chipnr]->flags |= CHIP_IRQ_CUSTOM;
 
        return 0;
-}      
+}
 
 int esdpci200_init_obj_data(struct canchip_t *chip, int objnr)
 {