/* i82527.c
* Linux CAN-bus device driver.
* Written by Arnaud Westenberg email:arnaud@wanadoo.nl
+ * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
+ * email:pisa@cmp.felk.cvut.cz
* This software is released under the GPL-License.
- * Version 0.7 6 Aug 2001
+ * Version lincan-0.3 17 Jun 2004
*/
-#define __NO_VERSION__
-#include <linux/module.h>
-
-#include <linux/autoconf.h>
-#if defined (CONFIG_MODVERSIONS) && !defined (MODVERSIONS)
-#define MODVERSIONS
-#endif
-
-#if defined (MODVERSIONS)
-#include <linux/modversions.h>
-#endif
-
-#include <linux/fs.h>
-
+#include "../include/can.h"
+#include "../include/can_sysdep.h"
#include "../include/main.h"
#include "../include/i82527.h"
+void i82527_irq_rtr_handler(struct canchip_t *chip, struct msgobj_t *obj,
+ struct rtr_id *rtr_search, unsigned long message_id);
+
+
extern int stdmask;
extern int extmask;
extern int mo15mask;
-int i82527_enable_configuration(struct chip_t *chip)
+/* helper functions for segmented cards read and write configuration and status registers
+ above 0xf offset */
+
+void i82527_seg_write_reg(const struct canchip_t *chip, unsigned char data, unsigned address)
+{
+ if((address > 0xf) && (chip->flags & CHIP_SEGMENTED))
+ canobj_write_reg(chip, chip->msgobj[(address>>4)-1],data, address & 0xf);
+ else
+ can_write_reg(chip, data, address);
+}
+
+unsigned i82527_seg_read_reg(const struct canchip_t *chip, unsigned address)
+{
+ if((address > 0xf) && (chip->flags & CHIP_SEGMENTED))
+ return canobj_read_reg(chip, chip->msgobj[(address>>4)-1], address & 0xf);
+ else
+ return can_read_reg(chip, address);
+}
+
+int i82527_enable_configuration(struct canchip_t *chip)
{
unsigned short flags=0;
return 0;
}
-int i82527_disable_configuration(struct chip_t *chip)
+int i82527_disable_configuration(struct canchip_t *chip)
{
unsigned short flags=0;
return 0;
}
-int i82527_chip_config(struct chip_t *chip)
+int i82527_chip_config(struct canchip_t *chip)
{
can_write_reg(chip,chip->int_cpu_reg,iCPU); // Configure cpu interface
can_write_reg(chip,(iCTL_CCE|iCTL_INI),iCTL); // Enable configuration
- can_write_reg(chip,chip->int_clk_reg,iCLK); // Set clock out slew rates
- can_write_reg(chip,chip->int_bus_reg,iBUS); /* Bus configuration */
+ i82527_seg_write_reg(chip,chip->int_clk_reg,iCLK); // Set clock out slew rates
+ i82527_seg_write_reg(chip,chip->int_bus_reg,iBUS); /* Bus configuration */
can_write_reg(chip,0x00,iSTAT); /* Clear error status register */
/* Check if we can at least read back some arbitrary data from the
* card. If we can not, the card is not properly configured!
*/
- can_write_reg(chip,0x25,MSG_OFFSET(1)+iMSGDAT1);
- can_write_reg(chip,0x52,MSG_OFFSET(2)+iMSGDAT3);
- can_write_reg(chip,0xc3,MSG_OFFSET(10)+iMSGDAT6);
- if ( (can_read_reg(chip,MSG_OFFSET(1)+iMSGDAT1) != 0x25) ||
- (can_read_reg(chip,MSG_OFFSET(2)+iMSGDAT3) != 0x52) ||
- (can_read_reg(chip,MSG_OFFSET(10)+iMSGDAT6) != 0xc3) ) {
+ canobj_write_reg(chip,chip->msgobj[1],0x25,iMSGDAT1);
+ canobj_write_reg(chip,chip->msgobj[2],0x52,iMSGDAT3);
+ canobj_write_reg(chip,chip->msgobj[10],0xc3,iMSGDAT6);
+ if ( (canobj_read_reg(chip,chip->msgobj[1],iMSGDAT1) != 0x25) ||
+ (canobj_read_reg(chip,chip->msgobj[2],iMSGDAT3) != 0x52) ||
+ (canobj_read_reg(chip,chip->msgobj[10],iMSGDAT6) != 0xc3) ) {
CANMSG("Could not read back from the hardware.\n");
CANMSG("This probably means that your hardware is not correctly configured!\n");
return -1;
else
DEBUGMSG("Could read back, hardware is probably configured correctly\n");
- if (baudrate == 0)
- baudrate=1000;
+ if (chip->baudrate == 0)
+ chip->baudrate=1000000;
- if (i82527_baud_rate(chip,baudrate*1000,chip->clock,0,75,0)) {
+ if (i82527_baud_rate(chip,chip->baudrate,chip->clock,0,75,0)) {
CANMSG("Error configuring baud rate\n");
return -ENODEV;
}
CANMSG("Error clearing message objects\n");
return -ENODEV;
}
- if (i82527_config_irqs(chip,0x0a)) {
+ if (i82527_config_irqs(chip,iCTL_IE|iCTL_EIE)) { /* has been 0x0a */
CANMSG("Error configuring interrupts\n");
return -ENODEV;
}
* param sampl_pt sample point in % (0-100) sets (TSEG1+2)/(TSEG1+TSEG2+3) ratio
* param flags fields BTR1_SAM, OCMODE, OCPOL, OCTP, OCTN, CLK_OFF, CBP
*/
-int i82527_baud_rate(struct chip_t *chip, int rate, int clock, int sjw,
+int i82527_baud_rate(struct canchip_t *chip, int rate, int clock, int sjw,
int sampl_pt, int flags)
{
int best_error = 1000000000, error;
if (i82527_enable_configuration(chip))
return -ENODEV;
- clock /=2;
+ if(chip->int_cpu_reg & iCPU_DSC)
+ clock /=2;
/* tseg even = round down, odd = round up */
for (tseg=(0+0+2)*2; tseg<=(MAX_TSEG2+MAX_TSEG1+2)*2+1; tseg++) {
(100*(best_tseg-tseg2)/(best_tseg+1)));
- can_write_reg(chip, sjw<<6 | best_brp, iBT0);
+ i82527_seg_write_reg(chip, sjw<<6 | best_brp, iBT0);
can_write_reg(chip, ((flags & BTR1_SAM) != 0)<<7 | tseg2<<4 | tseg1,
iBT1);
DEBUGMSG("Writing 0x%x to iBT0\n",(sjw<<6 | best_brp));
return 0;
}
-int i82527_standard_mask(struct chip_t *chip, unsigned short code, unsigned short mask)
+int i82527_standard_mask(struct canchip_t *chip, unsigned short code, unsigned short mask)
{
unsigned char mask0, mask1;
return 0;
}
-int i82527_extended_mask(struct chip_t *chip, unsigned long code, unsigned long mask)
+int i82527_extended_mask(struct canchip_t *chip, unsigned long code, unsigned long mask)
{
unsigned char mask0, mask1, mask2, mask3;
return 0;
}
-int i82527_message15_mask(struct chip_t *chip, unsigned long code, unsigned long mask)
+int i82527_message15_mask(struct canchip_t *chip, unsigned long code, unsigned long mask)
{
unsigned char mask0, mask1, mask2, mask3;
}
-int i82527_clear_objects(struct chip_t *chip)
+int i82527_clear_objects(struct canchip_t *chip)
{
int i=0,id=0,data=0;
+ struct msgobj_t *obj;
DEBUGMSG("Cleared all message objects on chip\n");
for (i=1; i<=15; i++) {
- can_write_reg(chip,(INTPD_RES|RXIE_RES|TXIE_RES|MVAL_RES) ,
- MSG_OFFSET(i)+iMSGCTL0);
- can_write_reg(chip,(NEWD_RES|MLST_RES|TXRQ_RES|RMPD_RES) ,
- MSG_OFFSET(i)+iMSGCTL1);
+ obj=chip->msgobj[i];
+ canobj_write_reg(chip,obj,(INTPD_RES|RXIE_RES|TXIE_RES|MVAL_RES),iMSGCTL0);
+ canobj_write_reg(chip,obj,(NEWD_RES|MLST_RES|TXRQ_RES|RMPD_RES), iMSGCTL1);
for (data=0x07; data<0x0f; data++)
- can_write_reg(chip,0x00,MSG_OFFSET(i)+data);
+ canobj_write_reg(chip,obj,0x00,data);
for (id=2; id<6; id++) {
- can_write_reg(chip,0x00,MSG_OFFSET(i)+id);
+ canobj_write_reg(chip,obj,0x00,id);
}
if (extended==0) {
- can_write_reg(chip,0x00,MSG_OFFSET(i)+iMSGCFG);
+ canobj_write_reg(chip,obj,0x00,iMSGCFG);
}
else {
- can_write_reg(chip,MCFG_XTD,MSG_OFFSET(i)+iMSGCFG);
+ canobj_write_reg(chip,obj,MCFG_XTD,iMSGCFG);
}
}
if (extended==0)
return 0;
}
-int i82527_config_irqs(struct chip_t *chip, short irqs)
+int i82527_config_irqs(struct canchip_t *chip, short irqs)
{
can_write_reg(chip,irqs,iCTL);
DEBUGMSG("Configured hardware interrupt delivery\n");
return 0;
}
-int i82527_pre_read_config(struct chip_t *chip, struct msgobj_t *obj)
+int i82527_pre_read_config(struct canchip_t *chip, struct msgobj_t *obj)
{
- if (extended) {
- can_write_reg(chip,MCFG_XTD,MSG_OFFSET(obj->object)+iMSGCFG);
- }
- else {
- can_write_reg(chip,0x00,MSG_OFFSET(obj->object)+iMSGCFG);
+ unsigned long id=obj->rx_preconfig_id;
+
+ can_msgobj_set_fl(obj,RX_MODE);
+
+ if (extended || can_msgobj_test_fl(obj,RX_MODE_EXT)) {
+ id<<=3;
+ canobj_write_reg(chip,obj,id,iMSGID3);
+ canobj_write_reg(chip,obj,id>>8,iMSGID2);
+ canobj_write_reg(chip,obj,id>>16,iMSGID1);
+ canobj_write_reg(chip,obj,id>>24,iMSGID0);
+ canobj_write_reg(chip,obj,MCFG_XTD,iMSGCFG);
+ } else {
+ id<<=5;
+ canobj_write_reg(chip,obj,id,iMSGID1);
+ canobj_write_reg(chip,obj,id>>8,iMSGID0);
+ canobj_write_reg(chip,obj,0x00,iMSGCFG);
}
- can_write_reg(chip ,(NEWD_RES|MLST_RES|TXRQ_RES|RMPD_RES),
- MSG_OFFSET(obj->object)+iMSGCTL1);
- can_write_reg(chip ,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),
- MSG_OFFSET(obj->object)+iMSGCTL0);
-
+
+ canobj_write_reg(chip,obj,(NEWD_RES|MLST_RES|TXRQ_RES|RMPD_RES), iMSGCTL1);
+ canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0);
+
+ DEBUGMSG("i82527_pre_read_config: configured obj at 0x%08lx\n",obj->obj_base_addr);
+
return 0;
}
-int i82527_pre_write_config(struct chip_t *chip, struct msgobj_t *obj,
+int i82527_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj,
struct canmsg_t *msg)
{
int i=0,id0=0,id1=0,id2=0,id3=0;
+ int len;
+
+ len = msg->length;
+ if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
- can_write_reg(chip,(RMPD_RES|TXRQ_RES|CPUU_SET|NEWD_RES),
- MSG_OFFSET(obj->object)+iMSGCTL1);
- can_write_reg(chip,(MVAL_SET|TXIE_SET|RXIE_RES|INTPD_RES),
- MSG_OFFSET(obj->object)+iMSGCTL0);
- if (extended) {
- can_write_reg(chip,(msg->length<<4)+(MCFG_DIR|MCFG_XTD),
- MSG_OFFSET(obj->object)+iMSGCFG);
- }
- else {
- can_write_reg(chip,(msg->length<<4)+MCFG_DIR,
- MSG_OFFSET(obj->object)+iMSGCFG);
- }
- if (extended) {
+ can_msgobj_clear_fl(obj,RX_MODE);
+
+ canobj_write_reg(chip,obj,(MVAL_SET|TXIE_SET|RXIE_RES|INTPD_RES),iMSGCTL0);
+ canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|CPUU_SET|NEWD_RES),iMSGCTL1);
+
+ if (extended || (msg->flags&MSG_EXT)) {
+ canobj_write_reg(chip,obj,(len<<4)|(MCFG_DIR|MCFG_XTD),iMSGCFG);
id0 = (unsigned char) (msg->id<<3);
id1 = (unsigned char) (msg->id>>5);
id2 = (unsigned char) (msg->id>>13);
id3 = (unsigned char) (msg->id>>21);
- can_write_reg(chip,id0,MSG_OFFSET(obj->object)+iMSGID3);
- can_write_reg(chip,id1,MSG_OFFSET(obj->object)+iMSGID2);
- can_write_reg(chip,id2,MSG_OFFSET(obj->object)+iMSGID1);
- can_write_reg(chip,id3,MSG_OFFSET(obj->object)+iMSGID0);
+ canobj_write_reg(chip,obj,id0,iMSGID3);
+ canobj_write_reg(chip,obj,id1,iMSGID2);
+ canobj_write_reg(chip,obj,id2,iMSGID1);
+ canobj_write_reg(chip,obj,id3,iMSGID0);
}
else {
+ canobj_write_reg(chip,obj,(len<<4)|MCFG_DIR,iMSGCFG);
id1 = (unsigned char) (msg->id<<5);
id0 = (unsigned char) (msg->id>>3);
- can_write_reg(chip,id1,MSG_OFFSET(obj->object)+iMSGID1);
- can_write_reg(chip,id0,MSG_OFFSET(obj->object)+iMSGID0);
+ canobj_write_reg(chip,obj,id1,iMSGID1);
+ canobj_write_reg(chip,obj,id0,iMSGID0);
}
- can_write_reg(chip,0xfa,MSG_OFFSET(obj->object)+iMSGCTL1);
- for (i=0; i<msg->length; i++) {
- can_write_reg(chip,msg->data[i],MSG_OFFSET(obj->object)+
- iMSGDAT0+i);
+ canobj_write_reg(chip,obj,RMPD_UNC|TXRQ_UNC|CPUU_SET|NEWD_SET,iMSGCTL1);
+ for (i=0; i<len; i++) {
+ canobj_write_reg(chip,obj,msg->data[i],iMSGDAT0+i);
}
return 0;
}
-int i82527_send_msg(struct chip_t *chip, struct msgobj_t *obj,
+int i82527_send_msg(struct canchip_t *chip, struct msgobj_t *obj,
struct canmsg_t *msg)
{
+ canobj_write_reg(chip,obj,(MVAL_SET|TXIE_SET|RXIE_RES|INTPD_RES),iMSGCTL0);
+
if (msg->flags & MSG_RTR) {
- can_write_reg(chip,(RMPD_RES|TXRQ_RES|CPUU_RES|NEWD_SET),
- MSG_OFFSET(obj->object)+iMSGCTL1);
+ canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|CPUU_RES|NEWD_SET),iMSGCTL1);
}
else {
- can_write_reg(chip,(RMPD_RES|TXRQ_SET|CPUU_RES|NEWD_SET),
- MSG_OFFSET(obj->object)+iMSGCTL1);
+ canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_SET|CPUU_RES|NEWD_SET),iMSGCTL1);
}
return 0;
}
-int i82527_check_tx_stat(struct chip_t *chip)
+int i82527_check_tx_stat(struct canchip_t *chip)
{
if (can_read_reg(chip,iSTAT) & iSTAT_TXOK) {
can_write_reg(chip,0x0,iSTAT);
}
}
-int i82527_remote_request(struct chip_t *chip, struct msgobj_t *obj)
+int i82527_remote_request(struct canchip_t *chip, struct msgobj_t *obj)
{
- can_write_reg(chip, (MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),
- MSG_OFFSET(obj->object)+iMSGCTL0);
- can_write_reg(chip, (RMPD_RES|TXRQ_SET|MLST_RES|NEWD_RES),
- MSG_OFFSET(obj->object)+iMSGCTL1);
+ canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0);
+ canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_SET|MLST_RES|NEWD_RES),iMSGCTL1);
return 0;
}
-int i82527_set_btregs(struct chip_t *chip, unsigned short btr0,
+int i82527_set_btregs(struct canchip_t *chip, unsigned short btr0,
unsigned short btr1)
{
if (i82527_enable_configuration(chip))
return -ENODEV;
- can_write_reg(chip, btr0, iBT0);
- can_write_reg(chip, btr1, iBT1);
+ i82527_seg_write_reg(chip, btr0, iBT0);
+ i82527_seg_write_reg(chip, btr1, iBT1);
i82527_disable_configuration(chip);
return 0;
}
-int i82527_start_chip(struct chip_t *chip)
+int i82527_start_chip(struct canchip_t *chip)
{
unsigned short flags = 0;
return 0;
}
-int i82527_stop_chip(struct chip_t *chip)
+int i82527_stop_chip(struct canchip_t *chip)
{
unsigned short flags = 0;
return 0;
}
+int i82527_attach_to_chip(struct canchip_t *chip)
+{
+ return 0;
+}
+
+int i82527_release_chip(struct canchip_t *chip)
+{
+ i82527_stop_chip(chip);
+ can_write_reg(chip, (iCTL_CCE|iCTL_INI), iCTL);
+
+ return 0;
+}
+
+static inline
+void i82527_irq_write_handler(struct canchip_t *chip, struct msgobj_t *obj)
+{
+ int cmd;
+
+ canobj_write_reg(chip,obj,(MVAL_RES|TXIE_RES|RXIE_RES|INTPD_RES),iMSGCTL0);
+
+ if(obj->tx_slot){
+ /* Do local transmitted message distribution if enabled */
+ if (processlocal){
+ /* fill CAN message timestamp */
+ can_filltimestamp(&obj->tx_slot->msg.timestamp);
+
+ obj->tx_slot->msg.flags |= MSG_LOCAL;
+ canque_filter_msg2edges(obj->qends, &obj->tx_slot->msg);
+ }
+ /* Free transmitted slot */
+ canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
+ obj->tx_slot=NULL;
+ }
+
+ cmd=canque_test_outslot(obj->qends, &obj->tx_qedge, &obj->tx_slot);
+ if(cmd<0)
+ return;
+
+ if (chip->chipspecops->pre_write_config(chip, obj, &obj->tx_slot->msg)) {
+ obj->ret = -1;
+ canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_PREP);
+ canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
+ obj->tx_slot=NULL;
+ return;
+ }
+ if (chip->chipspecops->send_msg(chip, obj, &obj->tx_slot->msg)) {
+ obj->ret = -1;
+ canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_SEND);
+ canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
+ obj->tx_slot=NULL;
+ return;
+ }
+ return;
+}
+
+static inline
+void i82527_irq_read_handler(struct canchip_t *chip, struct msgobj_t *obj, int objnum)
+{
+ int i;
+ unsigned long message_id;
+ int msgcfg, msgctl1;
+
+ msgctl1=canobj_read_reg(chip,obj,iMSGCTL1);
+ if(msgctl1 & NEWD_RES)
+ return;
+
+ do {
+ if(objnum != 14) {
+ canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|MLST_UNC|NEWD_RES),iMSGCTL1);
+ canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0);
+ }
+
+ msgcfg = canobj_read_reg(chip,obj,iMSGCFG);
+
+ if (msgcfg&MCFG_XTD) {
+ message_id =canobj_read_reg(chip,obj,iMSGID3);
+ message_id|=canobj_read_reg(chip,obj,iMSGID2)<<8;
+ message_id|=canobj_read_reg(chip,obj,iMSGID1)<<16;
+ message_id|=canobj_read_reg(chip,obj,iMSGID0)<<24;
+ message_id>>=3;
+ obj->rx_msg.flags = MSG_EXT;
+
+ }
+ else {
+ message_id =canobj_read_reg(chip,obj,iMSGID1);
+ message_id|=canobj_read_reg(chip,obj,iMSGID0)<<8;
+ message_id>>=5;
+ obj->rx_msg.flags = 0;
+ }
+
+ obj->rx_msg.length = (msgcfg >> 4) & 0xf;
+ if(obj->rx_msg.length > CAN_MSG_LENGTH) obj->rx_msg.length = CAN_MSG_LENGTH;
+
+ obj->rx_msg.id = message_id;
+
+ for (i=0; i < obj->rx_msg.length; i++)
+ obj->rx_msg.data[i] = canobj_read_reg(chip,obj,iMSGDAT0+i);
+
+
+ if(objnum != 14) {
+ /* if NEWD is set after data read, then read data are likely inconsistent */
+ msgctl1=canobj_read_reg(chip,obj,iMSGCTL1);
+ if(msgctl1 & NEWD_SET) {
+ CANMSG("i82527_irq_read_handler: object %d data overwritten\n",objnum);
+ continue;
+ }
+ }
+ else {
+ /* this object is special and data are queued in the shadow register */
+ canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0);
+ canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|MLST_UNC|NEWD_RES),iMSGCTL1);
+ msgctl1=canobj_read_reg(chip,obj,iMSGCTL1);
+ }
+
+
+ /* fill CAN message timestamp */
+ can_filltimestamp(&obj->rx_msg.timestamp);
+
+ canque_filter_msg2edges(obj->qends, &obj->rx_msg);
+
+ if (msgctl1 & NEWD_SET)
+ continue;
+
+ if (msgctl1 & MLST_SET) {
+ canobj_write_reg(chip,obj,(RMPD_UNC|TXRQ_UNC|MLST_RES|NEWD_UNC),iMSGCTL1);
+ CANMSG("i82527_irq_read_handler: object %d message lost\n",objnum);
+ }
+
+ return;
+
+ } while(1);
+}
+
+/*
+ if (msgcfg&MCFG_XTD) {
+ message_id =canobj_read_reg(chip,obj,iMSGID3);
+ message_id|=canobj_read_reg(chip,obj,iMSGID2)<<8;
+ message_id|=canobj_read_reg(chip,obj,iMSGID1)<<16;
+ message_id|=canobj_read_reg(chip,obj,iMSGID0)<<24;
+ message_id>>=3;
+ }
+ else {
+ message_id =canobj_read_reg(chip,obj,iMSGID1);
+ message_id|=canobj_read_reg(chip,obj,iMSGID0)<<8;
+ message_id>>=5;
+ }
+
+ can_spin_lock(&hardware_p->rtr_lock);
+ rtr_search=hardware_p->rtr_queue;
+ while (rtr_search != NULL) {
+ if (rtr_search->id == message_id)
+ break;
+ rtr_search=rtr_search->next;
+ }
+ can_spin_unlock(&hardware_p->rtr_lock);
+ if ((rtr_search!=NULL) && (rtr_search->id==message_id))
+ i82527_irq_rtr_handler(chip, obj, rtr_search, message_id);
+ else
+ i82527_irq_read_handler(chip, obj, message_id);
+*/
+
+
+static inline
+void i82527_irq_update_filter(struct canchip_t *chip, struct msgobj_t *obj)
+{
+ struct canfilt_t filt;
+
+ if(canqueue_ends_filt_conjuction(obj->qends, &filt)) {
+ obj->rx_preconfig_id=filt.id;
+ canobj_write_reg(chip,obj,(MVAL_RES|TXIE_RES|RXIE_RES|INTPD_RES),iMSGCTL0);
+ if(obj->object == 15) {
+ i82527_message15_mask(chip,filt.id,filt.mask);
+ }
+ if (filt.flags&MSG_EXT)
+ can_msgobj_set_fl(obj,RX_MODE_EXT);
+ else
+ can_msgobj_clear_fl(obj,RX_MODE_EXT);
+
+ i82527_pre_read_config(chip, obj);
+
+ CANMSG("i82527_irq_update_filter: obj at 0x%08lx\n",obj->obj_base_addr);
+ }
+}
+
+
+void i82527_irq_sync_activities(struct canchip_t *chip, struct msgobj_t *obj)
+{
+ while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)) {
+
+ if(can_msgobj_test_and_clear_fl(obj,TX_REQUEST)) {
+ if(canobj_read_reg(chip,obj,iMSGCTL1)&TXRQ_RES)
+ i82527_irq_write_handler(chip, obj);
+ }
+
+ if(!obj->tx_slot) {
+ if(can_msgobj_test_and_clear_fl(obj,FILTCH_REQUEST)) {
+ i82527_irq_update_filter(chip, obj);
+ }
+ }
+
+ mb();
+
+ can_msgobj_clear_fl(obj,TX_LOCK);
+ if(can_msgobj_test_fl(obj,TX_REQUEST))
+ continue;
+ if(can_msgobj_test_fl(obj,FILTCH_REQUEST) && !obj->tx_slot)
+ continue;
+ break;
+ }
+}
+
+int i82527_irq_handler(int irq, struct canchip_t *chip)
+{
+ unsigned char msgcfg;
+
+ unsigned irq_register;
+ unsigned object;
+ struct msgobj_t *obj;
+ int loop_cnt=CHIP_MAX_IRQLOOP;
+
+ /*put_reg=device->hwspecops->write_register;*/
+ /*get_reg=device->hwspecops->read_register;*/
+
+ irq_register = i82527_seg_read_reg(chip, iIRQ);
+
+ if(!irq_register) {
+ DEBUGMSG("i82527: spurious IRQ\n");
+ return CANCHIP_IRQ_NONE;
+ }
+
+
+ do {
+
+ if(!loop_cnt--) {
+ CANMSG("i82527_irq_handler IRQ %d stuck\n",irq);
+ CANMSG("i82527_irq_register 0x%x\n",irq_register);
+ return CANCHIP_IRQ_STUCK;
+ }
+
+ DEBUGMSG("i82527: iIRQ 0x%02x\n",irq_register);
+
+ if (irq_register == 0x01) {
+ DEBUGMSG("Status register: 0x%x\n",can_read_reg(chip, iSTAT));
+ continue;
+ /*return CANCHIP_IRQ_NONE;*/
+ }
+
+ if (irq_register == 0x02)
+ object = 14;
+ else if(irq_register < 14)
+ object = irq_register-3;
+ else
+ return CANCHIP_IRQ_NONE;
+
+ obj=chip->msgobj[object];
+
+ msgcfg = canobj_read_reg(chip,obj,iMSGCFG);
+ if (msgcfg & MCFG_DIR) {
+ can_msgobj_set_fl(obj,TX_REQUEST);
+
+ /* calls i82527_irq_write_handler synchronized with other invocations */
+ i82527_irq_sync_activities(chip, obj);
+ }
+ else {
+
+ i82527_irq_read_handler(chip, obj, object);
+ }
+
+ } while((irq_register=i82527_seg_read_reg(chip, iIRQ)) != 0);
+
+ return CANCHIP_IRQ_HANDLED;
+}
+
+void i82527_irq_rtr_handler(struct canchip_t *chip, struct msgobj_t *obj,
+ struct rtr_id *rtr_search, unsigned long message_id)
+{
+ short int i=0;
+
+ canobj_write_reg(chip,obj,(MVAL_RES|TXIE_RES|RXIE_RES|INTPD_RES),iMSGCTL0);
+ canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|MLST_RES|NEWD_RES),iMSGCTL1);
+
+ can_spin_lock(&hardware_p->rtr_lock);
+
+ rtr_search->rtr_message->id=message_id;
+ rtr_search->rtr_message->length=(canobj_read_reg(chip,obj,iMSGCFG) & 0xf0)>>4;
+ for (i=0; i<rtr_search->rtr_message->length; i++)
+ rtr_search->rtr_message->data[i]=canobj_read_reg(chip,obj,iMSGDAT0+i);
+
+ can_spin_unlock(&hardware_p->rtr_lock);
+
+ if (waitqueue_active(&rtr_search->rtr_wq))
+ wake_up(&rtr_search->rtr_wq);
+}
+
+/**
+ * i82527_wakeup_tx: - wakeups TX processing
+ * @chip: pointer to chip state structure
+ * @obj: pointer to message object structure
+ *
+ * Function is responsible for initiating message transmition.
+ * It is responsible for clearing of object TX_REQUEST flag
+ *
+ * Return Value: negative value reports error.
+ * File: src/i82527.c
+ */
+int i82527_wakeup_tx(struct canchip_t *chip, struct msgobj_t *obj)
+{
+ can_preempt_disable();
+
+ can_msgobj_set_fl(obj,TX_REQUEST);
+
+ /* calls i82527_irq_write_handler synchronized with other invocations
+ from kernel and IRQ context */
+ i82527_irq_sync_activities(chip, obj);
+
+ can_preempt_enable();
+ return 0;
+}
+
+int i82527_filtch_rq(struct canchip_t *chip, struct msgobj_t *obj)
+{
+ can_preempt_disable();
+
+ can_msgobj_set_fl(obj,FILTCH_REQUEST);
+
+ /* setups filter synchronized with other invocations from kernel and IRQ context */
+ i82527_irq_sync_activities(chip, obj);
+
+ can_preempt_enable();
+ return 0;
+}
+
int i82527_register(struct chipspecops_t *chipspecops)
{
chipspecops->chip_config = i82527_chip_config;
chipspecops->pre_write_config = i82527_pre_write_config;
chipspecops->send_msg = i82527_send_msg;
chipspecops->check_tx_stat = i82527_check_tx_stat;
+ chipspecops->wakeup_tx = i82527_wakeup_tx;
+ chipspecops->filtch_rq = i82527_filtch_rq;
chipspecops->remote_request = i82527_remote_request;
chipspecops->enable_configuration = i82527_enable_configuration;
chipspecops->disable_configuration = i82527_disable_configuration;
chipspecops->set_btregs = i82527_set_btregs;
+ chipspecops->attach_to_chip = i82527_attach_to_chip;
+ chipspecops->release_chip = i82527_release_chip;
chipspecops->start_chip = i82527_start_chip;
chipspecops->stop_chip = i82527_stop_chip;
+ chipspecops->irq_handler = i82527_irq_handler;
+ chipspecops->irq_accept = NULL;
+ return 0;
+}
+
+int i82527_fill_chipspecops(struct canchip_t *chip)
+{
+ chip->chip_type="i82527";
+ chip->max_objects=15;
+ i82527_register(chip->chipspecops);
return 0;
}
projects / lincan.git / blobdiff