/* sja1000.h
* Header file for the Linux CAN-bus driver.
* Written by Arnaud Westenberg email:arnaud@wanadoo.nl
+ * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
+ * email:pisa@cmp.felk.cvut.cz
* This software is released under the GPL-License.
- * Version 0.7 6 Aug 2001
+ * Version lincan-0.3 17 Jun 2004
*/
-int sja1000_enable_configuration(struct chip_t *chip);
-int sja1000_disable_configuration(struct chip_t *chip);
-int sja1000_chip_config(struct chip_t *chip);
-int sja1000_standard_mask(struct chip_t *chip, unsigned short code, unsigned short mask);
-int sja1000_baud_rate(struct chip_t *chip, int rate, int clock, int sjw,
+int sja1000_enable_configuration(struct canchip_t *chip);
+int sja1000_disable_configuration(struct canchip_t *chip);
+int sja1000_chip_config(struct canchip_t *chip);
+int sja1000_standard_mask(struct canchip_t *chip, unsigned short code, unsigned short mask);
+int sja1000_baud_rate(struct canchip_t *chip, int rate, int clock, int sjw,
int sampl_pt, int flags);
-int sja1000_pre_read_config(struct chip_t *chip, struct msgobj_t *obj);
-int sja1000_pre_write_config(struct chip_t *chip, struct msgobj_t *obj,
+int sja1000_pre_read_config(struct canchip_t *chip, struct msgobj_t *obj);
+int sja1000_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj,
struct canmsg_t *msg);
-int sja1000_send_msg(struct chip_t *chip, struct msgobj_t *obj,
+int sja1000_send_msg(struct canchip_t *chip, struct msgobj_t *obj,
struct canmsg_t *msg);
-int sja1000_check_tx_stat(struct chip_t *chip);
-int sja1000_set_btregs(struct chip_t *chip, unsigned short btr0,
+int sja1000_check_tx_stat(struct canchip_t *chip);
+int sja1000_set_btregs(struct canchip_t *chip, unsigned short btr0,
unsigned short btr1);
-int sja1000_start_chip(struct chip_t *chip);
-int sja1000_stop_chip(struct chip_t *chip);
-void sja1000_irq_handler(int irq, void *dev_id, struct pt_regs *regs);
+int sja1000_start_chip(struct canchip_t *chip);
+int sja1000_stop_chip(struct canchip_t *chip);
+int sja1000_irq_handler(int irq, struct canchip_t *chip);
+int sja1000_fill_chipspecops(struct canchip_t *chip);
/* BasicCAN mode address map */
#define SJACR 0x00 /* Control register */
/* Command register */
enum sja1000_BASIC_CMR {
- CMR_TR = 1, // Transmission request
- CMR_AT = 1<<1, // Abort Transmission
- CMR_RRB = 1<<2, // Release Receive Buffer
- CMR_CDO = 1<<3, // Clear Data Overrun
- CMR_GTS = 1<<4 // Go To Sleep
+ sjaCMR_TR = 1, // Transmission request
+ sjaCMR_AT = 1<<1, // Abort Transmission
+ sjaCMR_RRB = 1<<2, // Release Receive Buffer
+ sjaCMR_CDO = 1<<3, // Clear Data Overrun
+ sjaCMR_GTS = 1<<4 // Go To Sleep
};
/* Status Register */
enum sja1000_BASIC_SR {
- SR_RBS = 1, // Receive Buffer Status
- SR_DOS = 1<<1, // Data Overrun Status
- SR_TBS = 1<<2, // Transmit Buffer Status
- SR_TCS = 1<<3, // Transmission Complete Status
- SR_RS = 1<<4, // Receive Status
- SR_TS = 1<<5, // Transmit Status
- SR_ES = 1<<6, // Error Status
- SR_BS = 1<<7 // Bus Status
+ sjaSR_RBS = 1, // Receive Buffer Status
+ sjaSR_DOS = 1<<1, // Data Overrun Status
+ sjaSR_TBS = 1<<2, // Transmit Buffer Status
+ sjaSR_TCS = 1<<3, // Transmission Complete Status
+ sjaSR_RS = 1<<4, // Receive Status
+ sjaSR_TS = 1<<5, // Transmit Status
+ sjaSR_ES = 1<<6, // Error Status
+ sjaSR_BS = 1<<7 // Bus Status
};
/* Control Register */
enum sja1000_BASIC_CR {
- CR_RR = 1, // Reset Request
- CR_RIE = 1<<1, // Receive Interrupt Enable
- CR_TIE = 1<<2, // Transmit Interrupt Enable
- CR_EIE = 1<<3, // Error Interrupt Enable
- CR_OIE = 1<<4 // Overrun Interrupt Enable
+ sjaCR_RR = 1, // Reset Request
+ sjaCR_RIE = 1<<1, // Receive Interrupt Enable
+ sjaCR_TIE = 1<<2, // Transmit Interrupt Enable
+ sjaCR_EIE = 1<<3, // Error Interrupt Enable
+ sjaCR_OIE = 1<<4 // Overrun Interrupt Enable
};
/* Interrupt (status) Register */
enum sja1000_BASIC_IR {
- IR_RI = 1, // Receive Interrupt
- IR_TI = 1<<1, // Transmit Interrupt
- IR_EI = 1<<2, // Error Interrupt
- IR_DOI = 1<<3, // Data Overrun Interrupt
- IR_WUI = 1<<4 // Wake-Up Interrupt
+ sjaIR_RI = 1, // Receive Interrupt
+ sjaIR_TI = 1<<1, // Transmit Interrupt
+ sjaIR_EI = 1<<2, // Error Interrupt
+ sjaIR_DOI = 1<<3, // Data Overrun Interrupt
+ sjaIR_WUI = 1<<4 // Wake-Up Interrupt
};
/* Clock Divider Register */
enum sja1000_CDR {
/* f_out = f_osc/(2*(CDR[2:0]+1)) or f_osc if CDR[2:0]==7 */
- CDR_CLKOUT_MASK = 7,
- CDR_CLK_OFF = 1<<3, // Clock Off
- CDR_RXINPEN = 1<<5, // TX1 output is RX irq output
- CDR_CBP = 1<<6, // Input Comparator By-Pass
- CDR_PELICAN = 1<<7 // PeliCAN Mode
+ sjaCDR_CLKOUT_DIV1 = 7,
+ sjaCDR_CLKOUT_DIV2 = 0,
+ sjaCDR_CLKOUT_DIV4 = 1,
+ sjaCDR_CLKOUT_DIV6 = 2,
+ sjaCDR_CLKOUT_DIV8 = 3,
+ sjaCDR_CLKOUT_DIV10 = 4,
+ sjaCDR_CLKOUT_DIV12 = 5,
+ sjaCDR_CLKOUT_DIV14 = 6,
+ sjaCDR_CLKOUT_MASK = 7,
+ sjaCDR_CLK_OFF = 1<<3, // Clock Off
+ sjaCDR_RXINPEN = 1<<5, // TX1 output is RX irq output
+ sjaCDR_CBP = 1<<6, // Input Comparator By-Pass
+ sjaCDR_PELICAN = 1<<7 // PeliCAN Mode
};
/* Output Control Register */
enum sja1000_OCR {
- OCR_MODE_BIPHASE = 0,
- OCR_MODE_TEST = 1,
- OCR_MODE_NORMAL = 2,
- OCR_MODE_CLOCK = 3,
+ sjaOCR_MODE_BIPHASE = 0,
+ sjaOCR_MODE_TEST = 1,
+ sjaOCR_MODE_NORMAL = 2,
+ sjaOCR_MODE_CLOCK = 3,
// TX0 push-pull not inverted
- OCR_TX0_LH = 0x18,
+ sjaOCR_TX0_LH = 0x18,
// TX0 push-pull inverted
- OCR_TX0_HL = 0x1c,
+ sjaOCR_TX0_HL = 0x1c,
// TX1 floating (off)
- OCR_TX1_ZZ = 0,
+ sjaOCR_TX1_ZZ = 0,
// TX1 pull-down not inverted
- OCR_TX1_LZ = 0x40
+ sjaOCR_TX1_LZ = 0x40
};
/** Frame format information 0x11 */
enum sja1000_BASIC_ID0 {
- ID0_RTR = 1<<4, // Remote request
- ID0_DLC_M = (1<<4)-1 // Length Mask
+ sjaID0_RTR = 1<<4, // Remote request
+ sjaID0_DLC_M = (1<<4)-1 // Length Mask
};
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