* Version lincan-0.2 9 Jul 2003
*/
-#define __NO_VERSION__
-#include <linux/module.h>
-
-#include <linux/autoconf.h>
-
-#include <linux/sched.h>
-#include <linux/fs.h>
-
+#include "../include/can.h"
+#include "../include/can_sysdep.h"
#include "../include/main.h"
#include "../include/i82527.h"
else
DEBUGMSG("Could read back, hardware is probably configured correctly\n");
- if (baudrate == 0)
- baudrate=1000;
+ if (chip->baudrate == 0)
+ chip->baudrate=1000000;
- if (i82527_baud_rate(chip,baudrate*1000,chip->clock,0,75,0)) {
+ if (i82527_baud_rate(chip,chip->baudrate,chip->clock,0,75,0)) {
CANMSG("Error configuring baud rate\n");
return -ENODEV;
}
CANMSG("Error clearing message objects\n");
return -ENODEV;
}
- if (i82527_config_irqs(chip,0x0a)) {
+ if (i82527_config_irqs(chip,iCTL_IE|iCTL_EIE)) { /* has been 0x0a */
CANMSG("Error configuring interrupts\n");
return -ENODEV;
}
}
canobj_write_reg(chip,obj,(NEWD_RES|MLST_RES|TXRQ_RES|RMPD_RES), iMSGCTL1);
canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0);
+
+ DEBUGMSG("i82527_pre_read_config: configured obj at 0x%08lx\n",obj->obj_base_addr);
+
return 0;
}
struct canmsg_t *msg)
{
int i=0,id0=0,id1=0,id2=0,id3=0;
+ int len;
+
+ len = msg->length;
+ if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
- canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|CPUU_SET|NEWD_RES),iMSGCTL1);
canobj_write_reg(chip,obj,(MVAL_SET|TXIE_SET|RXIE_RES|INTPD_RES),iMSGCTL0);
- if (extended) {
- canobj_write_reg(chip,obj,(msg->length<<4)+(MCFG_DIR|MCFG_XTD),iMSGCFG);
- }
- else {
- canobj_write_reg(chip,obj,(msg->length<<4)+MCFG_DIR,iMSGCFG);
- }
- if (extended) {
+ canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|CPUU_SET|NEWD_RES),iMSGCTL1);
+
+ if (extended || (msg->flags&MSG_EXT)) {
+ canobj_write_reg(chip,obj,(len<<4)|(MCFG_DIR|MCFG_XTD),iMSGCFG);
id0 = (unsigned char) (msg->id<<3);
id1 = (unsigned char) (msg->id>>5);
id2 = (unsigned char) (msg->id>>13);
canobj_write_reg(chip,obj,id3,iMSGID0);
}
else {
+ canobj_write_reg(chip,obj,(len<<4)|MCFG_DIR,iMSGCFG);
id1 = (unsigned char) (msg->id<<5);
id0 = (unsigned char) (msg->id>>3);
canobj_write_reg(chip,obj,id1,iMSGID1);
canobj_write_reg(chip,obj,id0,iMSGID0);
}
- canobj_write_reg(chip,obj,0xfa,iMSGCTL1);
- for (i=0; i<msg->length; i++) {
+ canobj_write_reg(chip,obj,RMPD_UNC|TXRQ_UNC|CPUU_SET|NEWD_SET,iMSGCTL1);
+ for (i=0; i<len; i++) {
canobj_write_reg(chip,obj,msg->data[i],iMSGDAT0+i);
}
int i82527_send_msg(struct chip_t *chip, struct msgobj_t *obj,
struct canmsg_t *msg)
{
+ canobj_write_reg(chip,obj,(MVAL_SET|TXIE_SET|RXIE_RES|INTPD_RES),iMSGCTL0);
+
if (msg->flags & MSG_RTR) {
canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|CPUU_RES|NEWD_SET),iMSGCTL1);
}
return 0;
}
-inline void i82527_irq_write_handler(struct chip_t *chip, struct msgobj_t *obj)
+static inline
+void i82527_irq_write_handler(struct chip_t *chip, struct msgobj_t *obj)
{
int cmd;
- canobj_write_reg(chip,obj,(MVAL_RES|TXIE_RES|RXIE_RES|INTPD_RES),+iMSGCTL0);
+ canobj_write_reg(chip,obj,(MVAL_RES|TXIE_RES|RXIE_RES|INTPD_RES),iMSGCTL0);
if(obj->tx_slot){
+ /* Do local transmitted message distribution if enabled */
+ if (processlocal){
+ obj->tx_slot->msg.flags |= MSG_LOCAL;
+ canque_filter_msg2edges(obj->qends, &obj->tx_slot->msg);
+ }
+ /* Free transmitted slot */
canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
obj->tx_slot=NULL;
}
canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
obj->tx_slot=NULL;
return;
- }
+ }
+ return;
}
-inline void i82527_irq_read_handler(struct chip_t *chip, struct msgobj_t *obj,
- unsigned long message_id)
+static inline
+void i82527_irq_read_handler(struct chip_t *chip, struct msgobj_t *obj, int objnum)
{
- int i=0, tmp=1 ;
+ int i;
+ unsigned long message_id;
+ int msgcfg, msgctl1;
- while (tmp) {
- canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|MLST_RES|NEWD_RES),iMSGCTL1);
- canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0);
+ msgctl1=canobj_read_reg(chip,obj,iMSGCTL1);
+ if(msgctl1 & NEWD_RES)
+ return;
+
+ do {
+ if(objnum != 14) {
+ canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|MLST_UNC|NEWD_RES),iMSGCTL1);
+ canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0);
+ }
+
+ msgcfg = canobj_read_reg(chip,obj,iMSGCFG);
+
+ if (msgcfg&MCFG_XTD) {
+ message_id =canobj_read_reg(chip,obj,iMSGID3);
+ message_id|=canobj_read_reg(chip,obj,iMSGID2)<<8;
+ message_id|=canobj_read_reg(chip,obj,iMSGID1)<<16;
+ message_id|=canobj_read_reg(chip,obj,iMSGID0)<<24;
+ message_id>>=3;
+ obj->rx_msg.flags = MSG_EXT;
+
+ }
+ else {
+ message_id =canobj_read_reg(chip,obj,iMSGID1);
+ message_id|=canobj_read_reg(chip,obj,iMSGID0)<<8;
+ message_id>>=5;
+ obj->rx_msg.flags = 0;
+ }
+
+ obj->rx_msg.length = (msgcfg >> 4) & 0xf;
+ if(obj->rx_msg.length > CAN_MSG_LENGTH) obj->rx_msg.length = CAN_MSG_LENGTH;
- obj->rx_msg.length =(canobj_read_reg(chip,obj,iMSGCFG) & 0xf0) >> 4;
obj->rx_msg.id = message_id;
+
for (i=0; i < obj->rx_msg.length; i++)
obj->rx_msg.data[i] = canobj_read_reg(chip,obj,iMSGDAT0+i);
-//FIXME: Add buffer overflow check, currently it's silently over written!
+
+ if(objnum != 14) {
+ /* if NEWD is set after data read, then read data are likely inconsistent */
+ msgctl1=canobj_read_reg(chip,obj,iMSGCTL1);
+ if(msgctl1 & NEWD_SET) {
+ CANMSG("i82527_irq_read_handler: object %d data overwritten\n",objnum);
+ continue;
+ }
+ }
+ else {
+ /* this object is special and data are queued in the shadow register */
+ canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0);
+ canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|MLST_UNC|NEWD_RES),iMSGCTL1);
+ msgctl1=canobj_read_reg(chip,obj,iMSGCTL1);
+ }
+
canque_filter_msg2edges(obj->qends, &obj->rx_msg);
+
+ if (msgctl1 & NEWD_SET)
+ continue;
+
+ if (msgctl1 & MLST_SET) {
+ canobj_write_reg(chip,obj,(RMPD_UNC|TXRQ_UNC|MLST_RES|NEWD_UNC),iMSGCTL1);
+ CANMSG("i82527_irq_read_handler: object %d message lost\n",objnum);
+ }
+
+ return;
- if (!((tmp=canobj_read_reg(chip,obj,iMSGCTL1)) & NEWD_SET)) {
- break;
+ } while(1);
+}
+
+/*
+ if (msgcfg&MCFG_XTD) {
+ message_id =canobj_read_reg(chip,obj,iMSGID3);
+ message_id|=canobj_read_reg(chip,obj,iMSGID2)<<8;
+ message_id|=canobj_read_reg(chip,obj,iMSGID1)<<16;
+ message_id|=canobj_read_reg(chip,obj,iMSGID0)<<24;
+ message_id>>=3;
+ }
+ else {
+ message_id =canobj_read_reg(chip,obj,iMSGID1);
+ message_id|=canobj_read_reg(chip,obj,iMSGID0)<<8;
+ message_id>>=5;
+ }
+
+ can_spin_lock(&hardware_p->rtr_lock);
+ rtr_search=hardware_p->rtr_queue;
+ while (rtr_search != NULL) {
+ if (rtr_search->id == message_id)
+ break;
+ rtr_search=rtr_search->next;
+ }
+ can_spin_unlock(&hardware_p->rtr_lock);
+ if ((rtr_search!=NULL) && (rtr_search->id==message_id))
+ i82527_irq_rtr_handler(chip, obj, rtr_search, message_id);
+ else
+ i82527_irq_read_handler(chip, obj, message_id);
+*/
+
+
+static inline
+void i82527_irq_update_filter(struct chip_t *chip, struct msgobj_t *obj)
+{
+ struct canfilt_t filt;
+ unsigned long id;
+
+ if(canqueue_ends_filt_conjuction(obj->qends, &filt)) {
+ canobj_write_reg(chip,obj,(MVAL_RES|TXIE_RES|RXIE_RES|INTPD_RES),iMSGCTL0);
+ if(obj->object == 15) {
+ i82527_message15_mask(chip,filt.id,filt.mask);
+ }
+ if (filt.flags&MSG_EXT) {
+ id=filt.id<<3;
+ canobj_write_reg(chip,obj,id,iMSGID3);
+ canobj_write_reg(chip,obj,id>>8,iMSGID2);
+ canobj_write_reg(chip,obj,id>>16,iMSGID1);
+ canobj_write_reg(chip,obj,id>>24,iMSGID0);
+ canobj_write_reg(chip,obj,MCFG_XTD,iMSGCFG);
+ }
+ else {
+ id=filt.id<<5;
+ canobj_write_reg(chip,obj,id,iMSGID1);
+ canobj_write_reg(chip,obj,id>>8,iMSGID0);
+ canobj_write_reg(chip,obj,0x00,iMSGCFG);
}
- if (tmp & MLST_SET)
- CANMSG("Message lost!\n");
+ canobj_write_reg(chip,obj,(NEWD_RES|MLST_RES|TXRQ_RES|RMPD_RES), iMSGCTL1);
+ canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0);
+ CANMSG("i82527_irq_update_filter: obj at 0x%08lx\n",obj->obj_base_addr);
+
}
}
-irqreturn_t i82527_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
+
+void i82527_irq_sync_activities(struct chip_t *chip, struct msgobj_t *obj)
{
- int id0=0, id1=0, id2=0, id3=0;
+ while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)) {
+
+ if(can_msgobj_test_and_clear_fl(obj,TX_REQUEST)) {
+ if(canobj_read_reg(chip,obj,iMSGCTL1)&TXRQ_RES)
+ i82527_irq_write_handler(chip, obj);
+ }
+
+ if(!obj->tx_slot) {
+ if(can_msgobj_test_and_clear_fl(obj,FILTCH_REQUEST)) {
+ i82527_irq_update_filter(chip, obj);
+ }
+ }
+
+ can_msgobj_clear_fl(obj,TX_LOCK);
+ if(can_msgobj_test_fl(obj,TX_REQUEST))
+ continue;
+ if(can_msgobj_test_fl(obj,FILTCH_REQUEST) && !obj->tx_slot)
+ continue;
+ break;
+ }
+}
+
+can_irqreturn_t i82527_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
+{
+ unsigned char msgcfg;
unsigned irq_register;
unsigned object;
struct chip_t *chip=(struct chip_t *)dev_id;
struct msgobj_t *obj;
- unsigned long message_id;
- struct rtr_id *rtr_search;
/*put_reg=device->hwspecops->write_register;*/
/*get_reg=device->hwspecops->read_register;*/
irq_register = i82527_seg_read_reg(chip, iIRQ);
- while (irq_register) {
+ if(!irq_register) {
+ DEBUGMSG("i82527: spurious IRQ\n");
+ return CAN_IRQ_NONE;
+ }
+
+ do {
+
+ DEBUGMSG("i82527: iIRQ 0x%02x\n",irq_register);
+
if (irq_register == 0x01) {
DEBUGMSG("Status register: 0x%x\n",can_read_reg(chip, iSTAT));
- return IRQ_NONE;
+ continue;
+ /*return CAN_IRQ_NONE;*/
}
if (irq_register == 0x02)
object = 14;
- else
+ else if(irq_register < 14)
object = irq_register-3;
+ else
+ return CAN_IRQ_NONE;
obj=chip->msgobj[object];
-
- if (canobj_read_reg(chip,obj,iMSGCFG) & MCFG_DIR) {
- set_bit(OBJ_TX_REQUEST,&obj->flags);
- while(!test_and_set_bit(OBJ_TX_LOCK,&obj->flags)){
- clear_bit(OBJ_TX_REQUEST,&obj->flags);
-
- if(canobj_read_reg(chip,obj,iMSGCTL1)&TXRQ_RES)
- i82527_irq_write_handler(chip, obj);
-
- clear_bit(OBJ_TX_LOCK,&obj->flags);
- if(!test_bit(OBJ_TX_REQUEST,&obj->flags)) break;
- }
+
+ msgcfg = canobj_read_reg(chip,obj,iMSGCFG);
+ if (msgcfg & MCFG_DIR) {
+ can_msgobj_set_fl(obj,TX_REQUEST);
+
+ /* calls i82527_irq_write_handler synchronized with other invocations */
+ i82527_irq_sync_activities(chip, obj);
}
else {
- if (extended) {
- id0=canobj_read_reg(chip,obj,iMSGID3);
- id1=canobj_read_reg(chip,obj,iMSGID2)<<8;
- id2=canobj_read_reg(chip,obj,iMSGID1)<<16;
- id3=canobj_read_reg(chip,obj,iMSGID0)<<24;
- message_id=(id0|id1|id2|id3)>>3;
- }
- else {
- id0=canobj_read_reg(chip,obj,iMSGID1);
- id1=canobj_read_reg(chip,obj,iMSGID0)<<8;
- message_id=(id0|id1)>>5;
- }
-
- spin_lock(&hardware_p->rtr_lock);
- rtr_search=hardware_p->rtr_queue;
- while (rtr_search != NULL) {
- if (rtr_search->id == message_id)
- break;
- rtr_search=rtr_search->next;
- }
- spin_unlock(&hardware_p->rtr_lock);
- if ((rtr_search!=NULL) && (rtr_search->id==message_id))
- i82527_irq_rtr_handler(chip, obj, rtr_search, message_id);
- else
- i82527_irq_read_handler(chip, obj, message_id);
+ i82527_irq_read_handler(chip, obj, object);
}
- irq_register=i82527_seg_read_reg(chip, iIRQ);
- }
- return IRQ_HANDLED;
+ } while((irq_register=i82527_seg_read_reg(chip, iIRQ)) != 0);
+
+ return CAN_IRQ_HANDLED;
}
void i82527_irq_rtr_handler(struct chip_t *chip, struct msgobj_t *obj,
canobj_write_reg(chip,obj,(MVAL_RES|TXIE_RES|RXIE_RES|INTPD_RES),iMSGCTL0);
canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|MLST_RES|NEWD_RES),iMSGCTL1);
- spin_lock(&hardware_p->rtr_lock);
+ can_spin_lock(&hardware_p->rtr_lock);
rtr_search->rtr_message->id=message_id;
rtr_search->rtr_message->length=(canobj_read_reg(chip,obj,iMSGCFG) & 0xf0)>>4;
for (i=0; i<rtr_search->rtr_message->length; i++)
rtr_search->rtr_message->data[i]=canobj_read_reg(chip,obj,iMSGDAT0+i);
- spin_unlock(&hardware_p->rtr_lock);
+ can_spin_unlock(&hardware_p->rtr_lock);
if (waitqueue_active(&rtr_search->rtr_wq))
- wake_up_interruptible(&rtr_search->rtr_wq);
+ wake_up(&rtr_search->rtr_wq);
}
+/**
+ * i82527_wakeup_tx: - wakeups TX processing
+ * @chip: pointer to chip state structure
+ * @obj: pointer to message object structure
+ *
+ * Function is responsible for initiating message transmition.
+ * It is responsible for clearing of object TX_REQUEST flag
+ *
+ * Return Value: negative value reports error.
+ * File: src/i82527.c
+ */
int i82527_wakeup_tx(struct chip_t *chip, struct msgobj_t *obj)
{
- /* dummy lock to prevent preemption fully portable way */
- spinlock_t dummy_lock;
-
- /* preempt_disable() */
- spin_lock_init(&dummy_lock);
- spin_lock(&dummy_lock);
+ can_preempt_disable();
- set_bit(OBJ_TX_REQUEST,&obj->flags);
- while(!test_and_set_bit(OBJ_TX_LOCK,&obj->flags)){
- clear_bit(OBJ_TX_REQUEST,&obj->flags);
+ can_msgobj_set_fl(obj,TX_REQUEST);
- if(canobj_read_reg(chip,obj,iMSGCTL1)&TXRQ_RES)
- i82527_irq_write_handler(chip, obj);
+ /* calls i82527_irq_write_handler synchronized with other invocations
+ from kernel and IRQ context */
+ i82527_irq_sync_activities(chip, obj);
+
+ can_preempt_enable();
+ return 0;
+}
+
+int i82527_filtch_rq(struct chip_t *chip, struct msgobj_t *obj)
+{
+ can_preempt_disable();
- clear_bit(OBJ_TX_LOCK,&obj->flags);
- if(!test_bit(OBJ_TX_REQUEST,&obj->flags)) break;
- }
+ can_msgobj_set_fl(obj,FILTCH_REQUEST);
+
+ /* setups filter synchronized with other invocations from kernel and IRQ context */
+ i82527_irq_sync_activities(chip, obj);
+
+ can_preempt_enable();
+ return 0;
- /* preempt_enable(); */
- spin_unlock(&dummy_lock);
return 0;
}
chipspecops->send_msg = i82527_send_msg;
chipspecops->check_tx_stat = i82527_check_tx_stat;
chipspecops->wakeup_tx = i82527_wakeup_tx;
+ chipspecops->filtch_rq = i82527_filtch_rq;
chipspecops->remote_request = i82527_remote_request;
chipspecops->enable_configuration = i82527_enable_configuration;
chipspecops->disable_configuration = i82527_disable_configuration;
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