* Rewritten for new CAN queues by Pavel Pisa - OCERA team member
* email:pisa@cmp.felk.cvut.cz
* This software is released under the GPL-License.
- * Version lincan-0.2 9 Jul 2003
+ * Version lincan-0.3 17 Jun 2004
*/
#include "../include/can.h"
#include "../include/main.h"
#include "../include/i82527.h"
-void i82527_irq_rtr_handler(struct chip_t *chip, struct msgobj_t *obj,
+void i82527_irq_rtr_handler(struct canchip_t *chip, struct msgobj_t *obj,
struct rtr_id *rtr_search, unsigned long message_id);
/* helper functions for segmented cards read and write configuration and status registers
above 0xf offset */
-void i82527_seg_write_reg(const struct chip_t *chip, unsigned char data, unsigned address)
+void i82527_seg_write_reg(const struct canchip_t *chip, unsigned char data, unsigned address)
{
if((address > 0xf) && (chip->flags & CHIP_SEGMENTED))
canobj_write_reg(chip, chip->msgobj[(address>>4)-1],data, address & 0xf);
can_write_reg(chip, data, address);
}
-unsigned i82527_seg_read_reg(const struct chip_t *chip, unsigned address)
+unsigned i82527_seg_read_reg(const struct canchip_t *chip, unsigned address)
{
if((address > 0xf) && (chip->flags & CHIP_SEGMENTED))
return canobj_read_reg(chip, chip->msgobj[(address>>4)-1], address & 0xf);
return can_read_reg(chip, address);
}
-int i82527_enable_configuration(struct chip_t *chip)
+int i82527_enable_configuration(struct canchip_t *chip)
{
unsigned short flags=0;
return 0;
}
-int i82527_disable_configuration(struct chip_t *chip)
+int i82527_disable_configuration(struct canchip_t *chip)
{
unsigned short flags=0;
return 0;
}
-int i82527_chip_config(struct chip_t *chip)
+int i82527_chip_config(struct canchip_t *chip)
{
can_write_reg(chip,chip->int_cpu_reg,iCPU); // Configure cpu interface
can_write_reg(chip,(iCTL_CCE|iCTL_INI),iCTL); // Enable configuration
* param sampl_pt sample point in % (0-100) sets (TSEG1+2)/(TSEG1+TSEG2+3) ratio
* param flags fields BTR1_SAM, OCMODE, OCPOL, OCTP, OCTN, CLK_OFF, CBP
*/
-int i82527_baud_rate(struct chip_t *chip, int rate, int clock, int sjw,
+int i82527_baud_rate(struct canchip_t *chip, int rate, int clock, int sjw,
int sampl_pt, int flags)
{
int best_error = 1000000000, error;
if (i82527_enable_configuration(chip))
return -ENODEV;
- clock /=2;
+ if(chip->int_cpu_reg & iCPU_DSC)
+ clock /=2;
/* tseg even = round down, odd = round up */
for (tseg=(0+0+2)*2; tseg<=(MAX_TSEG2+MAX_TSEG1+2)*2+1; tseg++) {
return 0;
}
-int i82527_standard_mask(struct chip_t *chip, unsigned short code, unsigned short mask)
+int i82527_standard_mask(struct canchip_t *chip, unsigned short code, unsigned short mask)
{
unsigned char mask0, mask1;
return 0;
}
-int i82527_extended_mask(struct chip_t *chip, unsigned long code, unsigned long mask)
+int i82527_extended_mask(struct canchip_t *chip, unsigned long code, unsigned long mask)
{
unsigned char mask0, mask1, mask2, mask3;
return 0;
}
-int i82527_message15_mask(struct chip_t *chip, unsigned long code, unsigned long mask)
+int i82527_message15_mask(struct canchip_t *chip, unsigned long code, unsigned long mask)
{
unsigned char mask0, mask1, mask2, mask3;
}
-int i82527_clear_objects(struct chip_t *chip)
+int i82527_clear_objects(struct canchip_t *chip)
{
int i=0,id=0,data=0;
struct msgobj_t *obj;
return 0;
}
-int i82527_config_irqs(struct chip_t *chip, short irqs)
+int i82527_config_irqs(struct canchip_t *chip, short irqs)
{
can_write_reg(chip,irqs,iCTL);
DEBUGMSG("Configured hardware interrupt delivery\n");
return 0;
}
-int i82527_pre_read_config(struct chip_t *chip, struct msgobj_t *obj)
+int i82527_pre_read_config(struct canchip_t *chip, struct msgobj_t *obj)
{
- if (extended) {
+ unsigned long id=obj->rx_preconfig_id;
+
+ can_msgobj_set_fl(obj,RX_MODE);
+
+ if (extended || can_msgobj_test_fl(obj,RX_MODE_EXT)) {
+ id<<=3;
+ canobj_write_reg(chip,obj,id,iMSGID3);
+ canobj_write_reg(chip,obj,id>>8,iMSGID2);
+ canobj_write_reg(chip,obj,id>>16,iMSGID1);
+ canobj_write_reg(chip,obj,id>>24,iMSGID0);
canobj_write_reg(chip,obj,MCFG_XTD,iMSGCFG);
- }
- else {
+ } else {
+ id<<=5;
+ canobj_write_reg(chip,obj,id,iMSGID1);
+ canobj_write_reg(chip,obj,id>>8,iMSGID0);
canobj_write_reg(chip,obj,0x00,iMSGCFG);
}
+
canobj_write_reg(chip,obj,(NEWD_RES|MLST_RES|TXRQ_RES|RMPD_RES), iMSGCTL1);
canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0);
DEBUGMSG("i82527_pre_read_config: configured obj at 0x%08lx\n",obj->obj_base_addr);
-
return 0;
}
-int i82527_pre_write_config(struct chip_t *chip, struct msgobj_t *obj,
+int i82527_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj,
struct canmsg_t *msg)
{
int i=0,id0=0,id1=0,id2=0,id3=0;
len = msg->length;
if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
+ can_msgobj_clear_fl(obj,RX_MODE);
+
canobj_write_reg(chip,obj,(MVAL_SET|TXIE_SET|RXIE_RES|INTPD_RES),iMSGCTL0);
canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|CPUU_SET|NEWD_RES),iMSGCTL1);
return 0;
}
-int i82527_send_msg(struct chip_t *chip, struct msgobj_t *obj,
+int i82527_send_msg(struct canchip_t *chip, struct msgobj_t *obj,
struct canmsg_t *msg)
{
canobj_write_reg(chip,obj,(MVAL_SET|TXIE_SET|RXIE_RES|INTPD_RES),iMSGCTL0);
return 0;
}
-int i82527_check_tx_stat(struct chip_t *chip)
+int i82527_check_tx_stat(struct canchip_t *chip)
{
if (can_read_reg(chip,iSTAT) & iSTAT_TXOK) {
can_write_reg(chip,0x0,iSTAT);
}
}
-int i82527_remote_request(struct chip_t *chip, struct msgobj_t *obj)
+int i82527_remote_request(struct canchip_t *chip, struct msgobj_t *obj)
{
canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0);
canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_SET|MLST_RES|NEWD_RES),iMSGCTL1);
return 0;
}
-int i82527_set_btregs(struct chip_t *chip, unsigned short btr0,
+int i82527_set_btregs(struct canchip_t *chip, unsigned short btr0,
unsigned short btr1)
{
if (i82527_enable_configuration(chip))
return 0;
}
-int i82527_start_chip(struct chip_t *chip)
+int i82527_start_chip(struct canchip_t *chip)
{
unsigned short flags = 0;
return 0;
}
-int i82527_stop_chip(struct chip_t *chip)
+int i82527_stop_chip(struct canchip_t *chip)
{
unsigned short flags = 0;
return 0;
}
+int i82527_attach_to_chip(struct canchip_t *chip)
+{
+ return 0;
+}
+
+int i82527_release_chip(struct canchip_t *chip)
+{
+ i82527_stop_chip(chip);
+ can_write_reg(chip, (iCTL_CCE|iCTL_INI), iCTL);
+
+ return 0;
+}
+
static inline
-void i82527_irq_write_handler(struct chip_t *chip, struct msgobj_t *obj)
+void i82527_irq_write_handler(struct canchip_t *chip, struct msgobj_t *obj)
{
int cmd;
if(obj->tx_slot){
/* Do local transmitted message distribution if enabled */
if (processlocal){
+ /* fill CAN message timestamp */
+ can_filltimestamp(&obj->tx_slot->msg.timestamp);
+
obj->tx_slot->msg.flags |= MSG_LOCAL;
canque_filter_msg2edges(obj->qends, &obj->tx_slot->msg);
}
}
static inline
-void i82527_irq_read_handler(struct chip_t *chip, struct msgobj_t *obj, int objnum)
+void i82527_irq_read_handler(struct canchip_t *chip, struct msgobj_t *obj, int objnum)
{
int i;
unsigned long message_id;
}
+ /* fill CAN message timestamp */
+ can_filltimestamp(&obj->rx_msg.timestamp);
+
canque_filter_msg2edges(obj->qends, &obj->rx_msg);
if (msgctl1 & NEWD_SET)
static inline
-void i82527_irq_update_filter(struct chip_t *chip, struct msgobj_t *obj)
+void i82527_irq_update_filter(struct canchip_t *chip, struct msgobj_t *obj)
{
struct canfilt_t filt;
- unsigned long id;
if(canqueue_ends_filt_conjuction(obj->qends, &filt)) {
+ obj->rx_preconfig_id=filt.id;
canobj_write_reg(chip,obj,(MVAL_RES|TXIE_RES|RXIE_RES|INTPD_RES),iMSGCTL0);
if(obj->object == 15) {
i82527_message15_mask(chip,filt.id,filt.mask);
}
- if (filt.flags&MSG_EXT) {
- id=filt.id<<3;
- canobj_write_reg(chip,obj,id,iMSGID3);
- canobj_write_reg(chip,obj,id>>8,iMSGID2);
- canobj_write_reg(chip,obj,id>>16,iMSGID1);
- canobj_write_reg(chip,obj,id>>24,iMSGID0);
- canobj_write_reg(chip,obj,MCFG_XTD,iMSGCFG);
- }
- else {
- id=filt.id<<5;
- canobj_write_reg(chip,obj,id,iMSGID1);
- canobj_write_reg(chip,obj,id>>8,iMSGID0);
- canobj_write_reg(chip,obj,0x00,iMSGCFG);
- }
+ if (filt.flags&MSG_EXT)
+ can_msgobj_set_fl(obj,RX_MODE_EXT);
+ else
+ can_msgobj_clear_fl(obj,RX_MODE_EXT);
- canobj_write_reg(chip,obj,(NEWD_RES|MLST_RES|TXRQ_RES|RMPD_RES), iMSGCTL1);
- canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0);
+ i82527_pre_read_config(chip, obj);
CANMSG("i82527_irq_update_filter: obj at 0x%08lx\n",obj->obj_base_addr);
-
}
}
-void i82527_irq_sync_activities(struct chip_t *chip, struct msgobj_t *obj)
+void i82527_irq_sync_activities(struct canchip_t *chip, struct msgobj_t *obj)
{
while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)) {
}
}
+ mb();
+
can_msgobj_clear_fl(obj,TX_LOCK);
if(can_msgobj_test_fl(obj,TX_REQUEST))
continue;
}
}
-can_irqreturn_t i82527_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
+int i82527_irq_handler(int irq, struct canchip_t *chip)
{
unsigned char msgcfg;
unsigned irq_register;
unsigned object;
- struct chip_t *chip=(struct chip_t *)dev_id;
struct msgobj_t *obj;
+ int loop_cnt=CHIP_MAX_IRQLOOP;
/*put_reg=device->hwspecops->write_register;*/
/*get_reg=device->hwspecops->read_register;*/
if(!irq_register) {
DEBUGMSG("i82527: spurious IRQ\n");
- return CAN_IRQ_NONE;
+ return CANCHIP_IRQ_NONE;
}
do {
+ if(!loop_cnt--) {
+ CANMSG("i82527_irq_handler IRQ %d stuck\n",irq);
+ CANMSG("i82527_irq_register 0x%x\n",irq_register);
+ return CANCHIP_IRQ_STUCK;
+ }
+
DEBUGMSG("i82527: iIRQ 0x%02x\n",irq_register);
if (irq_register == 0x01) {
DEBUGMSG("Status register: 0x%x\n",can_read_reg(chip, iSTAT));
continue;
- /*return CAN_IRQ_NONE;*/
+ /*return CANCHIP_IRQ_NONE;*/
}
if (irq_register == 0x02)
else if(irq_register < 14)
object = irq_register-3;
else
- return CAN_IRQ_NONE;
+ return CANCHIP_IRQ_NONE;
obj=chip->msgobj[object];
i82527_irq_read_handler(chip, obj, object);
}
-
+
} while((irq_register=i82527_seg_read_reg(chip, iIRQ)) != 0);
- return CAN_IRQ_HANDLED;
+ return CANCHIP_IRQ_HANDLED;
}
-void i82527_irq_rtr_handler(struct chip_t *chip, struct msgobj_t *obj,
+void i82527_irq_rtr_handler(struct canchip_t *chip, struct msgobj_t *obj,
struct rtr_id *rtr_search, unsigned long message_id)
{
short int i=0;
wake_up(&rtr_search->rtr_wq);
}
-int i82527_wakeup_tx(struct chip_t *chip, struct msgobj_t *obj)
+/**
+ * i82527_wakeup_tx: - wakeups TX processing
+ * @chip: pointer to chip state structure
+ * @obj: pointer to message object structure
+ *
+ * Function is responsible for initiating message transmition.
+ * It is responsible for clearing of object TX_REQUEST flag
+ *
+ * Return Value: negative value reports error.
+ * File: src/i82527.c
+ */
+int i82527_wakeup_tx(struct canchip_t *chip, struct msgobj_t *obj)
{
can_preempt_disable();
return 0;
}
-int i82527_filtch_rq(struct chip_t *chip, struct msgobj_t *obj)
+int i82527_filtch_rq(struct canchip_t *chip, struct msgobj_t *obj)
{
can_preempt_disable();
can_preempt_enable();
return 0;
-
- return 0;
}
int i82527_register(struct chipspecops_t *chipspecops)
chipspecops->enable_configuration = i82527_enable_configuration;
chipspecops->disable_configuration = i82527_disable_configuration;
chipspecops->set_btregs = i82527_set_btregs;
+ chipspecops->attach_to_chip = i82527_attach_to_chip;
+ chipspecops->release_chip = i82527_release_chip;
chipspecops->start_chip = i82527_start_chip;
chipspecops->stop_chip = i82527_stop_chip;
chipspecops->irq_handler = i82527_irq_handler;
+ chipspecops->irq_accept = NULL;
+ return 0;
+}
+
+int i82527_fill_chipspecops(struct canchip_t *chip)
+{
+ chip->chip_type="i82527";
+ chip->max_objects=15;
+ i82527_register(chip->chipspecops);
return 0;
}
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