2 * Linux CAN-bus device driver.
3 * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
4 * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
5 * email:pisa@cmp.felk.cvut.cz
6 * This software is released under the GPL-License.
7 * Version lincan-0.2 9 Jul 2003
10 #define __NO_VERSION__
11 #include <linux/module.h>
13 #include <linux/autoconf.h>
15 #include <linux/sched.h>
18 #include "../include/main.h"
19 #include "../include/i82527.h"
21 void i82527_irq_rtr_handler(struct chip_t *chip, struct msgobj_t *obj,
22 struct rtr_id *rtr_search, unsigned long message_id);
29 /* helper functions for segmented cards read and write configuration and status registers
32 void i82527_seg_write_reg(const struct chip_t *chip, unsigned char data, unsigned address)
34 if((address > 0xf) && (chip->flags & CHIP_SEGMENTED))
35 canobj_write_reg(chip, chip->msgobj[(address>>4)-1],data, address & 0xf);
37 can_write_reg(chip, data, address);
40 unsigned i82527_seg_read_reg(const struct chip_t *chip, unsigned address)
42 if((address > 0xf) && (chip->flags & CHIP_SEGMENTED))
43 return canobj_read_reg(chip, chip->msgobj[(address>>4)-1], address & 0xf);
45 return can_read_reg(chip, address);
48 int i82527_enable_configuration(struct chip_t *chip)
50 unsigned short flags=0;
52 flags = can_read_reg(chip, iCTL) & (iCTL_IE|iCTL_SIE|iCTL_EIE);
53 can_write_reg(chip, flags|iCTL_CCE, iCTL);
58 int i82527_disable_configuration(struct chip_t *chip)
60 unsigned short flags=0;
62 flags = can_read_reg(chip, iCTL) & (iCTL_IE|iCTL_SIE|iCTL_EIE);
63 can_write_reg(chip, flags, iCTL);
68 int i82527_chip_config(struct chip_t *chip)
70 can_write_reg(chip,chip->int_cpu_reg,iCPU); // Configure cpu interface
71 can_write_reg(chip,(iCTL_CCE|iCTL_INI),iCTL); // Enable configuration
72 i82527_seg_write_reg(chip,chip->int_clk_reg,iCLK); // Set clock out slew rates
73 i82527_seg_write_reg(chip,chip->int_bus_reg,iBUS); /* Bus configuration */
74 can_write_reg(chip,0x00,iSTAT); /* Clear error status register */
76 /* Check if we can at least read back some arbitrary data from the
77 * card. If we can not, the card is not properly configured!
79 canobj_write_reg(chip,chip->msgobj[1],0x25,iMSGDAT1);
80 canobj_write_reg(chip,chip->msgobj[2],0x52,iMSGDAT3);
81 canobj_write_reg(chip,chip->msgobj[10],0xc3,iMSGDAT6);
82 if ( (canobj_read_reg(chip,chip->msgobj[1],iMSGDAT1) != 0x25) ||
83 (canobj_read_reg(chip,chip->msgobj[2],iMSGDAT3) != 0x52) ||
84 (canobj_read_reg(chip,chip->msgobj[10],iMSGDAT6) != 0xc3) ) {
85 CANMSG("Could not read back from the hardware.\n");
86 CANMSG("This probably means that your hardware is not correctly configured!\n");
90 DEBUGMSG("Could read back, hardware is probably configured correctly\n");
95 if (i82527_baud_rate(chip,baudrate*1000,chip->clock,0,75,0)) {
96 CANMSG("Error configuring baud rate\n");
99 if (i82527_standard_mask(chip,0x0000,stdmask)) {
100 CANMSG("Error configuring standard mask\n");
103 if (i82527_extended_mask(chip,0x00000000,extmask)) {
104 CANMSG("Error configuring extended mask\n");
107 if (i82527_message15_mask(chip,0x00000000,mo15mask)) {
108 CANMSG("Error configuring message 15 mask\n");
111 if (i82527_clear_objects(chip)) {
112 CANMSG("Error clearing message objects\n");
115 if (i82527_config_irqs(chip,0x0a)) {
116 CANMSG("Error configuring interrupts\n");
123 /* Set communication parameters.
124 * param rate baud rate in Hz
125 * param clock frequency of i82527 clock in Hz (ISA osc is 14318000)
126 * param sjw synchronization jump width (0-3) prescaled clock cycles
127 * param sampl_pt sample point in % (0-100) sets (TSEG1+2)/(TSEG1+TSEG2+3) ratio
128 * param flags fields BTR1_SAM, OCMODE, OCPOL, OCTP, OCTN, CLK_OFF, CBP
130 int i82527_baud_rate(struct chip_t *chip, int rate, int clock, int sjw,
131 int sampl_pt, int flags)
133 int best_error = 1000000000, error;
134 int best_tseg=0, best_brp=0, best_rate=0, brp=0;
135 int tseg=0, tseg1=0, tseg2=0;
137 if (i82527_enable_configuration(chip))
142 /* tseg even = round down, odd = round up */
143 for (tseg=(0+0+2)*2; tseg<=(MAX_TSEG2+MAX_TSEG1+2)*2+1; tseg++) {
144 brp = clock/((1+tseg/2)*rate)+tseg%2;
145 if (brp == 0 || brp > 64)
147 error = rate - clock/(brp*(1+tseg/2));
150 if (error <= best_error) {
154 best_rate = clock/(brp*(1+tseg/2));
157 if (best_error && (rate/best_error < 10)) {
158 CANMSG("baud rate %d is not possible with %d Hz clock\n",
160 CANMSG("%d bps. brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d\n",
161 best_rate, best_brp, best_tseg, tseg1, tseg2);
164 tseg2 = best_tseg-(sampl_pt*(best_tseg+1))/100;
167 if (tseg2 > MAX_TSEG2)
170 tseg1 = best_tseg-tseg2-2;
171 if (tseg1>MAX_TSEG1) {
173 tseg2 = best_tseg-tseg1-2;
176 DEBUGMSG("Setting %d bps.\n", best_rate);
177 DEBUGMSG("brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d, sampl_pt=%d\n",
178 best_brp, best_tseg, tseg1, tseg2,
179 (100*(best_tseg-tseg2)/(best_tseg+1)));
182 i82527_seg_write_reg(chip, sjw<<6 | best_brp, iBT0);
183 can_write_reg(chip, ((flags & BTR1_SAM) != 0)<<7 | tseg2<<4 | tseg1,
185 DEBUGMSG("Writing 0x%x to iBT0\n",(sjw<<6 | best_brp));
186 DEBUGMSG("Writing 0x%x to iBT1\n",((flags & BTR1_SAM) != 0)<<7 |
189 i82527_disable_configuration(chip);
194 int i82527_standard_mask(struct chip_t *chip, unsigned short code, unsigned short mask)
196 unsigned char mask0, mask1;
198 mask0 = (unsigned char) (mask >> 3);
199 mask1 = (unsigned char) (mask << 5);
201 can_write_reg(chip,mask0,iSGM0);
202 can_write_reg(chip,mask1,iSGM1);
204 DEBUGMSG("Setting standard mask to 0x%lx\n",(unsigned long)mask);
209 int i82527_extended_mask(struct chip_t *chip, unsigned long code, unsigned long mask)
211 unsigned char mask0, mask1, mask2, mask3;
213 mask0 = (unsigned char) (mask >> 21);
214 mask1 = (unsigned char) (mask >> 13);
215 mask2 = (unsigned char) (mask >> 5);
216 mask3 = (unsigned char) (mask << 3);
218 can_write_reg(chip,mask0,iEGM0);
219 can_write_reg(chip,mask1,iEGM1);
220 can_write_reg(chip,mask2,iEGM2);
221 can_write_reg(chip,mask3,iEGM3);
223 DEBUGMSG("Setting extended mask to 0x%lx\n",(unsigned long)mask);
228 int i82527_message15_mask(struct chip_t *chip, unsigned long code, unsigned long mask)
230 unsigned char mask0, mask1, mask2, mask3;
232 mask0 = (unsigned char) (mask >> 21);
233 mask1 = (unsigned char) (mask >> 13);
234 mask2 = (unsigned char) (mask >> 5);
235 mask3 = (unsigned char) (mask << 3);
237 can_write_reg(chip,mask0,i15M0);
238 can_write_reg(chip,mask1,i15M1);
239 can_write_reg(chip,mask2,i15M2);
240 can_write_reg(chip,mask3,i15M3);
242 DEBUGMSG("Setting message 15 mask to 0x%lx\n",mask);
249 int i82527_clear_objects(struct chip_t *chip)
252 struct msgobj_t *obj;
254 DEBUGMSG("Cleared all message objects on chip\n");
256 for (i=1; i<=15; i++) {
258 canobj_write_reg(chip,obj,(INTPD_RES|RXIE_RES|TXIE_RES|MVAL_RES),iMSGCTL0);
259 canobj_write_reg(chip,obj,(NEWD_RES|MLST_RES|TXRQ_RES|RMPD_RES), iMSGCTL1);
260 for (data=0x07; data<0x0f; data++)
261 canobj_write_reg(chip,obj,0x00,data);
262 for (id=2; id<6; id++) {
263 canobj_write_reg(chip,obj,0x00,id);
266 canobj_write_reg(chip,obj,0x00,iMSGCFG);
269 canobj_write_reg(chip,obj,MCFG_XTD,iMSGCFG);
273 DEBUGMSG("All message ID's set to standard\n");
275 DEBUGMSG("All message ID's set to extended\n");
280 int i82527_config_irqs(struct chip_t *chip, short irqs)
282 can_write_reg(chip,irqs,iCTL);
283 DEBUGMSG("Configured hardware interrupt delivery\n");
287 int i82527_pre_read_config(struct chip_t *chip, struct msgobj_t *obj)
290 canobj_write_reg(chip,obj,MCFG_XTD,iMSGCFG);
293 canobj_write_reg(chip,obj,0x00,iMSGCFG);
295 canobj_write_reg(chip,obj,(NEWD_RES|MLST_RES|TXRQ_RES|RMPD_RES), iMSGCTL1);
296 canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0);
301 int i82527_pre_write_config(struct chip_t *chip, struct msgobj_t *obj,
302 struct canmsg_t *msg)
304 int i=0,id0=0,id1=0,id2=0,id3=0;
308 if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
310 canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|CPUU_SET|NEWD_RES),iMSGCTL1);
311 canobj_write_reg(chip,obj,(MVAL_SET|TXIE_SET|RXIE_RES|INTPD_RES),iMSGCTL0);
313 if (extended || (msg->flags&MSG_EXT)) {
314 canobj_write_reg(chip,obj,(len<<4)|(MCFG_DIR|MCFG_XTD),iMSGCFG);
315 id0 = (unsigned char) (msg->id<<3);
316 id1 = (unsigned char) (msg->id>>5);
317 id2 = (unsigned char) (msg->id>>13);
318 id3 = (unsigned char) (msg->id>>21);
319 canobj_write_reg(chip,obj,id0,iMSGID3);
320 canobj_write_reg(chip,obj,id1,iMSGID2);
321 canobj_write_reg(chip,obj,id2,iMSGID1);
322 canobj_write_reg(chip,obj,id3,iMSGID0);
325 canobj_write_reg(chip,obj,(len<<4)|MCFG_DIR,iMSGCFG);
326 id1 = (unsigned char) (msg->id<<5);
327 id0 = (unsigned char) (msg->id>>3);
328 canobj_write_reg(chip,obj,id1,iMSGID1);
329 canobj_write_reg(chip,obj,id0,iMSGID0);
331 canobj_write_reg(chip,obj,0xfa,iMSGCTL1);
332 for (i=0; i<len; i++) {
333 canobj_write_reg(chip,obj,msg->data[i],iMSGDAT0+i);
339 int i82527_send_msg(struct chip_t *chip, struct msgobj_t *obj,
340 struct canmsg_t *msg)
342 if (msg->flags & MSG_RTR) {
343 canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|CPUU_RES|NEWD_SET),iMSGCTL1);
346 canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_SET|CPUU_RES|NEWD_SET),iMSGCTL1);
352 int i82527_check_tx_stat(struct chip_t *chip)
354 if (can_read_reg(chip,iSTAT) & iSTAT_TXOK) {
355 can_write_reg(chip,0x0,iSTAT);
359 can_write_reg(chip,0x0,iSTAT);
364 int i82527_remote_request(struct chip_t *chip, struct msgobj_t *obj)
366 canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0);
367 canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_SET|MLST_RES|NEWD_RES),iMSGCTL1);
372 int i82527_set_btregs(struct chip_t *chip, unsigned short btr0,
375 if (i82527_enable_configuration(chip))
378 i82527_seg_write_reg(chip, btr0, iBT0);
379 i82527_seg_write_reg(chip, btr1, iBT1);
381 i82527_disable_configuration(chip);
386 int i82527_start_chip(struct chip_t *chip)
388 unsigned short flags = 0;
390 flags = can_read_reg(chip, iCTL) & (iCTL_IE|iCTL_SIE|iCTL_EIE);
391 can_write_reg(chip, flags, iCTL);
396 int i82527_stop_chip(struct chip_t *chip)
398 unsigned short flags = 0;
400 flags = can_read_reg(chip, iCTL) & (iCTL_IE|iCTL_SIE|iCTL_EIE);
401 can_write_reg(chip, flags|(iCTL_CCE|iCTL_INI), iCTL);
406 inline void i82527_irq_write_handler(struct chip_t *chip, struct msgobj_t *obj)
410 canobj_write_reg(chip,obj,(MVAL_RES|TXIE_RES|RXIE_RES|INTPD_RES),+iMSGCTL0);
413 /* Do local transmitted message distribution if enabled */
415 obj->tx_slot->msg.flags |= MSG_LOCAL;
416 canque_filter_msg2edges(obj->qends, &obj->tx_slot->msg);
418 /* Free transmitted slot */
419 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
423 cmd=canque_test_outslot(obj->qends, &obj->tx_qedge, &obj->tx_slot);
427 if (chip->chipspecops->pre_write_config(chip, obj, &obj->tx_slot->msg)) {
429 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_PREP);
430 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
434 if (chip->chipspecops->send_msg(chip, obj, &obj->tx_slot->msg)) {
436 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_SEND);
437 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
443 inline void i82527_irq_read_handler(struct chip_t *chip, struct msgobj_t *obj,
444 unsigned long message_id)
449 canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|MLST_RES|NEWD_RES),iMSGCTL1);
450 canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0);
452 len = (canobj_read_reg(chip,obj,iMSGCFG) >> 4) & 0xf;
453 obj->rx_msg.length = len;
454 obj->rx_msg.id = message_id;
456 if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
457 for (i=0; i < obj->rx_msg.length; i++)
458 obj->rx_msg.data[i] = canobj_read_reg(chip,obj,iMSGDAT0+i);
460 canque_filter_msg2edges(obj->qends, &obj->rx_msg);
462 if (!((tmp=canobj_read_reg(chip,obj,iMSGCTL1)) & NEWD_SET)) {
467 CANMSG("Message lost!\n");
472 irqreturn_t i82527_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
474 int id0=0, id1=0, id2=0, id3=0;
476 unsigned irq_register;
478 struct chip_t *chip=(struct chip_t *)dev_id;
479 struct msgobj_t *obj;
480 unsigned long message_id;
481 struct rtr_id *rtr_search;
483 /*put_reg=device->hwspecops->write_register;*/
484 /*get_reg=device->hwspecops->read_register;*/
486 irq_register = i82527_seg_read_reg(chip, iIRQ);
488 while (irq_register) {
490 if (irq_register == 0x01) {
491 DEBUGMSG("Status register: 0x%x\n",can_read_reg(chip, iSTAT));
495 if (irq_register == 0x02)
498 object = irq_register-3;
500 obj=chip->msgobj[object];
502 if (canobj_read_reg(chip,obj,iMSGCFG) & MCFG_DIR) {
503 set_bit(OBJ_TX_REQUEST,&obj->flags);
504 while(!test_and_set_bit(OBJ_TX_LOCK,&obj->flags)){
505 clear_bit(OBJ_TX_REQUEST,&obj->flags);
507 if(canobj_read_reg(chip,obj,iMSGCTL1)&TXRQ_RES)
508 i82527_irq_write_handler(chip, obj);
510 clear_bit(OBJ_TX_LOCK,&obj->flags);
511 if(!test_bit(OBJ_TX_REQUEST,&obj->flags)) break;
517 id0=canobj_read_reg(chip,obj,iMSGID3);
518 id1=canobj_read_reg(chip,obj,iMSGID2)<<8;
519 id2=canobj_read_reg(chip,obj,iMSGID1)<<16;
520 id3=canobj_read_reg(chip,obj,iMSGID0)<<24;
521 message_id=(id0|id1|id2|id3)>>3;
524 id0=canobj_read_reg(chip,obj,iMSGID1);
525 id1=canobj_read_reg(chip,obj,iMSGID0)<<8;
526 message_id=(id0|id1)>>5;
529 spin_lock(&hardware_p->rtr_lock);
530 rtr_search=hardware_p->rtr_queue;
531 while (rtr_search != NULL) {
532 if (rtr_search->id == message_id)
534 rtr_search=rtr_search->next;
536 spin_unlock(&hardware_p->rtr_lock);
537 if ((rtr_search!=NULL) && (rtr_search->id==message_id))
538 i82527_irq_rtr_handler(chip, obj, rtr_search, message_id);
540 i82527_irq_read_handler(chip, obj, message_id);
543 irq_register=i82527_seg_read_reg(chip, iIRQ);
548 void i82527_irq_rtr_handler(struct chip_t *chip, struct msgobj_t *obj,
549 struct rtr_id *rtr_search, unsigned long message_id)
553 canobj_write_reg(chip,obj,(MVAL_RES|TXIE_RES|RXIE_RES|INTPD_RES),iMSGCTL0);
554 canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|MLST_RES|NEWD_RES),iMSGCTL1);
556 spin_lock(&hardware_p->rtr_lock);
558 rtr_search->rtr_message->id=message_id;
559 rtr_search->rtr_message->length=(canobj_read_reg(chip,obj,iMSGCFG) & 0xf0)>>4;
560 for (i=0; i<rtr_search->rtr_message->length; i++)
561 rtr_search->rtr_message->data[i]=canobj_read_reg(chip,obj,iMSGDAT0+i);
563 spin_unlock(&hardware_p->rtr_lock);
565 if (waitqueue_active(&rtr_search->rtr_wq))
566 wake_up_interruptible(&rtr_search->rtr_wq);
569 int i82527_wakeup_tx(struct chip_t *chip, struct msgobj_t *obj)
571 /* dummy lock to prevent preemption fully portable way */
572 spinlock_t dummy_lock;
574 /* preempt_disable() */
575 spin_lock_init(&dummy_lock);
576 spin_lock(&dummy_lock);
578 set_bit(OBJ_TX_REQUEST,&obj->flags);
579 while(!test_and_set_bit(OBJ_TX_LOCK,&obj->flags)){
580 clear_bit(OBJ_TX_REQUEST,&obj->flags);
582 if(canobj_read_reg(chip,obj,iMSGCTL1)&TXRQ_RES)
583 i82527_irq_write_handler(chip, obj);
585 clear_bit(OBJ_TX_LOCK,&obj->flags);
586 if(!test_bit(OBJ_TX_REQUEST,&obj->flags)) break;
589 /* preempt_enable(); */
590 spin_unlock(&dummy_lock);
594 int i82527_register(struct chipspecops_t *chipspecops)
596 chipspecops->chip_config = i82527_chip_config;
597 chipspecops->baud_rate = i82527_baud_rate;
598 chipspecops->standard_mask = i82527_standard_mask;
599 chipspecops->extended_mask = i82527_extended_mask;
600 chipspecops->message15_mask = i82527_message15_mask;
601 chipspecops->clear_objects = i82527_clear_objects;
602 chipspecops->config_irqs = i82527_config_irqs;
603 chipspecops->pre_read_config = i82527_pre_read_config;
604 chipspecops->pre_write_config = i82527_pre_write_config;
605 chipspecops->send_msg = i82527_send_msg;
606 chipspecops->check_tx_stat = i82527_check_tx_stat;
607 chipspecops->wakeup_tx = i82527_wakeup_tx;
608 chipspecops->remote_request = i82527_remote_request;
609 chipspecops->enable_configuration = i82527_enable_configuration;
610 chipspecops->disable_configuration = i82527_disable_configuration;
611 chipspecops->set_btregs = i82527_set_btregs;
612 chipspecops->start_chip = i82527_start_chip;
613 chipspecops->stop_chip = i82527_stop_chip;
614 chipspecops->irq_handler = i82527_irq_handler;