lincan/src/ems_cpcpci.c

   1 /* ems_cpcpci.c - support for EMS-WUENSCHE CPC-PCI card
   2  * Linux CAN-bus device driver.
   3  * The card support added by Paolo Grisleri <grisleri@ce.unipr.it>
   4  * This software is released under the GPL-License.
   5  * Version lincan-0.3  17 Jun 2004
   6  */
   7
   8 #include "../include/can.h"
   9 #include "../include/can_sysdep.h"
  10 #include "../include/main.h"
  11 #include "../include/sja1000p.h"
  12
  13 #ifdef CAN_ENABLE_PCI_SUPPORT
  14
  15
  16 /* the only one supported: EMS CPC-PCI */
  17 // PGX: check identifiers name
  18 # define EMS_CPCPCI_PCICAN_VENDOR 0x110a
  19 # define EMS_CPCPCI_PCICAN_ID 0x2104
  20
  21 /*The Infineon PSB4610 PITA-2 is used as PCI to local bus bridge*/
  22 /*BAR0 - MEM - bridge control registers*/
  23
  24 /*BAR1 - MEM - parallel interface*/
  25 /* 0 more EMS control registers
  26  * 0x400 the first SJA1000
  27  * 0x600 the second SJA1000
  28  * each register occupies 4 bytes
  29  */
  30
  31 /*PSB4610 PITA-2 bridge control registers*/
  32 #define PITA2_ICR  0x00  /* Interrupt Control Register */
  33 #define   PITA2_ICR_INT0    0x00000002  /* [RC] INT0 Active/Clear */
  34 #define   PITA2_ICR_GP0_INT 0x00000004  /* [RC] GP0 Interrupt */
  35                                         /* GP0_Int_En=1, GP0_Out_En=0 and low detected */
  36 #define   PITA2_ICR_GP1_INT 0x00000008  /* [RC] GP1 Interrupt */
  37 #define   PITA2_ICR_GP2_INT 0x00000010  /* [RC] GP2 Interrupt */
  38 #define   PITA2_ICR_GP3_INT 0x00000020  /* [RC] GP2 Interrupt */
  39 #define   PITA2_ICR_INT0_En 0x00020000  /* [RW] Enable INT0 */
  40
  41 #define PITA2_MISC 0x1C  /* Miscellaneous Register */
  42 #define   PITA2_MISC_CONFIG 0x04000000
  43                          /* Multiplexed Parallel_interface_mode */
  44
  45 #define EMS_CPCPCI_BYTES_PER_CIRCUIT 0x200
  46 /* Each CPC register occupies 4 bytes */
  47 #define EMS_CPCPCI_BYTES_PER_REG     0x4
  48
  49 // Standard value: Pushpull  (OCTP1|OCTN1|OCTP0|OCTN0|OCM1)
  50 #define EMS_CPCPCI_OCR_DEFAULT_STD 0xDA
  51 // For Galathea piggyback.
  52 #define EMS_CPCPCI_OCR_DEFAULT_GAL 0xDB
  53
  54 /*
  55
  56 The board configuration is probably following:
  57 " RX1 is connected to ground.
  58 " TX1 is not connected.
  59 " CLKO is not connected.
  60 " Setting the OCR register to 0xDA is a good idea.
  61   This means  normal output mode , push-pull and the correct polarity.
  62 " In the CDR register, you should set CBP to 1.
  63   You will probably also want to set the clock divider value to 7
  64   (meaning direct oscillator output) because the second SJA1000 chip
  65   is driven by the first one CLKOUT output.
  66
  67 */
  68
  69
  70
  71 void ems_cpcpci_disconnect_irq(struct candevice_t *candev)
  72 {
  73         /* Disable interrupts from card */
  74         writel(0, candev->dev_base_addr + PITA2_ICR);
  75 }
  76
  77 void ems_cpcpci_connect_irq(struct candevice_t *candev)
  78 {
  79         /* Enable interrupts from card */
  80         writel(PITA2_ICR_INT0_En, candev->dev_base_addr + PITA2_ICR);
  81 }
  82
  83
  84 int ems_cpcpci_request_io(struct candevice_t *candev)
  85 {
  86         unsigned long pita2_addr;
  87         unsigned long io_addr;
  88         int i;
  89
  90     #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))
  91         if(pci_request_region(candev->sysdevptr.pcidev, 0, "ems_cpcpci_pita2") != 0){
  92                 CANMSG("Request of ems_cpcpci_pita2 range failed\n");
  93                 return -ENODEV;
  94         }else if(pci_request_region(candev->sysdevptr.pcidev, 1, "ems_cpcpci_io") != 0){
  95                 CANMSG("Request of ems_cpcpci_io range failed\n");
  96                 goto error_io;
  97         }
  98     #else /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
  99         if(pci_request_regions(candev->sysdevptr.pcidev, "EMS_CPCPCI") != 0){
 100                 CANMSG("Request of ems_cpcpci_s5920 regions failed\n");
 101                 return -ENODEV;
 102         }
 103     #endif /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
 104
 105         pita2_addr=pci_resource_start(candev->sysdevptr.pcidev,0);
 106         if (!(candev->dev_base_addr = (long) ioremap(pita2_addr,
 107               pci_resource_len(candev->sysdevptr.pcidev,0)))) {
 108                 CANMSG("Unable to access I/O memory at: 0x%lx\n", pita2_addr);
 109                 goto error_ioremap_pita2;
 110         }
 111
 112         io_addr=pci_resource_start(candev->sysdevptr.pcidev,1);;
 113         if (!(candev->io_addr = (long) ioremap(io_addr,
 114               pci_resource_len(candev->sysdevptr.pcidev,1)))) {
 115                 CANMSG("Unable to access I/O memory at: 0x%lx\n", io_addr);
 116                 goto error_ioremap_io;
 117         }
 118
 119         candev->res_addr=candev->io_addr;
 120
 121         /*
 122          * this is redundant with chip initialization, but remap address
 123          * can change when resources are temporarily released
 124          */
 125         for(i=0;i<candev->nr_all_chips;i++) {
 126                 struct chip_t *chip=candev->chip[i];
 127                 if(!chip) continue;
 128                 chip->chip_base_addr = candev->io_addr+
 129                         0x400 + i*EMS_CPCPCI_BYTES_PER_CIRCUIT;
 130                 if(!chip->msgobj[0]) continue;
 131                 chip->msgobj[0]->obj_base_addr=chip->chip_base_addr;
 132         }
 133
 134         /* Configure PITA-2 parallel interface */
 135         writel(PITA2_MISC_CONFIG, candev->dev_base_addr + PITA2_MISC);
 136
 137         ems_cpcpci_disconnect_irq(candev);
 138
 139         return 0;
 140
 141     error_ioremap_io:
 142         iounmap((void*)candev->dev_base_addr);
 143     error_ioremap_pita2:
 144     #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))
 145         pci_release_region(candev->sysdevptr.pcidev, 1);
 146     error_io:
 147         pci_release_region(candev->sysdevptr.pcidev, 0);
 148     #else /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
 149         pci_release_regions(candev->sysdevptr.pcidev);
 150     #endif /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
 151
 152         return -ENODEV;
 153 }
 154
 155 int ems_cpcpci_release_io(struct candevice_t *candev)
 156 {
 157         ems_cpcpci_disconnect_irq(candev);
 158
 159         iounmap((void*)candev->io_addr);
 160         iounmap((void*)candev->dev_base_addr);
 161     #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))
 162         pci_release_region(candev->sysdevptr.pcidev, 1);
 163         pci_release_region(candev->sysdevptr.pcidev, 0);
 164     #else /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
 165         pci_release_regions(candev->sysdevptr.pcidev);
 166     #endif /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
 167
 168         return 0;
 169 }
 170
 171
 172 void ems_cpcpci_write_register(unsigned data, unsigned long address)
 173 {
 174         address += ((address&(EMS_CPCPCI_BYTES_PER_CIRCUIT-1))
 175                             *(EMS_CPCPCI_BYTES_PER_REG-1));
 176         writeb(data,address);
 177 }
 178
 179 unsigned ems_cpcpci_read_register(unsigned long address)
 180 {
 181         address += ((address&(EMS_CPCPCI_BYTES_PER_CIRCUIT-1))
 182                             *(EMS_CPCPCI_BYTES_PER_REG-1));
 183         return readb(address);
 184 }
 185
 186 extern can_irqreturn_t sja1000p_irq_handler(int irq, void *dev_id, struct pt_regs *regs);
 187
 188 can_irqreturn_t ems_cpcpci_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
 189 {
 190         struct chip_t *chip=(struct chip_t *)dev_id;
 191         struct candevice_t *candev=chip->hostdevice;
 192         int i;
 193         unsigned long icr;
 194         int test_irq_again;
 195
 196         icr=readl(candev->dev_base_addr + PITA2_ICR);
 197         if(!(icr & PITA2_ICR_INT0)) return CAN_IRQ_NONE;
 198
 199         /* correct way to handle interrupts from all chips connected to the one PITA-2 */
 200         do {
 201                 writel(PITA2_ICR_INT0_En | PITA2_ICR_INT0, candev->dev_base_addr + PITA2_ICR);
 202                 test_irq_again=0;
 203                 for(i=0;i<candev->nr_all_chips;i++){
 204                         chip=candev->chip[i];
 205                         if(!chip || !(chip->flags&CHIP_CONFIGURED))
 206                                 continue;
 207                         if(sja1000p_irq_handler(irq, chip, regs))
 208                                 test_irq_again=1;
 209                 }
 210                 icr=readl(candev->dev_base_addr + PITA2_ICR);
 211         } while((icr & PITA2_ICR_INT0)||test_irq_again);
 212         return CAN_IRQ_HANDLED;
 213 }
 214
 215 int ems_cpcpci_reset(struct candevice_t *candev)
 216 {
 217         int i=0,chip_nr;
 218         struct chip_t *chip;
 219         unsigned cdr;
 220
 221         DEBUGMSG("Resetting EMS_CPCPCI hardware ...\n");
 222
 223         /* Assert PTADR# - we're in passive mode so the other bits are not important */
 224
 225         ems_cpcpci_disconnect_irq(candev);
 226
 227         for(chip_nr=0;chip_nr<candev->nr_all_chips;chip_nr++){
 228                 if(!candev->chip[chip_nr]) continue;
 229                 chip=candev->chip[chip_nr];
 230
 231                 ems_cpcpci_write_register(sjaMOD_RM, chip->chip_base_addr+SJAMOD);
 232                 udelay(1000);
 233
 234                 cdr=ems_cpcpci_read_register(chip->chip_base_addr+SJACDR);
 235                 ems_cpcpci_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
 236
 237                 ems_cpcpci_write_register(0, chip->chip_base_addr+SJAIER);
 238
 239                 i=20;
 240                 ems_cpcpci_write_register(0, chip->chip_base_addr+SJAMOD);
 241                 while (ems_cpcpci_read_register(chip->chip_base_addr+SJAMOD)&sjaMOD_RM){
 242                         if(!i--) return -ENODEV;
 243                         udelay(1000);
 244                         ems_cpcpci_write_register(0, chip->chip_base_addr+SJAMOD);
 245                 }
 246
 247                 cdr=ems_cpcpci_read_register(chip->chip_base_addr+SJACDR);
 248                 ems_cpcpci_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
 249
 250                 ems_cpcpci_write_register(0, chip->chip_base_addr+SJAIER);
 251
 252                 ems_cpcpci_read_register(chip->chip_base_addr+SJAIR);
 253         }
 254
 255
 256         ems_cpcpci_connect_irq(candev);
 257
 258         return 0;
 259 }
 260
 261 int ems_cpcpci_init_hw_data(struct candevice_t *candev)
 262 {
 263         struct pci_dev *pcidev = NULL;
 264         int i;
 265         unsigned long l;
 266
 267         pcidev = pci_find_device(EMS_CPCPCI_PCICAN_VENDOR, EMS_CPCPCI_PCICAN_ID, pcidev);
 268         if(pcidev == NULL) return -ENODEV;
 269
 270         if (pci_enable_device (pcidev)){
 271                 printk(KERN_CRIT "Setup of EMS_CPCPCI failed\n");
 272                 return -EIO;
 273         }
 274         candev->sysdevptr.pcidev=pcidev;
 275
 276         for(i=0;i<2;i++){
 277                 if(!(pci_resource_flags(pcidev,0)&IORESOURCE_MEM)){
 278                         printk(KERN_CRIT "EMS_CPCPCI region %d is not memory\n",i);
 279                         return -EIO;
 280                 }
 281         }
 282
 283         /*request IO access temporarily to check card presence*/
 284         if(ems_cpcpci_request_io(candev)<0)
 285                 return -ENODEV;
 286
 287         /*** candev->dev_base_addr=pci_resource_start(pcidev,0); ***/
 288         /* some control registers */
 289         /*** candev->io_addr=pci_resource_start(pcidev,1); ***/
 290         /* 0 more EMS control registers
 291          * 0x400 the first SJA1000
 292          * 0x600 the second SJA1000
 293          * each register occupies 4 bytes
 294          */
 295
 296         /*candev->flags |= CANDEV_PROGRAMMABLE_IRQ;*/
 297
 298         for(l=0,i=0;i<4;i++){
 299                 l<<=8;
 300                 l|=readb(candev->io_addr + i*4);
 301         }
 302         i=readb(candev->io_addr + i*5);
 303
 304         CANMSG("EMS CPC-PCI check value %04lx, ID %d\n", l, i);
 305
 306         if(l!=0x55aa01cb) {
 307                 CANMSG("EMS CPC-PCI unexpected check values\n");
 308         }
 309
 310         /*if (!strcmp(candev->hwname,"ems_cpcpci"))*/
 311         candev->nr_82527_chips=0;
 312         candev->nr_sja1000_chips=2;
 313         candev->nr_all_chips=2;
 314
 315         ems_cpcpci_release_io(candev);
 316
 317         return 0;
 318 }
 319
 320 int ems_cpcpci_init_chip_data(struct candevice_t *candev, int chipnr)
 321 {
 322         if(candev->sysdevptr.pcidev==NULL)
 323                 return -ENODEV;
 324
 325         /* initialize common routines for the SJA1000 chip */
 326         sja1000p_fill_chipspecops(candev->chip[chipnr]);
 327
 328         /* special version of the IRQ handler is required for CPC-PCI board */
 329         candev->chip[chipnr]->chipspecops->irq_handler=ems_cpcpci_irq_handler;
 330
 331         candev->chip[chipnr]->chip_irq=candev->sysdevptr.pcidev->irq;
 332
 333         candev->chip[chipnr]->chip_base_addr = candev->io_addr+
 334                         0x400 + chipnr*EMS_CPCPCI_BYTES_PER_CIRCUIT;
 335         candev->chip[chipnr]->flags = 0;
 336         candev->chip[chipnr]->int_cpu_reg = 0;
 337         candev->chip[chipnr]->int_clk_reg = 0;
 338         candev->chip[chipnr]->int_bus_reg = 0;
 339         /* CLKOUT has to be equal to oscillator frequency to drive second chip */
 340         candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CBP | 7;
 341         candev->chip[chipnr]->sja_ocr_reg = EMS_CPCPCI_OCR_DEFAULT_STD;
 342         candev->chip[chipnr]->clock = 16000000;
 343         candev->chip[chipnr]->flags |= CHIP_IRQ_PCI;
 344
 345         return 0;
 346 }
 347
 348 int ems_cpcpci_init_obj_data(struct chip_t *chip, int objnr)
 349 {
 350         chip->msgobj[objnr]->obj_base_addr=chip->chip_base_addr;
 351         return 0;
 352 }
 353
 354 int ems_cpcpci_program_irq(struct candevice_t *candev)
 355 {
 356
 357         return 0;
 358 }
 359
 360 int ems_cpcpci_register(struct hwspecops_t *hwspecops)
 361 {
 362         hwspecops->request_io = ems_cpcpci_request_io;
 363         hwspecops->release_io = ems_cpcpci_release_io;
 364         hwspecops->reset = ems_cpcpci_reset;
 365         hwspecops->init_hw_data = ems_cpcpci_init_hw_data;
 366         hwspecops->init_chip_data = ems_cpcpci_init_chip_data;
 367         hwspecops->init_obj_data = ems_cpcpci_init_obj_data;
 368         hwspecops->write_register = ems_cpcpci_write_register;
 369         hwspecops->read_register = ems_cpcpci_read_register;
 370         hwspecops->program_irq = ems_cpcpci_program_irq;
 371         return 0;
 372 }
 373
 374
 375 #endif /*CAN_ENABLE_PCI_SUPPORT*/