lincan/src/c_can.c

   1 /* c_can.c - Hynix HMS30c7202 ARM generic C_CAN module handling
   2  * Linux CAN-bus device driver.
   3  * Written by Sebastian Stolzenberg email:stolzi@sebastian-stolzenberg.de
   4  * Based on code from Arnaud Westenberg email:arnaud@wanadoo.nl
   5  * and Ake Hedman, eurosource, akhe@eurosource.se
   6  * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
   7  * email:pisa@cmp.felk.cvut.cz
   8  * This software is released under the GPL-License.
   9  * Version lincan-0.3  17 Jun 2004
  10  */
  11
  12 #define __NO_VERSION__
  13
  14 #include "../include/can.h"
  15 #include "../include/can_sysdep.h"
  16 #include "../include/main.h"
  17 #include "../include/c_can.h"
  18
  19 extern int stdmask;
  20 extern int extmask;
  21
  22 CAN_DEFINE_SPINLOCK(c_can_spwlock);     // Spin lock for write operations
  23 CAN_DEFINE_SPINLOCK(c_can_sprlock);     // Spin lock for read operations
  24 CAN_DEFINE_SPINLOCK(c_can_if1lock);     // spin lock for the if1 register
  25 CAN_DEFINE_SPINLOCK(c_can_if2lock);     // spin lcok for the if2 register
  26
  27 /**
  28  * c_can_enable_configuration - enable chip configuration mode
  29  * @pchip: pointer to chip state structure
  30  */
  31 int c_can_enable_configuration(struct canchip_t *pchip)
  32 {
  33         int i = 0;
  34         u16 flags;
  35         DEBUGMSG("(c%d)calling c_can_enable_configuration(...)\n",
  36                  pchip->chip_idx);
  37 /*
  38    DEBUGMSG("Trying disable_irq(...) : ");
  39    //disable IRQ
  40         disable_irq(chip->chip_irq);
  41 */
  42         //read Control Register
  43         flags = c_can_read_reg_w(pchip, CCCR);
  44         //set Init-Bit in the Control Register (10 tries)
  45         while ((!(flags & CR_INIT)) && (i <= 10)) {
  46                 c_can_write_reg_w(pchip, flags | CR_INIT, CCCR);
  47                 udelay(1000);
  48                 i++;
  49                 flags = c_can_read_reg_w(pchip, CCCR);
  50         }
  51         if (i >= 10) {
  52                 CANMSG("Reset error\n");
  53                 //enable_irq(chip->chip_irq);
  54                 return -ENODEV;
  55         }
  56
  57         DEBUGMSG("-> ok\n");
  58         return 0;
  59 }
  60
  61 ///////////////////////////////////////////////////////////////////////
  62 int c_can_disable_configuration(struct canchip_t *pchip)
  63 {
  64         int i = 0;
  65         u16 flags;
  66
  67         DEBUGMSG("(c%d)calling c_can_disable_configuration(...)\n",
  68                  pchip->chip_idx);
  69         //read Control Register
  70         flags = c_can_read_reg_w(pchip, CCCR);
  71
  72         //reset Init-Bit in the Control Register (10 tries)
  73         while ((flags & CR_INIT) && (i <= 10)) {
  74                 c_can_write_reg_w(pchip, flags & ~CR_INIT, CCCR);
  75                 udelay(1000);   //100 microseconds
  76                 i++;
  77                 flags = c_can_read_reg_w(pchip, CCCR);
  78         }
  79         if (i >= 10) {
  80                 CANMSG("Error leaving reset status\n");
  81                 return -ENODEV;
  82         }
  83         //enable IRQ
  84         //enable_irq(chip->chip_irq);
  85         DEBUGMSG("-> ok\n");
  86         return 0;
  87 }
  88
  89 ///////////////////////////////////////////////////////////////////////
  90 int c_can_chip_config(struct canchip_t *pchip)
  91 {
  92
  93         DEBUGMSG("(c%d)calling c_can_chip_config(...)\n", pchip->chip_idx);
  94         // Validate pointer
  95         if (NULL == pchip)
  96                 return -1;
  97
  98         if (pchip->baudrate == 0)
  99                 pchip->baudrate = 1000000;
 100
 101         if (c_can_baud_rate
 102             (pchip, pchip->baudrate, pchip->clock, 0, 75, 0)) {
 103                 CANMSG("Error configuring baud rate\n");
 104                 return -ENODEV;
 105         }
 106         /*if (extended){
 107            if (c_can_extended_mask(pchip,0x0000000,extmask)) {
 108            CANMSG("Error configuring extended mask\n");
 109            return -ENODEV;
 110            }
 111            }else{
 112            if (c_can_standard_mask(pchip,0x0000,stdmask)) {
 113            CANMSG("Error configuring standard mask\n");
 114            return -ENODEV;
 115            }
 116            } */
 117         if (c_can_clear_objects(pchip)) {
 118                 CANMSG("Error clearing message objects\n");
 119                 return -ENODEV;
 120         }
 121         if (c_can_config_irqs(pchip, CR_MIE | CR_SIE | CR_EIE)) {
 122                 CANMSG("Error configuring interrupts\n");
 123                 return -ENODEV;
 124         }
 125
 126         DEBUGMSG("-> Configured successfully\n");
 127
 128 #ifdef REGDUMP
 129         c_can_registerdump(pchip);
 130 #endif
 131
 132         return 0;
 133 }
 134
 135 ///////////////////////////////////////////////////////////////////////
 136 /*
 137  * Checks if the Busy-Bit in the IF1-Command-Request Register is set
 138  */
 139 int c_can_if1_busycheck(struct canchip_t *pchip)
 140 {
 141
 142         int i = 0;
 143         unsigned short comreg = 0;
 144
 145         comreg = c_can_read_reg_w(pchip, CCIF1CR);
 146         while ((comreg & IFXCR_BUSY) && (i <= 100)) {
 147                 udelay(1);      //1 microseconds
 148                 i++;
 149                 comreg = c_can_read_reg_w(pchip, CCIF1CR);
 150         }
 151         if (i >= 10) {
 152                 CANMSG("Error Busy-Bit stays set\n");
 153                 return -ENODEV;
 154         }
 155
 156         return 0;
 157 }
 158
 159 ///////////////////////////////////////////////////////////////////////
 160 /*
 161  * Checks if the Busy-Bit in the IF2-Command-Request Register is set
 162  */
 163 int c_can_if2_busycheck(struct canchip_t *pchip)
 164 {
 165
 166         int i = 0;
 167         unsigned short comreg = 0;
 168
 169         comreg = c_can_read_reg_w(pchip, CCIF2CR);
 170         while ((comreg & IFXCR_BUSY) && (i <= 100)) {
 171                 udelay(1);      //1 microseconds
 172                 i++;
 173                 comreg = c_can_read_reg_w(pchip, CCIF2CR);
 174         }
 175         if (i >= 10) {
 176                 CANMSG("Error Busy-Bit stays set\n");
 177                 return -ENODEV;
 178         }
 179
 180         return 0;
 181 }
 182
 183 ///////////////////////////////////////////////////////////////////////
 184 /*
 185  * Though the C-CAN Chip can handle one mask for each Message Object, this Method defines
 186  * one mask for all MOs. That means every MO gets the same mask.
 187  */
 188
 189 /* Set communication parameters.
 190  * param rate baud rate in Hz
 191  * param clock frequency of C-CAN clock in Hz
 192  * param sjw synchronization jump width (0-3) prescaled clock cycles
 193  * param sampl_pt sample point in % (0-100) sets (TSEG1+2)/(TSEG1+TSEG2+3) ratio
 194  * param flags fields BTR1_SAM, OCMODE, OCPOL, OCTP, OCTN, CLK_OFF, CBP
 195  */
 196 int c_can_baud_rate(struct canchip_t *pchip, int rate, int clock,
 197                     int sjw, int sampl_pt, int flags)
 198 {
 199         int best_error = 1000000000, error;
 200         int best_tseg = 0, best_brp = 0, best_rate = 0, brp = 0;
 201         int tseg = 0, tseg1 = 0, tseg2 = 0;
 202
 203         unsigned short tempCR = 0;
 204
 205         DEBUGMSG("(c%d)calling c_can_baud_rate(...)\n", pchip->chip_idx);
 206
 207         if (c_can_enable_configuration(pchip))
 208                 return -ENODEV;
 209
 210         /* tseg even = round down, odd = round up */
 211         for (tseg = (0 + 0 + 2) * 2;
 212              tseg <= (MAX_TSEG2 + MAX_TSEG1 + 2) * 2 + 1; tseg++) {
 213                 brp = clock / ((1 + tseg / 2) * rate) + tseg % 2;
 214                 if (brp == 0 || brp > 64)
 215                         continue;
 216                 error = rate - clock / (brp * (1 + tseg / 2));
 217                 if (error < 0)
 218                         error = -error;
 219                 if (error <= best_error) {
 220                         best_error = error;
 221                         best_tseg = tseg / 2;
 222                         best_brp = brp - 1;
 223                         best_rate = clock / (brp * (1 + tseg / 2));
 224                 }
 225         }
 226         if (best_error && (rate / best_error < 10)) {
 227                 CANMSG("baud rate %d is not possible with %d Hz clock\n",
 228                        rate, clock);
 229                 CANMSG("%d bps. brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d\n",
 230                        best_rate, best_brp, best_tseg, tseg1, tseg2);
 231                 return -EINVAL;
 232         }
 233         tseg2 = best_tseg - (sampl_pt * (best_tseg + 1)) / 100;
 234         if (tseg2 < 0)
 235                 tseg2 = 0;
 236         if (tseg2 > MAX_TSEG2)
 237                 tseg2 = MAX_TSEG2;
 238         tseg1 = best_tseg - tseg2 - 2;
 239         if (tseg1 > MAX_TSEG1) {
 240                 tseg1 = MAX_TSEG1;
 241                 tseg2 = best_tseg - tseg1 - 2;
 242         }
 243
 244         DEBUGMSG("-> Setting %d bps.\n", best_rate);
 245         DEBUGMSG("->brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d, sampl_pt=%d\n",
 246                  best_brp, best_tseg, tseg1, tseg2,
 247                  (100 * (best_tseg - tseg2) / (best_tseg + 1)));
 248
 249         //read Control Register
 250         tempCR = c_can_read_reg_w(pchip, CCCR);
 251         //Configuration Change Enable
 252         c_can_write_reg_w(pchip, tempCR | CR_CCE, CCCR);
 253         c_can_write_reg_w(pchip,
 254                           ((unsigned short)tseg2) << 12 | ((unsigned short)
 255                                                            tseg1) << 8 |
 256                           (unsigned short)sjw << 6 | (unsigned short)best_brp,
 257                           CCBT);
 258
 259         if (c_can_disable_configuration(pchip))
 260                 return -ENODEV;
 261
 262         return 0;
 263 }
 264
 265 ///////////////////////////////////////////////////////////////////////
 266 int c_can_mask(struct msgobj_t *pmsgobj, u32 mask, u16 usedirbit)
 267 {
 268         unsigned short tempreg = 0;
 269         unsigned short readMaskCM;
 270         unsigned short writeMaskCM;
 271
 272         DEBUGMSG("(c%dm%d)calling c_can_mask(...)\n",
 273                  pmsgobj->hostchip->chip_idx, pmsgobj->object);
 274
 275         readMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_MASK;
 276         writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_MASK | IFXCM_WRRD;
 277
 278         spin_lock(&c_can_if1lock);
 279
 280         //load Message Object in IF1
 281         if (c_can_if1_busycheck(pmsgobj->hostchip))
 282                 return -ENODEV;
 283         c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF1CM);
 284         c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
 285
 286         //setting Message Valid Bit to zero
 287         if (c_can_if1_busycheck(pmsgobj->hostchip))
 288                 return -ENODEV;
 289         tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1A2);
 290         c_can_write_reg_w(pmsgobj->hostchip, tempreg & ~(IFXARB2_MVAL),
 291                           CCIF1A2);
 292         c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
 293         c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
 294
 295         //setting UMask, MsgVal and Mask Register
 296         if (c_can_if1_busycheck(pmsgobj->hostchip))
 297                 return -ENODEV;
 298
 299         //set indication, that mask is used
 300         tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1DMC);
 301         c_can_write_reg_w(pmsgobj->hostchip, tempreg | IFXMC_UMASK,
 302                 CCIF1DMC);
 303
 304         //writing acceptance mask for extended or standart mode
 305         if (can_msgobj_test_fl(pmsgobj, RX_MODE_EXT)) {
 306                 if (usedirbit)
 307                         c_can_write_reg_w(pmsgobj->hostchip,
 308                                           (mask >> 16 & 0x1FFF) | IFXMSK2_MXTD |
 309                                           IFXMSK2_MDIR, CCIF1M2);
 310                 else
 311                         c_can_write_reg_w(pmsgobj->hostchip,
 312                                           (mask >> 16 & 0x1FFF) | IFXMSK2_MXTD,
 313                                           CCIF1M2);
 314                 c_can_write_reg_w(pmsgobj->hostchip, (mask & 0xFFFF), CCIF1M1);
 315         } else {
 316                 if (usedirbit)
 317                         c_can_write_reg_w(pmsgobj->hostchip,
 318                                           ((mask << 2) & 0x1FFC) | IFXMSK2_MDIR,
 319                                           CCIF1M2);
 320                 else
 321                         c_can_write_reg_w(pmsgobj->hostchip,
 322                                           ((mask << 2) & 0x1FFC), CCIF1M2);
 323                 c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF1M1);
 324         }
 325
 326         //seting Message Valid Bit to one
 327         tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1A2);
 328         c_can_write_reg_w(pmsgobj->hostchip, tempreg | IFXARB2_MVAL, CCIF1A2);
 329         //write to chip
 330         c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
 331         c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
 332
 333         spin_unlock(&c_can_if1lock);
 334
 335         DEBUGMSG("-> Setting acceptance mask to 0x%lx\n", (unsigned long)mask);
 336
 337 #ifdef REGDUMP
 338         c_can_registerdump(pmsgobj->hostchip);
 339 #endif
 340
 341         return 0;
 342 }
 343
 344 ///////////////////////////////////////////////////////////////////////
 345 int c_can_use_mask(struct msgobj_t *pmsgobj, u16 useflag)
 346 {
 347         unsigned short tempreg = 0;
 348         unsigned short readMaskCM;
 349         unsigned short writeMaskCM;
 350
 351 #ifdef DEBUG
 352         char *boolstring = "false";
 353         if (useflag)
 354                 boolstring = "true";
 355 #endif
 356         DEBUGMSG("(c%dm%d)calling c_can_use_mask(...)\n",
 357                  pmsgobj->hostchip->chip_idx, pmsgobj->object);
 358
 359         readMaskCM = IFXCM_CNTRL | IFXCM_ARB;
 360         writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_WRRD;;
 361
 362         spin_lock(&c_can_if1lock);
 363
 364         //load Message Object in IF1
 365         if (c_can_if1_busycheck(pmsgobj->hostchip))
 366                 return -ENODEV;
 367         c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF1CM);
 368         c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
 369
 370         //setting Message Valid Bit to zero
 371         if (c_can_if1_busycheck(pmsgobj->hostchip))
 372                 return -ENODEV;
 373         tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1A2);
 374         c_can_write_reg_w(pmsgobj->hostchip, tempreg & ~IFXARB2_MVAL, CCIF1A2);
 375         c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
 376         c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
 377
 378         //setting UMask bit
 379         if (c_can_if1_busycheck(pmsgobj->hostchip))
 380                 return -ENODEV;
 381         if (useflag) {
 382                 tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1DMC);
 383                 c_can_write_reg_w(pmsgobj->hostchip, tempreg | IFXMC_UMASK,
 384                                   CCIF1DMC);
 385         } else {
 386                 tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1DMC);
 387                 c_can_write_reg_w(pmsgobj->hostchip, tempreg & ~IFXMC_UMASK,
 388                                   CCIF1DMC);
 389         }
 390         //seting Message Valid Bit to one
 391         tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1A2);
 392         c_can_write_reg_w(pmsgobj->hostchip, tempreg | IFXARB2_MVAL, CCIF1A2);
 393         //write to chip
 394         c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
 395         c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
 396
 397         spin_unlock(&c_can_if1lock);
 398
 399 #ifdef DEBUG
 400         DEBUGMSG("-> Setting umask bit to %s\n", boolstring);
 401 #endif
 402 #ifdef REGDUMP
 403         c_can_registerdump(pmsgobj->hostchip);
 404 #endif
 405
 406         return 0;
 407 }
 408
 409 ///////////////////////////////////////////////////////////////////////
 410 int c_can_clear_objects(struct canchip_t *pchip)
 411 {
 412         unsigned short i = 0;
 413         unsigned short tempreg = 0;
 414
 415         unsigned short maskCM = IFXCM_ARB;
 416
 417         DEBUGMSG("(c%d)calling c_can_clear_objects(...)\n", pchip->chip_idx);
 418
 419         spin_lock(&c_can_if1lock);
 420         spin_lock(&c_can_if2lock);
 421
 422         for (i = 0; i < 0x10; i++) {
 423
 424                 //loading Message Objects in IF1 and IF2
 425                 if (c_can_if1_busycheck(pchip))
 426                         return -ENODEV;
 427                 c_can_write_reg_w(pchip, maskCM, CCIF1CM);
 428                 c_can_write_reg_w(pchip, i, CCIF1CR);
 429                 if (c_can_if2_busycheck(pchip))
 430                         return -ENODEV;
 431                 c_can_write_reg_w(pchip, maskCM, CCIF2CM);
 432                 c_can_write_reg_w(pchip, i + 0x10, CCIF2CR);
 433
 434                 //setting Message Valid Bit to zero
 435                 if (c_can_if1_busycheck(pchip))
 436                         return -ENODEV;
 437                 tempreg = c_can_read_reg_w(pchip, CCIF1A2);
 438                 c_can_write_reg_w(pchip, tempreg & ~IFXARB2_MVAL, CCIF1A2);
 439                 c_can_write_reg_w(pchip, i, CCIF1CR);
 440                 if (c_can_if2_busycheck(pchip))
 441                         return -ENODEV;
 442                 tempreg = c_can_read_reg_w(pchip, CCIF2A2);
 443                 c_can_write_reg_w(pchip, tempreg & ~IFXARB2_MVAL, CCIF2A2);
 444                 c_can_write_reg_w(pchip, i + 0x10, CCIF2CR);
 445         }
 446
 447         for (i = 0; i < pchip->max_objects; i++) {
 448                 if (can_msgobj_test_fl(pchip->msgobj[i], OPENED)) {
 449                         // In- and output buffer re-initialization
 450                         canqueue_ends_flush_inlist(pchip->msgobj[i]->qends);
 451                         canqueue_ends_flush_outlist(pchip->msgobj[i]->qends);
 452
 453                 }
 454         }
 455
 456         spin_unlock(&c_can_if1lock);
 457         spin_unlock(&c_can_if2lock);
 458
 459         DEBUGMSG("-> Message Objects reset\n");
 460
 461         return 0;
 462 }
 463
 464 ///////////////////////////////////////////////////////////////////////
 465 int c_can_config_irqs(struct canchip_t *pchip, u16 irqs)
 466 {
 467         u16 tempreg;
 468
 469         DEBUGMSG("(c%d)calling c_can_config_irqs(...)\n", pchip->chip_idx);
 470
 471         tempreg = c_can_read_reg_w(pchip, CCCR);
 472         DEBUGMSG("-> CAN Control Register: 0x%4lx\n", (long)tempreg);
 473         c_can_write_reg_w(pchip, tempreg | (irqs & 0xe), CCCR);
 474         DEBUGMSG("-> Configured hardware interrupt delivery\n");
 475         return 0;
 476 }
 477
 478 ///////////////////////////////////////////////////////////////////////
 479 int c_can_pre_read_config(struct canchip_t *pchip, struct msgobj_t *pmsgobj)
 480 {
 481         unsigned short readMaskCM = IFXCM_CNTRL | IFXCM_ARB;
 482         unsigned short writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_WRRD;
 483         unsigned short mcreg = 0;
 484         u32 id = pmsgobj->rx_preconfig_id;
 485
 486         DEBUGMSG("(c%dm%d)calling c_can_pre_read_config(...)\n",
 487                  pmsgobj->hostchip->chip_idx, pmsgobj->object);
 488
 489         spin_lock(&c_can_if1lock);
 490
 491         if (c_can_if1_busycheck(pmsgobj->hostchip))
 492                 goto error_enodev;
 493
 494         //loading Message Object in IF1
 495         c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF1CM);
 496         c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
 497
 498         if (c_can_if1_busycheck(pmsgobj->hostchip))
 499                 goto error_enodev;
 500
 501         //setting Message Valid Bit to zero
 502         c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF1A2);
 503         c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
 504         c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
 505
 506         /* Only access when the C_CAN controller is idle */
 507         if (c_can_if1_busycheck(pmsgobj->hostchip))
 508                 goto error_enodev;
 509
 510         //Configuring Message-Object
 511         mcreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1DMC);
 512         c_can_write_reg_w(pmsgobj->hostchip,
 513                           ((mcreg & IFXMC_UMASK) | IFXMC_EOB | IFXMC_RXIE),
 514                           CCIF1DMC);
 515
 516         //writing arbitration mask for extended or standart mode
 517         if (can_msgobj_test_fl(pmsgobj, RX_MODE_EXT)) {
 518                 c_can_write_reg_w(pmsgobj->hostchip,
 519                                   IFXARB2_XTD | IFXARB2_MVAL | (id >> 16 &
 520                                                                 0x1FFF),
 521                                   CCIF1A2);
 522                 c_can_write_reg_w(pmsgobj->hostchip, id & 0xFFFF, CCIF1A1);
 523         } else {
 524                 c_can_write_reg_w(pmsgobj->hostchip,
 525                                   IFXARB2_MVAL | (id << 2 & 0x1FFC), CCIF1A2);
 526                 //c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF1A1);
 527         }
 528         c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
 529         c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
 530
 531         spin_unlock(&c_can_if1lock);
 532
 533         DEBUGMSG("-> Receiving through message object %d with id=%d\n",
 534                  pmsgobj->object, id);
 535 #ifdef REGDUMP
 536         c_can_registerdump(pmsgobj->hostchip);
 537 #endif
 538
 539         return 0;
 540
 541       error_enodev:
 542         CANMSG("Timeout in c_can_if1_busycheck\n");
 543         spin_unlock(&c_can_if1lock);
 544         return -ENODEV;
 545
 546 }
 547
 548 ///////////////////////////////////////////////////////////////////////
 549 int c_can_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj,
 550                            struct canmsg_t *msg)
 551 {
 552         return 0;
 553 }
 554
 555  ///////////////////////////////////////////////////////////////////////
 556 /*
 557  *Prepare the Chip to send specified Message over specified Messageobject
 558  *In this version the method also sends the message.
 559  */
 560
 561 int c_can_send_msg(struct canchip_t *pchip, struct msgobj_t *pmsgobj,
 562                    struct canmsg_t *pmsg)
 563 {
 564         unsigned short readMaskCM =
 565             IFXCM_CNTRL | IFXCM_ARB | IFXCM_DA | IFXCM_DB;
 566         unsigned short writeMaskCM =
 567             IFXCM_CNTRL | IFXCM_ARB | IFXCM_DA | IFXCM_DB | IFXCM_WRRD;
 568         unsigned short writeSendMskCM =
 569             IFXCM_CNTRL | IFXCM_ARB | IFXCM_DA | IFXCM_DB | IFXCM_WRRD |
 570             IFXCM_TRND;
 571         unsigned short mcreg = 0;
 572         //unsigned short arbreg = 0;
 573         unsigned short dataA1 = 0;
 574         unsigned short dataA2 = 0;
 575         unsigned short dataB1 = 0;
 576         unsigned short dataB2 = 0;
 577
 578         DEBUGMSG("(c%dm%d)calling c_can_send_msg(...)\n",
 579                  pmsgobj->hostchip->chip_idx, pmsgobj->object);
 580
 581         spin_lock(&c_can_if2lock);
 582
 583         can_msgobj_clear_fl(pmsgobj, RX_MODE);
 584
 585         //loading Message Object in IF1
 586         if (c_can_if2_busycheck(pmsgobj->hostchip))
 587                 return -ENODEV;
 588         c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF2CM);
 589         c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF2CR);
 590         //setting Message Valid Bit to zero
 591         if (c_can_if2_busycheck(pmsgobj->hostchip))
 592                 return -ENODEV;
 593         c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF2A2);
 594         c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF2CM);
 595         c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF2CR);
 596         //Configuring MO
 597         if (c_can_if2_busycheck(pmsgobj->hostchip))
 598                 return -ENODEV;
 599         mcreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF2CM);
 600         //remote enable?
 601         //define Command Mask
 602         c_can_write_reg_w(pmsgobj->hostchip,
 603                           (mcreg & IFXMC_UMASK) | IFXMC_EOB | IFXMC_TXIE |
 604                           IFXMC_RMTEN | IFXMC_NEWDAT | IFXMC_TXRQST | (pmsg->
 605                                                                        length &
 606                                                                        0xF),
 607                           CCIF2DMC);
 608         //set Arbitration Bits
 609         if (can_msgobj_test_fl(pmsgobj, RX_MODE_EXT)) {
 610                 c_can_write_reg_w(pmsgobj->hostchip, (u16) (pmsg->id), CCIF2A1);
 611                 c_can_write_reg_w(pmsgobj->hostchip,
 612                                   IFXARB2_XTD | IFXARB2_MVAL | IFXARB2_DIR |
 613                                   ((u16) (pmsg->id >> 16) & 0x1FFF), CCIF2A2);
 614         } else {
 615                 c_can_write_reg_w(pmsgobj->hostchip,
 616                                   (IFXARB2_MVAL | IFXARB2_DIR |
 617                                    ((u16) (pmsg->id << 2) & 0x1FFC)), CCIF2A2);
 618                 c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF1A1);
 619         }
 620         //write Data
 621         if (pmsg->length > 0) {
 622                 dataA1 = pmsg->data[0] | (u16) pmsg->data[1] << 8;
 623                 dataA2 = pmsg->data[2] | (u16) pmsg->data[3] << 8;
 624                 dataB1 = pmsg->data[4] | (u16) pmsg->data[5] << 8;
 625                 dataB2 = pmsg->data[6] | (u16) pmsg->data[7] << 8;
 626
 627                 c_can_write_reg_w(pmsgobj->hostchip, dataA1, CCIF2DA1);
 628                 c_can_write_reg_w(pmsgobj->hostchip, dataA2, CCIF2DA2);
 629                 c_can_write_reg_w(pmsgobj->hostchip, dataB1, CCIF2DB1);
 630                 c_can_write_reg_w(pmsgobj->hostchip, dataB2, CCIF2DB2);
 631         }
 632
 633         c_can_write_reg_w(pmsgobj->hostchip, writeSendMskCM, CCIF2CM);
 634         c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF2CR);
 635
 636         spin_unlock(&c_can_if2lock);
 637
 638         DEBUGMSG("-> ok\n");
 639 #ifdef REGDUMP
 640         c_can_registerdump(pmsgobj->hostchip);
 641 #endif
 642
 643         return 0;
 644 }
 645
 646 //////////////////////////////////////////////////////////////////////
 647 int c_can_remote_request(struct canchip_t *pchip, struct msgobj_t *pmsgobj)
 648 {
 649         unsigned short readMaskCM = IFXCM_CNTRL;        // | IFXCM_ARB;
 650         //unsigned short writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_WRRD;
 651         unsigned short mcreg = 0;
 652
 653         DEBUGMSG("(c%dm%d)calling c_can_remote_request(...)\n",
 654                  pmsgobj->hostchip->chip_idx, pmsgobj->object);
 655
 656         //Remote request is only available when the message object is in receiving mode
 657         if (!can_msgobj_test_fl(pmsgobj, RX_MODE)) {
 658                 return 1;
 659         }
 660
 661         spin_lock(&c_can_if1lock);
 662
 663         //loading Message Object in IF1
 664         if (c_can_if1_busycheck(pmsgobj->hostchip))
 665                 return -ENODEV;
 666         c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF1CM);
 667         c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
 668         //setting Transmit-Request-Bit
 669         if (c_can_if1_busycheck(pmsgobj->hostchip))
 670                 return -ENODEV;
 671         mcreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1DMC);
 672         c_can_write_reg_w(pmsgobj->hostchip, mcreg | IFXMC_TXRQST, CCIF1DMC);
 673
 674         c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
 675
 676         spin_unlock(&c_can_if1lock);
 677
 678         DEBUGMSG("-> Sent remote request through message object %d\n",
 679                  pmsgobj->object);
 680 #ifdef REGDUMP
 681         c_can_registerdump(pmsgobj->hostchip);
 682 #endif
 683
 684         return 0;
 685 }
 686
 687 ///////////////////////////////////////////////////////////////////////
 688 int c_can_set_btregs(struct canchip_t *pchip, u16 btr0, u16 btr1)
 689 {
 690         unsigned short tempCR = 0;
 691
 692         DEBUGMSG("(c%d)calling c_can_set_btregs(...)\n", pchip->chip_idx);
 693
 694         // Validate pointer
 695         if (NULL == pchip)
 696                 return -1;
 697
 698         if (c_can_enable_configuration(pchip))
 699                 return -ENODEV;
 700
 701         //read Control Register
 702         tempCR = c_can_read_reg_w(pchip, CCCR);
 703         //Configuration Change Enable
 704         c_can_write_reg_w(pchip, tempCR | CR_CCE, CCCR);
 705         c_can_write_reg_w(pchip, btr0 | (btr1 << 8), CCBT);
 706
 707         if (c_can_disable_configuration(pchip))
 708                 return -ENODEV;
 709
 710         DEBUGMSG("-> ok\n");
 711         return 0;
 712 }
 713
 714 ///////////////////////////////////////////////////////////////////////
 715 /*
 716  * Starts the Chip, by setting the CAN Enable Bit
 717  */
 718 int c_can_start_chip(struct canchip_t *pchip)
 719 {
 720         u16 flags = 0;
 721
 722         DEBUGMSG("(c%d)calling c_can_start_chip(...)\n", pchip->chip_idx);
 723
 724         // Validate pointer
 725         if (NULL == pchip) {
 726                 DEBUGMSG("-> Error Chip not available.\n");
 727                 return -1;
 728         }
 729 #ifdef C_CAN_WITH_CCCE
 730         flags = c_can_read_reg_w(pchip, CCCE) | CE_EN;
 731         c_can_write_reg_w(pchip, flags, CCCE);
 732 #endif
 733
 734         DEBUGMSG("-> ok\n");
 735 #ifdef REGDUMP
 736         c_can_registerdump(pchip);
 737 #endif
 738
 739         return 0;
 740 }
 741
 742 ///////////////////////////////////////////////////////////////////////
 743 /*
 744  * Stops the Chip, by deleting the CAN Enable Bit
 745  */
 746 int c_can_stop_chip(struct canchip_t *pchip)
 747 {
 748         u16 flags = 0;
 749
 750         DEBUGMSG("(c%d)calling c_can_stop_chip(...)\n", pchip->chip_idx);
 751
 752         // Validate pointer
 753         if (NULL == pchip) {
 754                 DEBUGMSG("-> Error Chip not available.\n");
 755                 return -1;
 756         }
 757 #ifdef C_CAN_WITH_CCCE
 758         flags = c_can_read_reg_w(pchip, CCCE) & ~CE_EN;
 759         c_can_write_reg_w(pchip, flags, CCCE);
 760 #endif
 761
 762         DEBUGMSG("-> ok\n");
 763         return 0;
 764 }
 765
 766 int c_can_attach_to_chip(struct canchip_t *chip)
 767 {
 768         return 0;
 769 }
 770
 771 int c_can_release_chip(struct canchip_t *chip)
 772 {
 773         int temp;
 774
 775         temp = c_can_read_reg_w(chip, CCCR);
 776
 777         /* Disable IRQ generation */
 778         c_can_config_irqs(chip, 0);
 779
 780         temp = c_can_read_reg_w(chip, CCCR);
 781
 782         /* Power-down C_CAN, except this does nothing in the version 1.2 */
 783         c_can_stop_chip(chip);
 784
 785         return 0;
 786 }
 787
 788 ///////////////////////////////////////////////////////////////////////
 789 /*
 790  *Check the TxOK bit of the Status Register and resets it afterwards.
 791  */
 792 int c_can_check_tx_stat(struct canchip_t *pchip)
 793 {
 794         unsigned long tempstat = 0;
 795
 796         DEBUGMSG("(c%d)calling c_can_check_tx_stat(...)\n", pchip->chip_idx);
 797
 798         // Validate pointer
 799         if (NULL == pchip)
 800                 return -1;
 801
 802         tempstat = c_can_read_reg_w(pchip, CCSR);
 803
 804         if (tempstat & SR_TXOK) {
 805                 c_can_write_reg_w(pchip, tempstat & ~SR_TXOK, CCSR);
 806                 return 0;
 807         } else {
 808                 return 1;
 809         }
 810 }
 811
 812 ///////////////////////////////////////////////////////////////////////
 813 int c_can_wakeup_tx(struct canchip_t *chip, struct msgobj_t *obj)
 814 {
 815         can_preempt_disable();
 816
 817         can_msgobj_set_fl(obj, TX_REQUEST);
 818
 819         /* calls c_can_irq_write_handler synchronized with other invocations
 820            from kernel and IRQ context */
 821         c_can_irq_sync_activities(chip, obj);
 822
 823         can_preempt_enable();
 824         return 0;
 825 }
 826
 827 ///////////////////////////////////////////////////////////////////////
 828 int c_can_filtch_rq(struct canchip_t *chip, struct msgobj_t *obj)
 829 {
 830         can_preempt_disable();
 831
 832         can_msgobj_set_fl(obj, FILTCH_REQUEST);
 833
 834         /* setups filter synchronized with other invocations from kernel and IRQ context */
 835         c_can_irq_sync_activities(chip, obj);
 836
 837         can_preempt_enable();
 838         return 0;
 839 }
 840
 841 ///////////////////////////////////////////////////////////////////////
 842 void c_can_registerdump(struct canchip_t *pchip)
 843 {
 844         CANMSG("------------------------------------\n");
 845         CANMSG("---------C-CAN Register Dump--------\n");
 846         CANMSG("------------at 0x%.8lx-----------\n",
 847                (unsigned long)pchip->chip_base_addr);
 848         CANMSG("Control Register:             0x%.4lx\n",
 849                (long)(c_can_read_reg_w(pchip, CCCR)));
 850         CANMSG("Status Register:              0x%.4lx\n",
 851                (long)(c_can_read_reg_w(pchip, CCSR)));
 852         CANMSG("Error Counting Register:      0x%.4lx\n",
 853                (long)(c_can_read_reg_w(pchip, CCEC)));
 854         CANMSG("Bit Timing Register:          0x%.4lx\n",
 855                (long)(c_can_read_reg_w(pchip, CCBT)));
 856         CANMSG("Interrupt Register:           0x%.4lx\n",
 857                (long)(c_can_read_reg_w(pchip, CCINTR)));
 858         CANMSG("Test Register:                0x%.4lx\n",
 859                (long)(c_can_read_reg_w(pchip, CCTR)));
 860         CANMSG("Baud Rate Presc. Register:    0x%.4lx\n",
 861                (long)(c_can_read_reg_w(pchip, CCBRPE)));
 862 #ifdef C_CAN_WITH_CCCE
 863         CANMSG("CAN Enable Register:          0x%.4lx\n",
 864                (long)(c_can_read_reg_w(pchip, CCCE)));
 865 #endif
 866         CANMSG("Transm. Req. 1 Register:      0x%.4lx\n",
 867                (long)(c_can_read_reg_w(pchip, CCTREQ1)));
 868         CANMSG("Transm. Req. 2 Register:      0x%.4lx\n",
 869                (long)(c_can_read_reg_w(pchip, CCTREQ2)));
 870         CANMSG("New Data 1 Register:          0x%.4lx\n",
 871                (long)(c_can_read_reg_w(pchip, CCND1)));
 872         CANMSG("New Data 2 Register:          0x%.4lx\n",
 873                (long)(c_can_read_reg_w(pchip, CCND2)));
 874         CANMSG("Interrupt Pend. 1 Register:   0x%.4lx\n",
 875                (long)(c_can_read_reg_w(pchip, CCINTP1)));
 876         CANMSG("Interrupt Pend. 2 Register:   0x%.4lx\n",
 877                (long)(c_can_read_reg_w(pchip, CCINTP2)));
 878         CANMSG("------------------------------------\n");
 879         CANMSG("IF1 Command Req. Register:    0x%.4lx\n",
 880                (long)(c_can_read_reg_w(pchip, CCIF1CR)));
 881         CANMSG("IF1 Command Mask Register:    0x%.4lx\n",
 882                (long)(c_can_read_reg_w(pchip, CCIF1CM)));
 883         CANMSG("IF1 Mask 1 Register:          0x%.4lx\n",
 884                (long)(c_can_read_reg_w(pchip, CCIF1M1)));
 885         CANMSG("IF1 Mask 2 Register:          0x%.4lx\n",
 886                (long)(c_can_read_reg_w(pchip, CCIF1M2)));
 887         CANMSG("IF1 Arbitration 1 Register:   0x%.4lx\n",
 888                (long)(c_can_read_reg_w(pchip, CCIF1A1)));
 889         CANMSG("IF1 Arbitration 2 Register:   0x%.4lx\n",
 890                (long)(c_can_read_reg_w(pchip, CCIF1A2)));
 891         CANMSG("IF1 Message Control Register: 0x%.4lx\n",
 892                (long)(c_can_read_reg_w(pchip, CCIF1DMC)));
 893         CANMSG("IF1 Data A1 Register:         0x%.4lx\n",
 894                (long)(c_can_read_reg_w(pchip, CCIF1DA1)));
 895         CANMSG("IF1 Data A2 Register:         0x%.4lx\n",
 896                (long)(c_can_read_reg_w(pchip, CCIF1DA2)));
 897         CANMSG("IF1 Data B1 Register:         0x%.4lx\n",
 898                (long)(c_can_read_reg_w(pchip, CCIF1DB1)));
 899         CANMSG("IF1 Data B2 Register:         0x%.4lx\n",
 900                (long)(c_can_read_reg_w(pchip, CCIF1DB2)));
 901         CANMSG("------------------------------------\n");
 902         CANMSG("IF2 Command Req. Register:    0x%.4lx\n",
 903                (long)(c_can_read_reg_w(pchip, CCIF2CR)));
 904         CANMSG("IF2 Command Mask Register:    0x%.4lx\n",
 905                (long)(c_can_read_reg_w(pchip, CCIF2CM)));
 906         CANMSG("IF2 Mask 1 Register:          0x%.4lx\n",
 907                (long)(c_can_read_reg_w(pchip, CCIF2M1)));
 908         CANMSG("IF2 Mask 2 Register:          0x%.4lx\n",
 909                (long)(c_can_read_reg_w(pchip, CCIF2M2)));
 910         CANMSG("IF2 Arbitration 1 Register:   0x%.4lx\n",
 911                (long)(c_can_read_reg_w(pchip, CCIF2A1)));
 912         CANMSG("IF2 Arbitration 2 Register:   0x%.4lx\n",
 913                (long)(c_can_read_reg_w(pchip, CCIF2A2)));
 914         CANMSG("IF2 Message Control Register: 0x%.4lx\n",
 915                (long)(c_can_read_reg_w(pchip, CCIF2DMC)));
 916         CANMSG("IF2 Data A1 Register:         0x%.4lx\n",
 917                (long)(c_can_read_reg_w(pchip, CCIF2DA1)));
 918         CANMSG("IF2 Data A2 Register:         0x%.4lx\n",
 919                (long)(c_can_read_reg_w(pchip, CCIF2DA2)));
 920         CANMSG("IF2 Data B1 Register:         0x%.4lx\n",
 921                (long)(c_can_read_reg_w(pchip, CCIF2DB1)));
 922         CANMSG("IF2 Data B2 Register:         0x%.4lx\n",
 923                (long)(c_can_read_reg_w(pchip, CCIF2DB2)));
 924         CANMSG("------------------------------------\n");
 925         CANMSG("------------------------------------\n");
 926 }
 927
 928 void c_can_if1_registerdump(struct canchip_t *pchip)
 929 {
 930         CANMSG("----------------------------------------\n");
 931         CANMSG("Error Counting Register:      0x%.4lx\n",
 932                (long)(c_can_read_reg_w(pchip, CCEC)));
 933         CANMSG("---------C-CAN IF1 Register Dump--------\n");
 934         CANMSG("IF1 Command Req. Register:    0x%.4lx\n",
 935                (long)(c_can_read_reg_w(pchip, CCIF1CR)));
 936         CANMSG("IF1 Command Mask Register:    0x%.4lx\n",
 937                (long)(c_can_read_reg_w(pchip, CCIF1CM)));
 938         CANMSG("IF1 Mask 1 Register:          0x%.4lx\n",
 939                (long)(c_can_read_reg_w(pchip, CCIF1M1)));
 940         CANMSG("IF1 Mask 2 Register:          0x%.4lx\n",
 941                (long)(c_can_read_reg_w(pchip, CCIF1M2)));
 942         CANMSG("IF1 Arbitration 1 Register:   0x%.4lx\n",
 943                (long)(c_can_read_reg_w(pchip, CCIF1A1)));
 944         CANMSG("IF1 Arbitration 2 Register:   0x%.4lx\n",
 945                (long)(c_can_read_reg_w(pchip, CCIF1A2)));
 946         CANMSG("IF1 Message Control Register: 0x%.4lx\n",
 947                (long)(c_can_read_reg_w(pchip, CCIF1DMC)));
 948         CANMSG("IF1 Data A1 Register:         0x%.4lx\n",
 949                (long)(c_can_read_reg_w(pchip, CCIF1DA1)));
 950         CANMSG("IF1 Data A2 Register:         0x%.4lx\n",
 951                (long)(c_can_read_reg_w(pchip, CCIF1DA2)));
 952         CANMSG("IF1 Data B1 Register:         0x%.4lx\n",
 953                (long)(c_can_read_reg_w(pchip, CCIF1DB1)));
 954         CANMSG("IF1 Data B2 Register:         0x%.4lx\n",
 955                (long)(c_can_read_reg_w(pchip, CCIF1DB2)));
 956 }
 957
 958 ///////////////////////////////////////////////////////////////////////
 959
 960 int c_can_register(struct chipspecops_t *chipspecops)
 961 {
 962         CANMSG("initializing c_can chip operations\n");
 963         chipspecops->chip_config = c_can_chip_config;
 964         chipspecops->baud_rate = c_can_baud_rate;
 965         /*chipspecops->standard_mask=c_can_standard_mask;
 966            chipspecops->extended_mask=c_can_extended_mask;
 967            chipspecops->message15_mask=c_can_extended_mask; */
 968         chipspecops->clear_objects = c_can_clear_objects;
 969         /*chipspecops->config_irqs=c_can_config_irqs; */
 970         chipspecops->pre_read_config = c_can_pre_read_config;
 971         chipspecops->pre_write_config = c_can_pre_write_config;
 972         chipspecops->send_msg = c_can_send_msg;
 973         chipspecops->check_tx_stat = c_can_check_tx_stat;
 974         chipspecops->wakeup_tx = c_can_wakeup_tx;
 975         chipspecops->filtch_rq = c_can_filtch_rq;
 976         chipspecops->remote_request = c_can_remote_request;
 977         chipspecops->enable_configuration = c_can_enable_configuration;
 978         chipspecops->disable_configuration = c_can_disable_configuration;
 979         chipspecops->attach_to_chip = c_can_attach_to_chip;
 980         chipspecops->release_chip = c_can_release_chip;
 981         chipspecops->set_btregs = c_can_set_btregs;
 982         chipspecops->start_chip = c_can_start_chip;
 983         chipspecops->stop_chip = c_can_stop_chip;
 984         chipspecops->irq_handler = c_can_irq_handler;
 985         chipspecops->irq_accept = NULL;
 986         return 0;
 987 }
 988
 989 int c_can_fill_chipspecops(struct canchip_t *chip)
 990 {
 991         chip->chip_type = "c_can";
 992         if (MAX_MSGOBJS >= 32) {
 993                 chip->max_objects = 32;
 994         } else {
 995                 CANMSG("C_CAN requires 32 message objects per chip,"
 996                        " but only %d is compiled maximum\n", MAX_MSGOBJS);
 997                 chip->max_objects = MAX_MSGOBJS;
 998         }
 999         c_can_register(chip->chipspecops);
1000         return 0;
1001 }