2 * Linux CAN-bus device driver.
3 * Written by Arnaud Westenberg email:arnaud@wnadoo.nl
4 * This software is released under the GPL-License.
5 * Version 0.7 6 Aug 2001
8 #include <linux/autoconf.h>
9 #if defined (CONFIG_MODVERSIONS) && !defined (MODVERSIONS)
13 #if defined (MODVERSIONS)
14 #include <linux/modversions.h>
17 #include <linux/ioport.h>
18 #include <linux/delay.h>
19 #include <asm/errno.h>
22 #include "../include/main.h"
23 #include "../include/pc-i03.h"
24 #include "../include/sja1000.h"
26 /* Basic hardware io address. This is also stored in the hardware structure but
27 * we need it global, else we have to change many internal functions.
28 * pc-i03_base_addr is initialized in pc-i03_init_chip_data().
30 unsigned int pci03_base_addr;
33 * IO_RANGE is the io-memory range that gets reserved, please adjust according
34 * your hardware. Example: #define IO_RANGE 0x100 for i82527 chips or
35 * #define IO_RANGE 0x20 for sja1000 chips in basic CAN mode.
37 #define IO_RANGE 0x200 // The pc-i03 uses an additional 0x100 bytes reset space
40 * pci03_request_io: - reserve io memory
41 * @io_addr: The reserved memory starts at @io_addr, wich is the module
44 * The function pci03_request_io() is used to reserve the io-memory. If your
45 * hardware uses a dedicated memory range as hardware control registers you
46 * will have to add the code to reserve this memory as well.
47 * %IO_RANGE is the io-memory range that gets reserved, please adjust according
48 * your hardware. Example: #define IO_RANGE 0x100 for i82527 chips or
49 * #define IO_RANGE 0x20 for sja1000 chips in basic CAN mode.
50 * Return Value: The function returns zero on success or %-ENODEV on failure
53 int pci03_request_io(unsigned long io_addr)
55 if (check_region(io_addr,IO_RANGE)) {
56 CANMSG("Unable to open port: 0x%lx\n",io_addr);
60 request_region(io_addr,IO_RANGE,DEVICE_NAME);
61 DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", io_addr, io_addr + IO_RANGE - 1);
67 * pci03_release_io - free reserved io-memory
68 * @io_addr: Start of the memory range to be released.
70 * The function pci03_release_io() is used to free reserved io-memory.
71 * In case you have reserved more io memory, don't forget to free it here.
72 * IO_RANGE is the io-memory range that gets released, please adjust according
73 * your hardware. Example: #define IO_RANGE 0x100 for i82527 chips or
74 * #define IO_RANGE 0x20 for sja1000 chips in basic CAN mode.
75 * Return Value: The function always returns zero
78 int pci03_release_io(unsigned long io_addr)
80 release_region(io_addr,IO_RANGE);
86 * pci03_reset - hardware reset routine
87 * @card: Number of the hardware card.
89 * The function pci03_reset() is used to give a hardware reset. This is
90 * rather hardware specific so I haven't included example code. Don't forget to
91 * check the reset status of the chip before returning.
92 * Return Value: The function returns zero on success or %-ENODEV on failure
95 int pci03_reset(int card)
99 DEBUGMSG("Resetting pc-i03 hardware ...\n");
100 pci03_write_register(0x01,pci03_base_addr +
101 0x100); // Write arbitrary data to reset mem
104 pci03_write_register(0x00, pci03_base_addr + SJACR);
106 /* Check hardware reset status */
108 while ( (pci03_read_register(pci03_base_addr + SJACR) & CR_RR)
114 CANMSG("Reset status timeout!\n");
115 CANMSG("Please check your hardware.\n");
119 DEBUGMSG("Chip[0] reset status ok.\n");
124 #define RESET_ADDR 0x100
129 * pci03_init_hw_data - Initialze hardware cards
130 * @card: Number of the hardware card.
132 * The function pci03_init_hw_data() is used to initialize the hardware
133 * structure containing information about the installed CAN-board.
134 * %RESET_ADDR represents the io-address of the hardware reset register.
135 * %NR_82527 represents the number of intel 82527 chips on the board.
136 * %NR_SJA1000 represents the number of philips sja1000 chips on the board.
137 * The flags entry can currently only be %PROGRAMMABLE_IRQ to indicate that
138 * the hardware uses programmable interrupts.
139 * Return Value: The function always returns zero
142 int pci03_init_hw_data(int card)
144 candevices_p[card]->res_addr=RESET_ADDR;
145 candevices_p[card]->nr_82527_chips=NR_82527;
146 candevices_p[card]->nr_sja1000_chips=NR_SJA1000;
147 candevices_p[card]->flags |= ~PROGRAMMABLE_IRQ;
152 #define CHIP_TYPE "sja1000"
154 * pci03_init_chip_data - Initialize chips
155 * @card: Number of the hardware card
156 * @chipnr: Number of the CAN chip on the hardware card
158 * The function pci03_init_chip_data() is used to initialize the hardware
159 * structure containing information about the CAN chips.
160 * %CHIP_TYPE represents the type of CAN chip. %CHIP_TYPE can be "i82527" or
162 * The @chip_base_addr entry represents the start of the 'official' memory map
163 * of the installed chip. It's likely that this is the same as the @io_addr
164 * argument supplied at module loading time.
165 * The @clock entry holds the chip clock value in Hz.
166 * The entry @sja_cdr_reg holds hardware specific options for the Clock Divider
167 * register. Options defined in the %sja1000.h file:
168 * %CDR_CLKOUT_MASK, %CDR_CLK_OFF, %CDR_RXINPEN, %CDR_CBP, %CDR_PELICAN
169 * The entry @sja_ocr_reg holds hardware specific options for the Output Control
170 * register. Options defined in the %sja1000.h file:
171 * %OCR_MODE_BIPHASE, %OCR_MODE_TEST, %OCR_MODE_NORMAL, %OCR_MODE_CLOCK,
172 * %OCR_TX0_LH, %OCR_TX1_ZZ.
173 * The entry @int_clk_reg holds hardware specific options for the Clock Out
174 * register. Options defined in the %i82527.h file:
175 * %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1.
176 * The entry @int_bus_reg holds hardware specific options for the Bus
177 * Configuration register. Options defined in the %i82527.h file:
178 * %iBUS_DR0, %iBUS_DR1, %iBUS_DT1, %iBUS_POL, %iBUS_CBY.
179 * Return Value: The function always returns zero
182 int pci03_init_chip_data(int card, int chipnr)
184 pci03_base_addr = candevices_p[card]->io_addr;
185 candevices_p[card]->chip[chipnr]->chip_type=CHIP_TYPE;
186 candevices_p[card]->chip[chipnr]->chip_base_addr=candevices_p[card]->io_addr;
187 candevices_p[card]->chip[chipnr]->clock = 16000000;
188 candevices_p[card]->chip[chipnr]->sja_cdr_reg = CDR_CBP | CDR_CLK_OFF;
189 candevices_p[card]->chip[chipnr]->sja_ocr_reg = OCR_MODE_NORMAL |
190 OCR_TX0_HL | OCR_TX1_LZ;
196 * pci03_init_obj_data - Initialize message buffers
197 * @chipnr: Number of the CAN chip
198 * @objnr: Number of the message buffer
200 * The function pci03_init_obj_data() is used to initialize the hardware
201 * structure containing information about the different message objects on the
202 * CAN chip. In case of the sja1000 there's only one message object but on the
203 * i82527 chip there are 15.
204 * The code below is for a i82527 chip and initializes the object base addresses
205 * The entry @obj_base_addr represents the first memory address of the message
206 * object. In case of the sja1000 @obj_base_addr is taken the same as the chips
208 * Unless the hardware uses a segmented memory map, flags can be set zero.
209 * Return Value: The function always returns zero
212 int pci03_init_obj_data(int chipnr, int objnr)
214 chips_p[chipnr]->msgobj[objnr]->obj_base_addr=chips_p[chipnr]->chip_base_addr;
215 chips_p[chipnr]->msgobj[objnr]->flags=0;
221 * pci03_program_irq - program interrupts
222 * @card: Number of the hardware card.
224 * The function pci03_program_irq() is used for hardware that uses
225 * programmable interrupts. If your hardware doesn't use programmable interrupts
226 * you should not set the @candevices_t->flags entry to %PROGRAMMABLE_IRQ and
227 * leave this function unedited. Again this function is hardware specific so
228 * there's no example code.
229 * Return value: The function returns zero on success or %-ENODEV on failure
232 int pci03_program_irq(int card)
238 * pci03_write_register - Low level write register routine
239 * @data: data to be written
240 * @address: memory address to write to
242 * The function pci03_write_register() is used to write to hardware registers
243 * on the CAN chip. You should only have to edit this function if your hardware
244 * uses some specific write process.
245 * Return Value: The function does not return a value
248 void pci03_write_register(unsigned char data, unsigned long address)
250 unsigned int *pci03_base_ptr;
251 unsigned short address_to_write;
253 /* The read/write functions are called by an extra abstract function.
254 * This extra function adds the basic io address of the card to the
255 * memory address we want to write to, so we substract the basic io
256 * address again to obtain the offset into the hardware's memory map.
258 address_to_write = address - pci03_base_addr; // Offset
259 pci03_base_ptr = (unsigned int *)(pci03_base_addr * 0x100001);
260 (*(pci03_base_ptr+address_to_write)) = data;
264 * pci03_read_register - Low level read register routine
265 * @address: memory address to read from
267 * The function pci03_read_register() is used to read from hardware registers
268 * on the CAN chip. You should only have to edit this function if your hardware
269 * uses some specific read process.
270 * Return Value: The function returns the value stored in @address
273 unsigned pci03_read_register(unsigned long address)
275 unsigned int *pci03_base_ptr;
276 unsigned short address_to_read;
278 /* The read/write functions are called by an extra abstract function.
279 * This extra function adds the basic io address of the card to the
280 * memory address we want to write to, so we substract the basic io
281 * address again to obtain the offset into the hardware's memory map.
283 address_to_read = address - pci03_base_addr;
284 pci03_base_ptr = (unsigned int *)(pci03_base_addr * 0x100001);
285 return (*(pci03_base_ptr+address_to_read));
288 int pci03_register(struct hwspecops_t *hwspecops)
290 hwspecops->request_io = pci03_request_io;
291 hwspecops->release_io = pci03_release_io;
292 hwspecops->reset = pci03_reset;
293 hwspecops->init_hw_data = pci03_init_hw_data;
294 hwspecops->init_chip_data = pci03_init_chip_data;
295 hwspecops->init_obj_data = pci03_init_obj_data;
296 hwspecops->write_register = pci03_write_register;
297 hwspecops->read_register = pci03_read_register;
298 hwspecops->program_irq = pci03_program_irq;