2 * Header file for the Linux CAN-bus driver.
3 * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
4 * Added by T.Motylewski@bfad.de
5 * See app. note an97076.pdf from Philips Semiconductors
6 * and SJA1000 data sheet
8 * This software is released under the GPL-License.
9 * Version lincan-0.3 17 Jun 2004
12 int sja1000p_chip_config(struct chip_t *chip);
13 int sja1000p_extended_mask(struct chip_t *chip, unsigned long code, unsigned long mask);
14 int sja1000p_baud_rate(struct chip_t *chip, int rate, int clock, int sjw,
15 int sampl_pt, int flags);
16 int sja1000p_pre_read_config(struct chip_t *chip, struct msgobj_t *obj);
17 int sja1000p_pre_write_config(struct chip_t *chip, struct msgobj_t *obj,
18 struct canmsg_t *msg);
19 int sja1000p_send_msg(struct chip_t *chip, struct msgobj_t *obj,
20 struct canmsg_t *msg);
23 enum SJA1000_PeliCAN_regs {
29 /// Interrupt register
33 /// Bus Timing register 0
35 /// Bus Timing register 1
37 /// Output Control register
39 /// Arbitration Lost Capture
41 /// Error Code Capture
43 /// Error Warning Limit
50 /// Rx Message Counter (number of msgs. in RX FIFO
52 /// Rx Buffer Start Addr. (address of current MSG)
54 /// Transmit Buffer (write) Receive Buffer (read) Frame Information
56 /// ID bytes (11 bits in 0 and 1 or 16 bits in 0,1 and 13 bits in 2,3 (extended))
57 SJAID0 = 0x11, SJAID1 = 0x12,
58 /// ID cont. for extended frames
59 SJAID2 = 0x13, SJAID3 = 0x14,
60 /// Data start standard frame
62 /// Data start extended frame
64 /// Acceptance Code (4 bytes) in RESET mode
66 /// Acceptance Mask (4 bytes) in RESET mode
69 SJA_PeliCAN_AC_LEN = 4,
74 /** Mode Register 0x00 */
75 enum sja1000_PeliCAN_MOD {
76 sjaMOD_SM = 1<<4, // Sleep Mode (writable only in OPERATING mode)
77 sjaMOD_AFM= 1<<3, // Acceptance Filter Mode (writable only in RESET)
78 sjaMOD_STM= 1<<2, // Self Test Mode (writable only in RESET)
79 sjaMOD_LOM= 1<<1, // Listen Only Mode (writable only in RESET)
80 sjaMOD_RM = 1 // Reset Mode
83 /** Command Register 0x01 */
84 enum sja1000_PeliCAN_CMR {
85 sjaCMR_SRR= 1<<4, // Self Reception Request (GoToSleep in BASIC mode)
86 sjaCMR_CDO= 1<<3, // Clear Data Overrun
87 sjaCMR_RRB= 1<<2, // Release Receive Buffer
88 sjaCMR_AT = 1<<1, // Abort Transmission
89 sjaCMR_TR = 1 }; // Transmission Request
91 /** Status Register 0x02 */
93 sjaSR_BS = 1<<7, // Bus Status
94 sjaSR_ES = 1<<6, // Error Status
95 sjaSR_TS = 1<<5, // Transmit Status
96 sjaSR_RS = 1<<4, // Receive Status
97 sjaSR_TCS = 1<<3, // Transmission Complete Status
98 sjaSR_TBS = 1<<2, // Transmit Buffer Status
99 sjaSR_DOS = 1<<1, // Data Overrun Status
100 sjaSR_RBS = 1 }; // Receive Buffer Status
102 /** Interrupt Enable Register 0x04 */
103 enum sja1000_PeliCAN_IER {
104 sjaIER_BEIE= 1<<7, // Bus Error Interrupt Enable
105 sjaIER_ALIE= 1<<6, // Arbitration Lost Interrupt Enable
106 sjaIER_EPIE= 1<<5, // Error Passive Interrupt Enable
107 sjaIER_WUIE= 1<<4, // Wake-Up Interrupt Enable
108 sjaIER_DOIE= 1<<3, // Data Overrun Interrupt Enable
109 sjaIER_EIE = 1<<2, // Error Warning Interrupt Enable
110 sjaIER_TIE = 1<<1, // Transmit Interrupt Enable
111 sjaIER_RIE = 1, // Receive Interrupt Enable
112 sjaENABLE_INTERRUPTS = sjaIER_BEIE|sjaIER_EPIE|sjaIER_DOIE|sjaIER_EIE|sjaIER_TIE|sjaIER_RIE,
113 sjaDISABLE_INTERRUPTS = 0
114 // WARNING: the chip automatically enters RESET (bus off) mode when
115 // error counter > 255
118 /** Arbitration Lost Capture Register 0x0b.
119 * Counting starts from 0 (bit1 of ID). Bits 5-7 reserved*/
120 enum sja1000_PeliCAN_ALC {
121 sjaALC_SRTR = 0x0b,// Arbitration lost in bit SRTR
122 sjaALC_IDE = 0x1c, // Arbitration lost in bit IDE
123 sjaALC_RTR = 0x1f, // Arbitration lost in RTR
126 /** Error Code Capture Register 0x0c*/
127 enum sja1000_PeliCAN_ECC {
131 sjaECC_FORM = sjaECC_ERCC0,
132 sjaECC_STUFF = sjaECC_ERCC1,
133 sjaECC_OTHER = sjaECC_ERCC0 | sjaECC_ERCC1,
134 sjaECC_DIR = 1<<5, // 1 == RX, 0 == TX
135 sjaECC_SEG_M = (1<<5) -1 // Segment mask, see page 37 of SJA1000 Data Sheet
138 /** Frame format information 0x10 */
139 enum sja1000_PeliCAN_FRM {
140 sjaFRM_FF = 1<<7, // Frame Format 1 == extended, 0 == standard
141 sjaFRM_RTR = 1<<6, // Remote request
142 sjaFRM_DLC_M = (1<<4)-1 // Length Mask
146 /** Interrupt (status) Register 0x03 */
147 enum sja1000_PeliCAN_IR {
148 sjaIR_BEI = 1<<7, // Bus Error Interrupt
149 sjaIR_ALI = 1<<6, // Arbitration Lost Interrupt
150 sjaIR_EPI = 1<<5, // Error Passive Interrupt (entered error passive state or error active state)
151 sjaIR_WUI = 1<<4, // Wake-Up Interrupt
152 sjaIR_DOI = 1<<3, // Data Overrun Interrupt
153 sjaIR_EI = 1<<2, // Error Interrupt
154 sjaIR_TI = 1<<1, // Transmit Interrupt
155 sjaIR_RI = 1 // Receive Interrupt
158 /** Bus Timing 1 Register 0x07 */
164 /** Output Control Register 0x08 */
166 sjaOCR_MODE_BIPHASE = 0,
167 sjaOCR_MODE_TEST = 1,
168 sjaOCR_MODE_NORMAL = 2,
169 sjaOCR_MODE_CLOCK = 3,
170 /// TX0 push-pull not inverted
171 sjaOCR_TX0_LH = 0x18,
172 /// TX1 floating (off)
176 /** Clock Divider register 0x1f */
178 sjaCDR_PELICAN = 1<<7,
179 /// bypass input comparator
181 /// switch TX1 to generate RX INT
182 sjaCDR_RXINPEN = 1<<5,
183 sjaCDR_CLK_OFF = 1<<3,
184 /// f_out = f_osc/(2*(CDR[2:0]+1)) or f_osc if CDR[2:0]==7
185 sjaCDR_CLKOUT_MASK = 7
188 /** flags for sja1000_baud_rate */
189 #define BTR1_SAM (1<<1)