1 /* c_can.c - Hynix HMS30c7202 ARM generic C_CAN module handling
2 * Linux CAN-bus device driver.
3 * Written by Sebastian Stolzenberg email:stolzi@sebastian-stolzenberg.de
4 * Based on code from Arnaud Westenberg email:arnaud@wanadoo.nl
5 * and Ake Hedman, eurosource, akhe@eurosource.se
6 * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
7 * email:pisa@cmp.felk.cvut.cz
8 * This software is released under the GPL-License.
9 * Version lincan-0.3 17 Jun 2004
12 #define __NO_VERSION__
14 #include "../include/can.h"
15 #include "../include/can_sysdep.h"
16 #include "../include/main.h"
17 #include "../include/c_can.h"
22 can_spinlock_t c_can_spwlock=SPIN_LOCK_UNLOCKED; // Spin lock for write operations
23 can_spinlock_t c_can_sprlock=SPIN_LOCK_UNLOCKED; // Spin lock for read operations
24 can_spinlock_t c_can_if1lock=SPIN_LOCK_UNLOCKED; // spin lock for the if1 register
25 can_spinlock_t c_can_if2lock=SPIN_LOCK_UNLOCKED; // spin lcok for the if2 register
28 * c_can_enable_configuration - enable chip configuration mode
29 * @pchip: pointer to chip state structure
31 int c_can_enable_configuration(struct canchip_t *pchip)
35 DEBUGMSG("(c%d)calling c_can_enable_configuration(...)\n", pchip->chip_idx);
37 DEBUGMSG("Trying disable_irq(...) : ");
39 disable_irq(chip->chip_irq);
41 //read Control Register
42 flags=c_can_read_reg_w(pchip, CCCR);
43 //set Init-Bit in the Control Register (10 tries)
44 while ((!(flags & CR_INIT)) && (i<=10))
46 c_can_write_reg_w(pchip,flags|CR_INIT, CCCR);
49 flags=c_can_read_reg_w(pchip, CCCR);
53 CANMSG("Reset error\n");
54 //enable_irq(chip->chip_irq);
62 ///////////////////////////////////////////////////////////////////////
63 int c_can_disable_configuration(struct canchip_t *pchip)
68 DEBUGMSG("(c%d)calling c_can_disable_configuration(...)\n", pchip->chip_idx);
69 //read Control Register
70 flags=c_can_read_reg_w(pchip, CCCR);
72 //reset Init-Bit in the Control Register (10 tries)
73 while ( (flags & CR_INIT) && (i<=10) )
75 c_can_write_reg_w( pchip,flags & ~CR_INIT, CCCR);
76 udelay(1000); //100 microseconds
78 flags=c_can_read_reg_w(pchip, CCCR);
82 CANMSG("Error leaving reset status\n");
87 //enable_irq(chip->chip_irq);
92 ///////////////////////////////////////////////////////////////////////
93 int c_can_chip_config(struct canchip_t *pchip)
96 DEBUGMSG("(c%d)calling c_can_chip_config(...)\n", pchip->chip_idx);
98 if ( NULL == pchip ) return -1;
100 if (pchip->baudrate == 0)
101 pchip->baudrate=1000;
103 if (c_can_baud_rate(pchip,pchip->baudrate*1000,pchip->clock,0,75,0))
105 CANMSG("Error configuring baud rate\n");
109 if (c_can_extended_mask(pchip,0x0000000,extmask)) {
110 CANMSG("Error configuring extended mask\n");
114 if (c_can_standard_mask(pchip,0x0000,stdmask)) {
115 CANMSG("Error configuring standard mask\n");
119 if (c_can_clear_objects(pchip))
121 CANMSG("Error clearing message objects\n");
124 if (c_can_config_irqs(pchip, CR_MIE | CR_SIE | CR_EIE))
126 CANMSG("Error configuring interrupts\n");
130 DEBUGMSG("-> Configured successfully\n");
133 c_can_registerdump(pchip);
139 ///////////////////////////////////////////////////////////////////////
141 * Checks if the Busy-Bit in the IF1-Command-Request Register is set
143 int c_can_if1_busycheck(struct canchip_t *pchip)
147 unsigned short comreg = 0;
149 comreg = c_can_read_reg_w( pchip, CCIF1CR);
150 while ( (comreg & IFXCR_BUSY) && (i<=10) )
152 udelay(100); //100 microseconds
154 comreg=c_can_read_reg_w( pchip, CCIF1CR);
158 CANMSG("Error Busy-Bit stays set\n");
165 ///////////////////////////////////////////////////////////////////////
167 * Checks if the Busy-Bit in the IF2-Command-Request Register is set
169 int c_can_if2_busycheck(struct canchip_t *pchip)
173 unsigned short comreg = 0;
175 comreg = c_can_read_reg_w( pchip, CCIF2CR);
176 while ( (comreg & IFXCR_BUSY) && (i<=10) )
178 udelay(100); //100 microseconds
180 comreg=c_can_read_reg_w( pchip, CCIF2CR);
184 CANMSG("Error Busy-Bit stays set\n");
191 ///////////////////////////////////////////////////////////////////////
193 * Though the C-CAN Chip can handle one mask for each Message Object, this Method defines
194 * one mask for all MOs. That means every MO gets the same mask.
197 /* Set communication parameters.
198 * param rate baud rate in Hz
199 * param clock frequency of C-CAN clock in Hz
200 * param sjw synchronization jump width (0-3) prescaled clock cycles
201 * param sampl_pt sample point in % (0-100) sets (TSEG1+2)/(TSEG1+TSEG2+3) ratio
202 * param flags fields BTR1_SAM, OCMODE, OCPOL, OCTP, OCTN, CLK_OFF, CBP
204 int c_can_baud_rate(struct canchip_t *pchip, int rate, int clock,
205 int sjw, int sampl_pt, int flags)
207 int best_error = 1000000000, error;
208 int best_tseg=0, best_brp=0, best_rate=0, brp=0;
209 int tseg=0, tseg1=0, tseg2=0;
211 unsigned short tempCR = 0;
213 DEBUGMSG("(c%d)calling c_can_baud_rate(...)\n", pchip->chip_idx);
215 if (c_can_enable_configuration(pchip))
218 /* tseg even = round down, odd = round up */
219 for (tseg=(0+0+2)*2; tseg<=(MAX_TSEG2+MAX_TSEG1+2)*2+1; tseg++)
221 brp = clock/((1+tseg/2)*rate)+tseg%2;
222 if (brp == 0 || brp > 64)
224 error = rate - clock/(brp*(1+tseg/2));
227 if (error <= best_error)
232 best_rate = clock/(brp*(1+tseg/2));
235 if (best_error && (rate/best_error < 10))
237 CANMSG("baud rate %d is not possible with %d Hz clock\n",
239 CANMSG("%d bps. brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d\n",
240 best_rate, best_brp, best_tseg, tseg1, tseg2);
243 tseg2 = best_tseg-(sampl_pt*(best_tseg+1))/100;
246 if (tseg2 > MAX_TSEG2)
248 tseg1 = best_tseg-tseg2-2;
249 if (tseg1 > MAX_TSEG1)
252 tseg2 = best_tseg-tseg1-2;
255 DEBUGMSG("-> Setting %d bps.\n", best_rate);
256 DEBUGMSG("->brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d, sampl_pt=%d\n",
257 best_brp, best_tseg, tseg1, tseg2,
258 (100*(best_tseg-tseg2)/(best_tseg+1)));
260 //read Control Register
261 tempCR = c_can_read_reg_w( pchip, CCCR);
262 //Configuration Change Enable
263 c_can_write_reg_w(pchip, tempCR | CR_CCE, CCCR);
264 c_can_write_reg_w(pchip, ((unsigned short)tseg2)<<12 | ((unsigned short)tseg1)<<8
265 | (unsigned short)sjw<<6 | (unsigned short) best_brp,
268 if (c_can_disable_configuration(pchip))
274 ///////////////////////////////////////////////////////////////////////
275 int c_can_mask(struct msgobj_t *pmsgobj,
279 unsigned short tempreg = 0;
280 unsigned short readMaskCM;
281 unsigned short writeMaskCM;
283 DEBUGMSG("(c%dm%d)calling c_can_mask(...)\n", pmsgobj->hostchip->chip_idx, pmsgobj->object);
285 readMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_MASK;
286 writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_MASK | IFXCM_WRRD;
288 spin_lock( &c_can_if1lock );
290 //load Message Object in IF1
291 if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
292 c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF1CM);
293 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
295 //setting Message Valid Bit to zero
296 if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
297 tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1A2);
298 c_can_write_reg_w(pmsgobj->hostchip, tempreg & ~(IFXARB2_MVAL), CCIF1A2);
299 c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
300 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
302 //setting UMask, MsgVal and Mask Register
303 if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
305 //writing acceptance mask for extended or standart mode
306 if (can_msgobj_test_fl(pmsgobj,RX_MODE_EXT))
309 c_can_write_reg_w(pmsgobj->hostchip,
310 (mask>>16 & 0x1FFF) | IFXMSK2_MXTD | IFXMSK2_MDIR, CCIF1M2);
312 c_can_write_reg_w(pmsgobj->hostchip,
313 (mask>>16 & 0x1FFF) | IFXMSK2_MXTD, CCIF1M2);
314 c_can_write_reg_w(pmsgobj->hostchip, (mask & 0xFFFF), CCIF1M1);
319 c_can_write_reg_w(pmsgobj->hostchip,
320 ((mask<<2) & 0x1FFC) | IFXMSK2_MDIR, CCIF1M2);
322 c_can_write_reg_w(pmsgobj->hostchip,
323 ((mask<<2) & 0x1FFC), CCIF1M2);
324 c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF1M1);
326 //seting Message Valid Bit to one
327 tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1A2);
328 c_can_write_reg_w(pmsgobj->hostchip, tempreg | IFXARB2_MVAL, CCIF1A2);
330 c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
331 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
333 spin_unlock( &c_can_if1lock );
335 DEBUGMSG("-> Setting acceptance mask to 0x%lx\n",(unsigned long)mask);
338 c_can_registerdump(pmsgobj->hostchip);
344 ///////////////////////////////////////////////////////////////////////
345 int c_can_use_mask(struct msgobj_t *pmsgobj,
348 unsigned short tempreg = 0;
349 unsigned short readMaskCM;
350 unsigned short writeMaskCM;
353 char *boolstring = "false";
354 if (useflag) boolstring = "true";
356 DEBUGMSG("(c%dm%d)calling c_can_use_mask(...)\n", pmsgobj->hostchip->chip_idx, pmsgobj->object);
358 readMaskCM = IFXCM_CNTRL | IFXCM_ARB;
359 writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_WRRD;;
361 spin_lock( &c_can_if1lock );
363 //load Message Object in IF1
364 if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
365 c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF1CM);
366 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
368 //setting Message Valid Bit to zero
369 if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
370 tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1A2);
371 c_can_write_reg_w(pmsgobj->hostchip, tempreg & ~IFXARB2_MVAL, CCIF1A2);
372 c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
373 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
376 if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
379 tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1DMC);
380 c_can_write_reg_w(pmsgobj->hostchip, tempreg | IFXMC_UMASK, CCIF1DMC);
384 tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1DMC);
385 c_can_write_reg_w(pmsgobj->hostchip, tempreg & ~IFXMC_UMASK, CCIF1DMC);
387 //seting Message Valid Bit to one
388 tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1A2);
389 c_can_write_reg_w(pmsgobj->hostchip, tempreg | IFXARB2_MVAL, CCIF1A2);
391 c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
392 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
394 spin_unlock( &c_can_if1lock );
397 DEBUGMSG("-> Setting umask bit to %s\n",boolstring);
400 c_can_registerdump(pmsgobj->hostchip);
406 ///////////////////////////////////////////////////////////////////////
407 int c_can_clear_objects(struct canchip_t *pchip)
409 unsigned short i = 0;
410 unsigned short tempreg = 0;
412 unsigned short maskCM = IFXCM_ARB;
414 DEBUGMSG("(c%d)calling c_can_clear_objects(...)\n", pchip->chip_idx);
416 spin_lock( &c_can_if1lock );
417 spin_lock( &c_can_if2lock );
419 for (i=0; i<0x10; i++)
422 //loading Message Objects in IF1 and IF2
423 if (c_can_if1_busycheck(pchip)) return -ENODEV;
424 c_can_write_reg_w(pchip, maskCM, CCIF1CM);
425 c_can_write_reg_w(pchip, i, CCIF1CR);
426 if (c_can_if2_busycheck(pchip)) return -ENODEV;
427 c_can_write_reg_w(pchip, maskCM, CCIF2CM);
428 c_can_write_reg_w(pchip, i+0x10, CCIF2CR);
430 //setting Message Valid Bit to zero
431 if (c_can_if1_busycheck(pchip)) return -ENODEV;
432 tempreg = c_can_read_reg_w(pchip, CCIF1A2);
433 c_can_write_reg_w(pchip, tempreg & ~IFXARB2_MVAL, CCIF1A2);
434 c_can_write_reg_w(pchip, i, CCIF1CR);
435 if (c_can_if2_busycheck(pchip)) return -ENODEV;
436 tempreg = c_can_read_reg_w(pchip, CCIF2A2);
437 c_can_write_reg_w(pchip, tempreg & ~IFXARB2_MVAL, CCIF2A2);
438 c_can_write_reg_w(pchip, i+0x10, CCIF2CR);
441 for (i=0; i<pchip->max_objects; i++)
443 if (can_msgobj_test_fl(pchip->msgobj[i],OPENED))
445 // In- and output buffer re-initialization
446 canqueue_ends_flush_inlist(pchip->msgobj[i]->qends);
447 canqueue_ends_flush_outlist(pchip->msgobj[i]->qends);
452 spin_unlock( &c_can_if1lock );
453 spin_unlock( &c_can_if2lock );
455 DEBUGMSG("-> Message Objects reset\n");
460 ///////////////////////////////////////////////////////////////////////
461 int c_can_config_irqs(struct canchip_t *pchip,
466 DEBUGMSG("(c%d)calling c_can_config_irqs(...)\n", pchip->chip_idx);
468 tempreg = c_can_read_reg_w(pchip, CCCR);
469 //DEBUGMSG("-> CAN Control Register: 0x%.4lx\n",(long)tempreg);
470 c_can_write_reg_w(pchip, tempreg | (irqs & 0xe), CCCR);
471 DEBUGMSG("-> Configured hardware interrupt delivery\n");
475 ///////////////////////////////////////////////////////////////////////
476 int c_can_pre_read_config(struct canchip_t *pchip, struct msgobj_t *pmsgobj)
478 unsigned short readMaskCM = IFXCM_CNTRL | IFXCM_ARB;
479 unsigned short writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_WRRD;
480 unsigned short mcreg = 0;
481 u32 id=pmsgobj->rx_preconfig_id;
483 DEBUGMSG("(c%dm%d)calling c_can_pre_read_config(...)\n", pmsgobj->hostchip->chip_idx, pmsgobj->object);
485 spin_lock( &c_can_if1lock );
487 //loading Message Object in IF1
488 if (c_can_if1_busycheck(pmsgobj->hostchip))
491 c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF1CM);
492 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
494 //setting Message Valid Bit to zero
495 if (c_can_if1_busycheck(pmsgobj->hostchip))
498 c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF1A2);
499 c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
500 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
502 //Configuring Message-Object
503 /* Only access when the C_CAN controller is idle */
504 if (c_can_if1_busycheck(pmsgobj->hostchip))
507 mcreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1CM);
508 c_can_write_reg_w(pmsgobj->hostchip,
509 ((mcreg & IFXMC_UMASK) | IFXMC_EOB | IFXMC_RXIE), CCIF1DMC);
510 //writing arbitration mask for extended or standart mode
511 if (can_msgobj_test_fl(pmsgobj,RX_MODE_EXT))
513 c_can_write_reg_w(pmsgobj->hostchip,
514 IFXARB2_XTD | IFXARB2_MVAL | (id>>16 & 0x1FFF), CCIF1A2);
515 c_can_write_reg_w(pmsgobj->hostchip, id & 0xFFFF, CCIF1A1);
519 c_can_write_reg_w(pmsgobj->hostchip,
520 IFXARB2_MVAL | (id<<2 & 0x1FFC), CCIF1A2);
521 //c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF1A1);
523 c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
524 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
526 spin_unlock( &c_can_if1lock );
528 DEBUGMSG("-> Receiving through message object %d with id=%d\n", pmsgobj->object,
531 c_can_registerdump(pmsgobj->hostchip);
537 CANMSG("Timeout in c_can_if1_busycheck\n");
538 spin_unlock(&c_can_if1lock);
543 ///////////////////////////////////////////////////////////////////////
544 int c_can_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj,
545 struct canmsg_t *msg)
550 ///////////////////////////////////////////////////////////////////////
552 *Prepare the Chip to send specified Message over specified Messageobject
553 *In this version the method also sends the message.
556 int c_can_send_msg(struct canchip_t *pchip, struct msgobj_t *pmsgobj,
557 struct canmsg_t *pmsg)
559 unsigned short readMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_DA | IFXCM_DB;
560 unsigned short writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_DA | IFXCM_DB| IFXCM_WRRD;
561 unsigned short writeSendMskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_DA | IFXCM_DB| IFXCM_WRRD | IFXCM_TRND;
562 unsigned short mcreg = 0;
563 //unsigned short arbreg = 0;
564 unsigned short dataA1 = 0;
565 unsigned short dataA2 = 0;
566 unsigned short dataB1 = 0;
567 unsigned short dataB2 = 0;
569 DEBUGMSG("(c%dm%d)calling c_can_send_msg(...)\n", pmsgobj->hostchip->chip_idx, pmsgobj->object);
571 spin_lock( &c_can_if2lock );
573 can_msgobj_clear_fl(pmsgobj,RX_MODE);
575 //loading Message Object in IF1
576 if (c_can_if2_busycheck(pmsgobj->hostchip)) return -ENODEV;
577 c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF2CM);
578 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF2CR);
579 //setting Message Valid Bit to zero
580 if (c_can_if2_busycheck(pmsgobj->hostchip)) return -ENODEV;
581 c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF2A2);
582 c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF2CM);
583 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF2CR);
585 if (c_can_if2_busycheck(pmsgobj->hostchip)) return -ENODEV;
586 mcreg = c_can_read_reg_w( pmsgobj->hostchip, CCIF2CM);
588 //define Command Mask
589 c_can_write_reg_w(pmsgobj->hostchip, (mcreg & IFXMC_UMASK) | IFXMC_EOB | IFXMC_TXIE
590 | IFXMC_RMTEN | IFXMC_NEWDAT | IFXMC_TXRQST | (pmsg->length & 0xF), CCIF2DMC);
591 //set Arbitration Bits
592 if (can_msgobj_test_fl(pmsgobj,RX_MODE_EXT))
594 c_can_write_reg_w(pmsgobj->hostchip, (u16)(pmsg->id), CCIF2A1);
595 c_can_write_reg_w(pmsgobj->hostchip, IFXARB2_XTD | IFXARB2_MVAL | IFXARB2_DIR
596 | ((u16)(pmsg->id>>16) & 0x1FFF), CCIF2A2);
600 c_can_write_reg_w(pmsgobj->hostchip,
601 (IFXARB2_MVAL | IFXARB2_DIR | ((u16)(pmsg->id<<2) & 0x1FFC)), CCIF2A2);
602 c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF1A1);
607 dataA1 = pmsg->data[0] | (u16)pmsg->data[1]<<8;
608 dataA2 = pmsg->data[2] | (u16)pmsg->data[3]<<8;
609 dataB1 = pmsg->data[4] | (u16)pmsg->data[5]<<8;
610 dataB2 = pmsg->data[6] | (u16)pmsg->data[7]<<8;
612 c_can_write_reg_w(pmsgobj->hostchip, dataA1, CCIF2DA1);
613 c_can_write_reg_w(pmsgobj->hostchip, dataA2, CCIF2DA2);
614 c_can_write_reg_w(pmsgobj->hostchip, dataB1, CCIF2DB1);
615 c_can_write_reg_w(pmsgobj->hostchip, dataB2, CCIF2DB2);
618 c_can_write_reg_w(pmsgobj->hostchip, writeSendMskCM, CCIF2CM);
619 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF2CR);
621 spin_unlock( &c_can_if2lock );
625 c_can_registerdump(pmsgobj->hostchip);
631 //////////////////////////////////////////////////////////////////////
632 int c_can_remote_request(struct canchip_t *pchip, struct msgobj_t *pmsgobj )
634 unsigned short readMaskCM = IFXCM_CNTRL;// | IFXCM_ARB;
635 //unsigned short writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_WRRD;
636 unsigned short mcreg = 0;
638 DEBUGMSG("(c%dm%d)calling c_can_remote_request(...)\n", pmsgobj->hostchip->chip_idx, pmsgobj->object);
640 //Remote request is only available when the message object is in receiving mode
641 if (!can_msgobj_test_fl(pmsgobj,RX_MODE))
646 spin_lock( &c_can_if1lock );
648 //loading Message Object in IF1
649 if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
650 c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF1CM);
651 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
652 //setting Transmit-Request-Bit
653 if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
654 mcreg = c_can_read_reg_w( pmsgobj->hostchip, CCIF1DMC);
655 c_can_write_reg_w(pmsgobj->hostchip, mcreg | IFXMC_TXRQST, CCIF1DMC);
657 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
659 spin_unlock( &c_can_if1lock );
661 DEBUGMSG("-> Sent remote request through message object %d\n", pmsgobj->object);
663 c_can_registerdump(pmsgobj->hostchip);
669 ///////////////////////////////////////////////////////////////////////
670 int c_can_set_btregs(struct canchip_t *pchip,
674 unsigned short tempCR = 0;
676 DEBUGMSG("(c%d)calling c_can_set_btregs(...)\n", pchip->chip_idx);
679 if ( NULL == pchip ) return -1;
681 if (c_can_enable_configuration(pchip))
684 //read Control Register
685 tempCR = c_can_read_reg_w(pchip, CCCR);
686 //Configuration Change Enable
687 c_can_write_reg_w(pchip, tempCR | CR_CCE, CCCR);
688 c_can_write_reg_w(pchip, btr0 | (btr1<<8), CCBT);
690 if (c_can_disable_configuration(pchip))
697 ///////////////////////////////////////////////////////////////////////
699 * Starts the Chip, by setting the CAN Enable Bit
701 int c_can_start_chip(struct canchip_t *pchip)
705 DEBUGMSG("(c%d)calling c_can_start_chip(...)\n", pchip->chip_idx);
710 DEBUGMSG("-> Error Chip not available.\n");
714 #ifdef C_CAN_WITH_CCCE
715 flags = c_can_read_reg_w(pchip, CCCE) | CE_EN;
716 c_can_write_reg_w(pchip, flags, CCCE);
721 c_can_registerdump(pchip);
727 ///////////////////////////////////////////////////////////////////////
729 * Stops the Chip, by deleting the CAN Enable Bit
731 int c_can_stop_chip(struct canchip_t *pchip)
735 DEBUGMSG("(c%d)calling c_can_stop_chip(...)\n", pchip->chip_idx);
740 DEBUGMSG("-> Error Chip not available.\n");
744 #ifdef C_CAN_WITH_CCCE
745 flags = c_can_read_reg_w(pchip, CCCE) & ~CE_EN;
746 c_can_write_reg_w(pchip, flags, CCCE);
753 ///////////////////////////////////////////////////////////////////////
755 *Check the TxOK bit of the Status Register and resets it afterwards.
757 int c_can_check_tx_stat(struct canchip_t *pchip)
759 unsigned long tempstat = 0;
761 DEBUGMSG("(c%d)calling c_can_check_tx_stat(...)\n", pchip->chip_idx);
764 if ( NULL == pchip ) return -1;
766 tempstat = c_can_read_reg_w(pchip, CCSR);
768 if (tempstat & SR_TXOK)
770 c_can_write_reg_w(pchip, tempstat & ~SR_TXOK, CCSR);
780 ///////////////////////////////////////////////////////////////////////
781 int c_can_wakeup_tx(struct canchip_t *chip, struct msgobj_t *obj)
783 can_preempt_disable();
785 can_msgobj_set_fl(obj,TX_REQUEST);
787 /* calls i82527_irq_write_handler synchronized with other invocations
788 from kernel and IRQ context */
789 c_can_irq_sync_activities(chip, obj);
791 can_preempt_enable();
795 ///////////////////////////////////////////////////////////////////////
796 int c_can_filtch_rq(struct canchip_t *chip, struct msgobj_t *obj)
798 can_preempt_disable();
800 can_msgobj_set_fl(obj,FILTCH_REQUEST);
802 /* setups filter synchronized with other invocations from kernel and IRQ context */
803 c_can_irq_sync_activities(chip, obj);
805 can_preempt_enable();
810 ///////////////////////////////////////////////////////////////////////
811 void c_can_registerdump(struct canchip_t *pchip)
813 CANMSG("------------------------------------\n");
814 CANMSG("---------C-CAN Register Dump--------\n");
815 CANMSG("------------at 0x%.8lx-----------\n"
816 ,(unsigned long)pchip->chip_base_addr);
817 CANMSG("Control Register: 0x%.4lx\n",
818 (long)(c_can_read_reg_w( pchip, CCCR)));
819 CANMSG("Status Register: 0x%.4lx\n",
820 (long)(c_can_read_reg_w( pchip, CCSR)));
821 CANMSG("Error Counting Register: 0x%.4lx\n",
822 (long)(c_can_read_reg_w( pchip, CCEC)));
823 CANMSG("Bit Timing Register: 0x%.4lx\n",
824 (long)(c_can_read_reg_w( pchip, CCBT)));
825 CANMSG("Interrupt Register: 0x%.4lx\n",
826 (long)(c_can_read_reg_w( pchip, CCINTR)));
827 CANMSG("Test Register: 0x%.4lx\n",
828 (long)(c_can_read_reg_w( pchip, CCTR)));
829 CANMSG("Baud Rate Presc. Register: 0x%.4lx\n",
830 (long)(c_can_read_reg_w( pchip, CCBRPE)));
831 #ifdef C_CAN_WITH_CCCE
832 CANMSG("CAN Enable Register: 0x%.4lx\n",
833 (long)(c_can_read_reg_w( pchip, CCCE)));
835 CANMSG("Transm. Req. 1 Register: 0x%.4lx\n",
836 (long)(c_can_read_reg_w( pchip, CCTREQ1)));
837 CANMSG("Transm. Req. 2 Register: 0x%.4lx\n",
838 (long)(c_can_read_reg_w( pchip, CCTREQ2)));
839 CANMSG("New Data 1 Register: 0x%.4lx\n",
840 (long)(c_can_read_reg_w( pchip, CCND1)));
841 CANMSG("New Data 2 Register: 0x%.4lx\n",
842 (long)(c_can_read_reg_w( pchip, CCND2)));
843 CANMSG("Interrupt Pend. 1 Register: 0x%.4lx\n",
844 (long)(c_can_read_reg_w( pchip, CCINTP1)));
845 CANMSG("Interrupt Pend. 2 Register: 0x%.4lx\n",
846 (long)(c_can_read_reg_w( pchip, CCINTP2)));
847 CANMSG("------------------------------------\n");
848 CANMSG("IF1 Command Req. Register: 0x%.4lx\n",
849 (long)(c_can_read_reg_w( pchip, CCIF1CR)));
850 CANMSG("IF1 Command Mask Register: 0x%.4lx\n",
851 (long)(c_can_read_reg_w( pchip, CCIF1CM)));
852 CANMSG("IF1 Mask 1 Register: 0x%.4lx\n",
853 (long)(c_can_read_reg_w( pchip, CCIF1M1)));
854 CANMSG("IF1 Mask 2 Register: 0x%.4lx\n",
855 (long)(c_can_read_reg_w( pchip, CCIF1M2)));
856 CANMSG("IF1 Arbitration 1 Register: 0x%.4lx\n",
857 (long)(c_can_read_reg_w( pchip, CCIF1A1)));
858 CANMSG("IF1 Arbitration 2 Register: 0x%.4lx\n",
859 (long)(c_can_read_reg_w( pchip, CCIF1A2)));
860 CANMSG("IF1 Message Control Register: 0x%.4lx\n",
861 (long)(c_can_read_reg_w( pchip, CCIF1DMC)));
862 CANMSG("IF1 Data A1 Register: 0x%.4lx\n",
863 (long)(c_can_read_reg_w( pchip, CCIF1DA1)));
864 CANMSG("IF1 Data A2 Register: 0x%.4lx\n",
865 (long)(c_can_read_reg_w( pchip, CCIF1DA2)));
866 CANMSG("IF1 Data B1 Register: 0x%.4lx\n",
867 (long)(c_can_read_reg_w( pchip, CCIF1DB1)));
868 CANMSG("IF1 Data B2 Register: 0x%.4lx\n",
869 (long)(c_can_read_reg_w( pchip, CCIF1DB2)));
870 CANMSG("------------------------------------\n");
871 CANMSG("IF2 Command Req. Register: 0x%.4lx\n",
872 (long)(c_can_read_reg_w( pchip, CCIF2CR)));
873 CANMSG("IF2 Command Mask Register: 0x%.4lx\n",
874 (long)(c_can_read_reg_w( pchip, CCIF2CM)));
875 CANMSG("IF2 Mask 1 Register: 0x%.4lx\n",
876 (long)(c_can_read_reg_w( pchip, CCIF2M1)));
877 CANMSG("IF2 Mask 2 Register: 0x%.4lx\n",
878 (long)(c_can_read_reg_w( pchip, CCIF2M2)));
879 CANMSG("IF2 Arbitration 1 Register: 0x%.4lx\n",
880 (long)(c_can_read_reg_w( pchip, CCIF2A1)));
881 CANMSG("IF2 Arbitration 2 Register: 0x%.4lx\n",
882 (long)(c_can_read_reg_w( pchip, CCIF2A2)));
883 CANMSG("IF2 Message Control Register: 0x%.4lx\n",
884 (long)(c_can_read_reg_w( pchip, CCIF2DMC)));
885 CANMSG("IF2 Data A1 Register: 0x%.4lx\n",
886 (long)(c_can_read_reg_w( pchip, CCIF2DA1)));
887 CANMSG("IF2 Data A2 Register: 0x%.4lx\n",
888 (long)(c_can_read_reg_w( pchip, CCIF2DA2)));
889 CANMSG("IF2 Data B1 Register: 0x%.4lx\n",
890 (long)(c_can_read_reg_w( pchip, CCIF2DB1)));
891 CANMSG("IF2 Data B2 Register: 0x%.4lx\n",
892 (long)(c_can_read_reg_w( pchip, CCIF2DB2)));
893 CANMSG("------------------------------------\n");
894 CANMSG("------------------------------------\n");
898 void c_can_if1_registerdump(struct canchip_t *pchip)
900 CANMSG("----------------------------------------\n");
901 CANMSG("Error Counting Register: 0x%.4lx\n",
902 (long)(c_can_read_reg_w( pchip, CCEC)));
903 CANMSG("---------C-CAN IF1 Register Dump--------\n");
904 CANMSG("IF1 Command Req. Register: 0x%.4lx\n",
905 (long)(c_can_read_reg_w( pchip, CCIF1CR)));
906 CANMSG("IF1 Command Mask Register: 0x%.4lx\n",
907 (long)(c_can_read_reg_w( pchip, CCIF1CM)));
908 CANMSG("IF1 Mask 1 Register: 0x%.4lx\n",
909 (long)(c_can_read_reg_w( pchip, CCIF1M1)));
910 CANMSG("IF1 Mask 2 Register: 0x%.4lx\n",
911 (long)(c_can_read_reg_w( pchip, CCIF1M2)));
912 CANMSG("IF1 Arbitration 1 Register: 0x%.4lx\n",
913 (long)(c_can_read_reg_w( pchip, CCIF1A1)));
914 CANMSG("IF1 Arbitration 2 Register: 0x%.4lx\n",
915 (long)(c_can_read_reg_w( pchip, CCIF1A2)));
916 CANMSG("IF1 Message Control Register: 0x%.4lx\n",
917 (long)(c_can_read_reg_w( pchip, CCIF1DMC)));
918 CANMSG("IF1 Data A1 Register: 0x%.4lx\n",
919 (long)(c_can_read_reg_w( pchip, CCIF1DA1)));
920 CANMSG("IF1 Data A2 Register: 0x%.4lx\n",
921 (long)(c_can_read_reg_w( pchip, CCIF1DA2)));
922 CANMSG("IF1 Data B1 Register: 0x%.4lx\n",
923 (long)(c_can_read_reg_w( pchip, CCIF1DB1)));
924 CANMSG("IF1 Data B2 Register: 0x%.4lx\n",
925 (long)(c_can_read_reg_w( pchip, CCIF1DB2)));
928 ///////////////////////////////////////////////////////////////////////
930 int c_can_register(struct chipspecops_t *chipspecops)
932 CANMSG("initializing c_can chip operations\n");
933 chipspecops->chip_config=c_can_chip_config;
934 chipspecops->baud_rate=c_can_baud_rate;
935 /*chipspecops->standard_mask=c_can_standard_mask;
936 chipspecops->extended_mask=c_can_extended_mask;
937 chipspecops->message15_mask=c_can_extended_mask;*/
938 chipspecops->clear_objects=c_can_clear_objects;
939 /*chipspecops->config_irqs=c_can_config_irqs;*/
940 chipspecops->pre_read_config=c_can_pre_read_config;
941 chipspecops->pre_write_config=c_can_pre_write_config;
942 chipspecops->send_msg=c_can_send_msg;
943 chipspecops->check_tx_stat=c_can_check_tx_stat;
944 chipspecops->wakeup_tx=c_can_wakeup_tx;
945 chipspecops->filtch_rq = c_can_filtch_rq;
946 chipspecops->remote_request=c_can_remote_request;
947 chipspecops->enable_configuration=c_can_enable_configuration;
948 chipspecops->disable_configuration=c_can_disable_configuration;
949 chipspecops->set_btregs=c_can_set_btregs;
950 chipspecops->start_chip=c_can_start_chip;
951 chipspecops->stop_chip=c_can_stop_chip;
952 chipspecops->irq_handler=c_can_irq_handler;
953 chipspecops->irq_accept = NULL;
957 int c_can_fill_chipspecops(struct canchip_t *chip)
959 chip->chip_type="c_can";
960 if(MAX_MSGOBJS >= 32) {
961 chip->max_objects = 32;
963 CANMSG("C_CAN requires 32 message objects per chip,"
964 " but only %d is compiled maximum\n",MAX_MSGOBJS);
965 chip->max_objects = MAX_MSGOBJS;
967 c_can_register(chip->chipspecops);