1 /**************************************************************************/
2 /* File: ipci165.h - support for IXXAT iPC-I 165 (PCI) compatible HW */
4 /* LinCAN - (Not only) Linux CAN bus driver */
5 /* Copyright (C) 2002-2009 DCE FEE CTU Prague <http://dce.felk.cvut.cz> */
6 /* Copyright (C) 2002-2009 Pavel Pisa <pisa@cmp.felk.cvut.cz> */
7 /* Copyright (C) 2004-2005 Radim Kalas <kalas@unicontrols.cz> */
8 /* Funded by OCERA and FRESCOR IST projects */
9 /* Based on CAN driver code by Arnaud Westenberg <arnaud@wanadoo.nl> */
11 /* LinCAN is free software; you can redistribute it and/or modify it */
12 /* under terms of the GNU General Public License as published by the */
13 /* Free Software Foundation; either version 2, or (at your option) any */
14 /* later version. LinCAN is distributed in the hope that it will be */
15 /* useful, but WITHOUT ANY WARRANTY; without even the implied warranty */
16 /* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU */
17 /* General Public License for more details. You should have received a */
18 /* copy of the GNU General Public License along with LinCAN; see file */
19 /* COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, */
20 /* Cambridge, MA 02139, USA. */
22 /* To allow use of LinCAN in the compact embedded systems firmware */
23 /* and RT-executives (RTEMS for example), main authors agree with next */
24 /* special exception: */
26 /* Including LinCAN header files in a file, instantiating LinCAN generics */
27 /* or templates, or linking other files with LinCAN objects to produce */
28 /* an application image/executable, does not by itself cause the */
29 /* resulting application image/executable to be covered by */
30 /* the GNU General Public License. */
31 /* This exception does not however invalidate any other reasons */
32 /* why the executable file might be covered by the GNU Public License. */
33 /* Publication of enhanced or derived LinCAN files is required although. */
34 /**************************************************************************/
36 #include "../include/can_sysdep.h"
37 #include "../include/kthread.h"
39 /* PCI device identification */
40 #define IPCI165_VENDOR_ID PCI_VENDOR_ID_PLX
41 #define IPCI165_DEVICE_ID PCI_DEVICE_ID_PLX_9050
43 #define IPCI165_SUBSYSTEM_ID 0x1067 /* subsystem ID for IXXAT iPC-I 165 card */
44 #define CP350_SUBSYSTEM_ID 0x1089 /* subsystem ID for PEP/Kontron CP350 card */
47 /*****************************************************************************
48 * Control Registers Memory specific defines *
49 *****************************************************************************/
50 #define CRM_SIZE 0x80 /* region size */
52 #define CRM_UCR 0x50 /* user control register */
53 #define CRM_ICR 0x4C /* interrupt control register */
55 /*****************************************************************************
56 * DP-RAM (PCI Memory Window 2) specific defines *
57 *****************************************************************************/
58 #define DPRAM_SIZE 8*1024 /* DP-RAM size - PCI Memory Window 2 */
60 #define OF_CMD_BUFFER 0 /* Offset of Command Buffer \
63 #define OF_CH1_TX_QUEUE 0x50 /* offset to TX queue for channel 1 */
64 #define OF_CH2_TX_QUEUE 0x438 /* offset to TX queue for channel 2 */
65 #define OF_CH1_RX_QUEUE 0x820 /* offset to RX queue for channel 1 */
66 #define OF_CH2_RX_QUEUE 0xc08 /* offset to RX queue for channel 2 */
68 #define OF_STATUS_BUFFER 0xff0 /* offset to status buffer */
70 #define BCI_QUEUE_SIZE 50 /* Size of TX and RX message queues \
71 (number of messages) */
72 #define BCI_MSG_SIZE 20 /* Size of one message */
74 /*****************************************************************************
75 * Bootstrap loader specific defines *
76 *****************************************************************************/
78 /* identification strings offsets & lengths */
79 #define BOARD_NAME_OFS 0x00 /* Name (string) */
80 #define BOARD_NAME_LEN 7 /* String length */
82 #define HW_VERSION_OFS 0x20 /* Version (string) */
83 #define HW_VERSION_LEN 6 /* String length */
85 #define MODE_OFS 0x102 /* Mode (string) */
86 #define MODE_LEN 14 /* String length */
88 #define TYPE_LEN 11 /* Type length */
90 /* FW loader command buffer offsets */
91 #define OF_LD_SYNC 0x100 /* Synchronization flag */
92 #define OF_LD_CMD 0x101 /* Command code */
93 #define OF_LD_NUM 0x102 /* Size of FW block */
94 #define OF_LD_ADDRESS 0x104 /* Start Address of FW block */
95 #define OF_LD_DATA 0x108 /* Data of FW block */
98 #define LD_CMD_DOWNLOAD 1 /* Download FW block */
99 #define LD_CMD_START_FW 2 /* Start FW */
101 /*****************************************************************************
102 * BCI specific defines *
103 *****************************************************************************/
105 /* BCI command buffer offsets */
106 #define OF_BCI_SYNC 0x00 /* Synchronization flag */
107 #define OF_BCI_NUM 0x01 /* Command size */
108 #define OF_BCI_CMD 0x04 /* Command code */
109 #define OF_BCI_DATA 0x05 /* Command data */
110 #define BCI_CMD_MAX_LEN 76 /* Max command length */
113 #define CMD_ID 1 /* Get identification string */
114 #define CMD_VERSION 2 /* Get version number string */
115 #define CMD_TEST 3 /* Test the command buffer, invert data bytes */
116 #define CMD_INIT_CAN 4 /* Initialization of the CAN controller */
117 #define CMD_START_CAN 6 /* Start the CAN controller */
118 #define CMD_STOP_CAN 7 /* Stop the CAN controller */
119 #define CMD_RESET_CAN 8 /* Reset the CAN controller */
120 #define CMD_SET_EXT_FILTER_MASK 9 /* Set global filter mask */
121 #define CMD_CONFIG_RX_QUEUE 11 /* Config receive queue mode */
122 #define CMD_GET_BOARD_INFO 12 /* Get board information */
123 #define CMD_START_TIMER 13 /* Start cyclic timer */
124 #define CMD_STOP_TIMER 14 /* Stop cyclic timer */
125 #define CMD_SET_ACC_MASK 15 /* Set acceptance mask */
127 /* CMD_BOARD_INFO offsets */
128 #define BOARD_INFO_SIZE 26 /* Size */
129 #define OF_BOARD_INFO_VER 1 /* Version in BCD, UINT16 */
130 #define OF_BOARD_INFO_CHIPS 3 /* Num of chips, UINT16 */
131 #define OF_BOARD_INFO_CHIP1_TYPE 5 /* Type of first chip, UINT8[10] */
132 #define OF_BOARD_INFO_CHIP2_TYPE 15 /* Type of second chip, UINT8[10] */
134 /* baud rates BTR0, BTR1 for SJA1000 */
135 #define BCI_10KB 0x67,0x2F
136 #define BCI_20KB 0x53,0x2F
137 #define BCI_50KB 0x47,0x2F
138 #define BCI_100KB 0x43,0x2F
139 #define BCI_125KB 0x03,0x1C
140 #define BCI_250KB 0x01,0x1C
141 #define BCI_500KB 0x00,0x1C
142 #define BCI_1000KB 0x00,0x14
144 #define CAN_FRAME_MIN_BIT_LEN 47 /* Min no of bits in CAN standard data frame */
145 #define CAN_FRAME_MAX_BIT_LEN 111 /* Max no of bits in CAN standard data frame */
147 /* BCI_CONFIG_RX Queue Modes */
148 #define BCI_POLL_MODE 0
149 #define BCI_LATENCY_MODE 1
150 #define BCI_THROUGHPUT_MODE 2
154 int idx; /* points to the active record in buffer */
155 can_ioptr_t addr; /* start address of the message queue */
158 /* ipci165 chip data */
159 struct ipci165_chip_t {
160 struct bci_queue_t rx_queue; /* RX queue info */
161 struct bci_queue_t tx_queue; /* TX queue info */
162 kthread_t kthread; /* kernel thread info */
163 long flags; /* flag for syncing with kernel thread */
166 #define CHIP_FLAG_BUS_OFF 1 /* bus-off signal to kthread */
167 #define CHIP_FLAG_RESET 2 /* chip is being reseted */
170 /* RX & TX Queue message structure */
171 #define BCI_MSG_STATUS 0 /* status (U8) */
172 #define BCI_MSG_NUM 1 /* size (U8) */
173 #define BCI_MSG_TIMESTAMP 2 /* timestamp (U32)*/
174 #define BCI_MSG_TYPE 6 /* message type (U8) */
177 #define BCI_MSG_FRAME 7 /* frame info (U8) */
178 #define BCI_MSG_ID 8 /* ID 11/29b (U16/U32) */
179 #define BCI_MSG_STD_DATA 10 /* message data */
180 #define BCI_MSG_EXT_DATA 12 /* message data */
183 #define BCI_MSG_CAN_STATUS 8 /* status info (U16) */
185 #define BCI_MSG_STATUS_FREE 0 /* message buffer is free */
186 #define BCI_MSG_STATUS_FULL 1 /* message buffer is used */
188 #define BCI_MSG_TYPE_CAN 0 /* message containing CAN frame */
189 #define BCI_MSG_TYPE_STATUS 1 /* message containing status info */
191 #define BCI_MSG_FRAME_RTR 0x40 /* RTR flag */
192 #define BCI_MSG_FRAME_EXT 0x80 /* Extended Frame */
194 #define BCI_TIMESTAMP_RES 125 /* Time stamp resolution in usec */
197 #define OF_CAN1_STATUS (OF_STATUS_BUFFER + 0)
198 #define OF_CAN1_LOAD (OF_STATUS_BUFFER + 2)
199 #define OF_CAN2_STATUS (OF_STATUS_BUFFER + 4)
200 #define OF_CAN2_LOAD (OF_STATUS_BUFFER + 6)
201 #define OF_CPU_LOAD (OF_STATUS_BUFFER + 8)
202 #define OF_LIFE_COUNTER (OF_STATUS_BUFFER + 10)
204 #define BCI_CAN_STATUS_INIT 0x0001 /* ctrl is in init mode */
205 #define BCI_CAN_STATUS_WARNING_LEVEL 0x0002 /* warning level has been reached */
206 #define BCI_CAN_STATUS_BUS_OFF 0x0004 /* ctrl disconnected from net */
207 #define BCI_CAN_STATUS_DATA_OVERRUN 0x0008 /* overrun of can message happend */
208 #define BCI_CAN_STATUS_RX 0x0010 /* ctrl is recieving */
209 #define BCI_CAN_STATUS_TX 0x0020 /* ctrl is sending */
210 #define BCI_CAN_STATUS_QUEUE_OVERRUN 0x0100 /* queue overrun */