lincan/src/sja1000.c

   1 /* sja1000.c
   2  * Linux CAN-bus device driver.
   3  * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
   4  * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
   5  * email:pisa@cmp.felk.cvut.cz
   6  * This software is released under the GPL-License.
   7  * Version lincan-0.2  9 Jul 2003
   8  */
   9
  10 #include "../include/can.h"
  11 #include "../include/can_sysdep.h"
  12 #include "../include/main.h"
  13 #include "../include/sja1000.h"
  14
  15 void sja1000_irq_read_handler(struct chip_t *chip, struct msgobj_t *obj);
  16 void sja1000_irq_write_handler(struct chip_t *chip, struct msgobj_t *obj);
  17
  18 int sja1000_enable_configuration(struct chip_t *chip)
  19 {
  20         int i=0;
  21         unsigned flags;
  22
  23         can_disable_irq(chip->chip_irq);
  24
  25         flags=can_read_reg(chip,SJACR);
  26
  27         while ((!(flags & CR_RR)) && (i<=10)) {
  28                 can_write_reg(chip,flags|CR_RR,SJACR);
  29                 udelay(100);
  30                 i++;
  31                 flags=can_read_reg(chip,SJACR);
  32         }
  33         if (i>=10) {
  34                 CANMSG("Reset error\n");
  35                 can_enable_irq(chip->chip_irq);
  36                 return -ENODEV;
  37         }
  38
  39         return 0;
  40 }
  41
  42 int sja1000_disable_configuration(struct chip_t *chip)
  43 {
  44         int i=0;
  45         unsigned flags;
  46
  47         flags=can_read_reg(chip,SJACR);
  48
  49         while ( (flags & CR_RR) && (i<=10) ) {
  50                 can_write_reg(chip,flags & (CR_RIE|CR_TIE|CR_EIE|CR_OIE),SJACR);
  51                 udelay(100);
  52                 i++;
  53                 flags=can_read_reg(chip,SJACR);
  54         }
  55         if (i>=10) {
  56                 CANMSG("Error leaving reset status\n");
  57                 return -ENODEV;
  58         }
  59
  60         can_enable_irq(chip->chip_irq);
  61
  62         return 0;
  63 }
  64
  65 int sja1000_chip_config(struct chip_t *chip)
  66 {
  67         if (sja1000_enable_configuration(chip))
  68                 return -ENODEV;
  69
  70         /* Set mode, clock out, comparator */
  71         can_write_reg(chip,chip->sja_cdr_reg,SJACDR);
  72         /* Set driver output configuration */
  73         can_write_reg(chip,chip->sja_ocr_reg,SJAOCR);
  74
  75         if (sja1000_standard_mask(chip,0x0000, 0xffff))
  76                 return -ENODEV;
  77
  78         if (!chip->baudrate)
  79                 chip->baudrate=1000000;
  80         if (sja1000_baud_rate(chip,chip->baudrate,chip->clock,0,75,0))
  81                 return -ENODEV;
  82
  83         /* Enable hardware interrupts */
  84         can_write_reg(chip,(CR_RIE|CR_TIE|CR_EIE|CR_OIE),SJACR);
  85
  86         sja1000_disable_configuration(chip);
  87
  88         return 0;
  89 }
  90
  91 int sja1000_standard_mask(struct chip_t *chip, unsigned short code, unsigned short mask)
  92 {
  93         unsigned char write_code, write_mask;
  94
  95         if (sja1000_enable_configuration(chip))
  96                 return -ENODEV;
  97
  98         /* The acceptance code bits (SJAACR bits 0-7) and the eight most
  99          * significant bits of the message identifier (id.10 to id.3) must be
 100          * equal to those bit positions which are marked relevant by the
 101          * acceptance mask bits (SJAAMR bits 0-7).
 102          * (id.10 to id.3) = (SJAACR.7 to SJAACR.0) v (SJAAMR.7 to SJAAMR.0)
 103          * (Taken from Philips sja1000 Data Sheet)
 104          */
 105         write_code = (unsigned char) code >> 3;
 106         write_mask = (unsigned char) mask >> 3;
 107
 108         can_write_reg(chip,write_code,SJAACR);
 109         can_write_reg(chip,write_mask,SJAAMR);
 110
 111         DEBUGMSG("Setting acceptance code to 0x%lx\n",(unsigned long)code);
 112         DEBUGMSG("Setting acceptance mask to 0x%lx\n",(unsigned long)mask);
 113
 114         sja1000_disable_configuration(chip);
 115
 116         return 0;
 117 }
 118
 119 /* Set communication parameters.
 120  * param rate baud rate in Hz
 121  * param clock frequency of sja1000 clock in Hz (ISA osc is 14318000)
 122  * param sjw synchronization jump width (0-3) prescaled clock cycles
 123  * param sampl_pt sample point in % (0-100) sets (TSEG1+2)/(TSEG1+TSEG2+3) ratio
 124  * param flags fields BTR1_SAM, OCMODE, OCPOL, OCTP, OCTN, CLK_OFF, CBP
 125  */
 126 int sja1000_baud_rate(struct chip_t *chip, int rate, int clock, int sjw,
 127                                                         int sampl_pt, int flags)
 128 {
 129         int best_error = 1000000000, error;
 130         int best_tseg=0, best_brp=0, best_rate=0, brp=0;
 131         int tseg=0, tseg1=0, tseg2=0;
 132
 133         if (sja1000_enable_configuration(chip))
 134                 return -ENODEV;
 135
 136         clock /=2;
 137
 138         /* tseg even = round down, odd = round up */
 139         for (tseg=(0+0+2)*2; tseg<=(MAX_TSEG2+MAX_TSEG1+2)*2+1; tseg++) {
 140                 brp = clock/((1+tseg/2)*rate)+tseg%2;
 141                 if (brp == 0 || brp > 64)
 142                         continue;
 143                 error = rate - clock/(brp*(1+tseg/2));
 144                 if (error < 0)
 145                         error = -error;
 146                 if (error <= best_error) {
 147                         best_error = error;
 148                         best_tseg = tseg/2;
 149                         best_brp = brp-1;
 150                         best_rate = clock/(brp*(1+tseg/2));
 151                 }
 152         }
 153         if (best_error && (rate/best_error < 10)) {
 154                 CANMSG("baud rate %d is not possible with %d Hz clock\n",
 155                                                                 rate, 2*clock);
 156                 CANMSG("%d bps. brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d\n",
 157                                 best_rate, best_brp, best_tseg, tseg1, tseg2);
 158                 return -EINVAL;
 159         }
 160         tseg2 = best_tseg-(sampl_pt*(best_tseg+1))/100;
 161         if (tseg2 < 0)
 162                 tseg2 = 0;
 163         if (tseg2 > MAX_TSEG2)
 164                 tseg2 = MAX_TSEG2;
 165         tseg1 = best_tseg-tseg2-2;
 166         if (tseg1 > MAX_TSEG1) {
 167                 tseg1 = MAX_TSEG1;
 168                 tseg2 = best_tseg-tseg1-2;
 169         }
 170
 171         DEBUGMSG("Setting %d bps.\n", best_rate);
 172         DEBUGMSG("brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d, sampl_pt=%d\n",
 173                                         best_brp, best_tseg, tseg1, tseg2,
 174                                         (100*(best_tseg-tseg2)/(best_tseg+1)));
 175
 176
 177         can_write_reg(chip, sjw<<6 | best_brp, SJABTR0);
 178         can_write_reg(chip, ((flags & BTR1_SAM) != 0)<<7 | tseg2<<4 | tseg1,
 179                                                                 SJABTR1);
 180 //      can_write_reg(chip, OCR_MODE_NORMAL | OCR_TX0_LH | OCR_TX1_ZZ, SJAOCR);
 181         /* BASIC mode, bypass input comparator */
 182 //      can_write_reg(chip, CDR_CBP| /* CDR_CLK_OFF | */ 7, SJACDR);
 183
 184         sja1000_disable_configuration(chip);
 185
 186         return 0;
 187 }
 188
 189 int sja1000_pre_read_config(struct chip_t *chip, struct msgobj_t *obj)
 190 {
 191         int i;
 192
 193         i=can_read_reg(chip,SJASR);
 194
 195         if (!(i&SR_RBS)) {
 196 //Temp
 197                 for (i=0; i<0x20; i++)
 198                         CANMSG("0x%x is 0x%x\n",i,can_read_reg(chip,i));
 199                         return 0;
 200         }
 201         sja1000_start_chip(chip);
 202
 203     // disable interrupts for a moment
 204         can_write_reg(chip, 0, SJACR);
 205
 206         sja1000_irq_read_handler(chip, obj);
 207
 208     // enable interrupts
 209         can_write_reg(chip, CR_OIE | CR_EIE | CR_TIE | CR_RIE, SJACR);
 210
 211
 212         return 1;
 213 }
 214
 215 #define MAX_TRANSMIT_WAIT_LOOPS 10
 216
 217 int sja1000_pre_write_config(struct chip_t *chip, struct msgobj_t *obj,
 218                                                         struct canmsg_t *msg)
 219 {
 220         int i=0, id=0;
 221         int len;
 222
 223         sja1000_start_chip(chip); //sja1000 goes automatically into reset mode on errors
 224
 225         /* Wait until Transmit Buffer Status is released */
 226         while ( !(can_read_reg(chip, SJASR) & SR_TBS) &&
 227                                                 i++<MAX_TRANSMIT_WAIT_LOOPS) {
 228                 udelay(i);
 229         }
 230
 231         if (!(can_read_reg(chip, SJASR) & SR_TBS)) {
 232                 CANMSG("Transmit timed out, cancelling\n");
 233                 can_write_reg(chip, CMR_AT, SJACMR);
 234                 i=0;
 235                 while ( !(can_read_reg(chip, SJASR) & SR_TBS) &&
 236                                 i++<MAX_TRANSMIT_WAIT_LOOPS) {
 237                         udelay(i);
 238                 }
 239                 if (!(can_read_reg(chip, SJASR) & SR_TBS)) {
 240                         CANMSG("Could not cancel, please reset\n");
 241                         return -EIO;
 242                 }
 243         }
 244
 245         len = msg->length;
 246         if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
 247         id = (msg->id<<5) | ((msg->flags&MSG_RTR)?ID0_RTR:0) | len;
 248
 249         can_write_reg(chip, id>>8, SJATXID1);
 250         can_write_reg(chip, id & 0xff , SJATXID0);
 251
 252         for (i=0; i<len; i++)
 253                 can_write_reg(chip, msg->data[i], SJATXDAT0+i);
 254
 255         return 0;
 256 }
 257
 258 int sja1000_send_msg(struct chip_t *chip, struct msgobj_t *obj,
 259                                                         struct canmsg_t *msg)
 260 {
 261         can_write_reg(chip, CMR_TR, SJACMR);
 262
 263         return 0;
 264 }
 265
 266 int sja1000_check_tx_stat(struct chip_t *chip)
 267 {
 268         if (can_read_reg(chip,SJASR) & SR_TCS)
 269                 return 0;
 270         else
 271                 return 1;
 272 }
 273
 274 int sja1000_set_btregs(struct chip_t *chip, unsigned short btr0,
 275                                                         unsigned short btr1)
 276 {
 277         if (sja1000_enable_configuration(chip))
 278                 return -ENODEV;
 279
 280         can_write_reg(chip, btr0, SJABTR0);
 281         can_write_reg(chip, btr1, SJABTR1);
 282
 283         sja1000_disable_configuration(chip);
 284
 285         return 0;
 286 }
 287
 288 int sja1000_start_chip(struct chip_t *chip)
 289 {
 290         unsigned short flags = 0;
 291
 292         flags = can_read_reg(chip, SJACR) & (CR_RIE|CR_TIE|CR_EIE|CR_OIE);
 293         can_write_reg(chip, flags, SJACR);
 294
 295         return 0;
 296 }
 297
 298 int sja1000_stop_chip(struct chip_t *chip)
 299 {
 300         unsigned short flags = 0;
 301
 302         flags = can_read_reg(chip, SJACR) & (CR_RIE|CR_TIE|CR_EIE|CR_OIE);
 303         can_write_reg(chip, flags|CR_RR, SJACR);
 304
 305         return 0;
 306 }
 307
 308 int sja1000_remote_request(struct chip_t *chip, struct msgobj_t *obj)
 309 {
 310         CANMSG("sja1000_remote_request not implemented\n");
 311         return -ENOSYS;
 312 }
 313
 314 int sja1000_extended_mask(struct chip_t *chip, unsigned long code,
 315                 unsigned long mask)
 316 {
 317         CANMSG("sja1000_extended_mask not implemented\n");
 318         return -ENOSYS;
 319 }
 320
 321 int sja1000_clear_objects(struct chip_t *chip)
 322 {
 323         CANMSG("sja1000_clear_objects not implemented\n");
 324         return -ENOSYS;
 325 }
 326
 327 int sja1000_config_irqs(struct chip_t *chip, short irqs)
 328 {
 329         CANMSG("sja1000_config_irqs not implemented\n");
 330         return -ENOSYS;
 331 }
 332
 333
 334 can_irqreturn_t sja1000_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
 335 {
 336         unsigned irq_register;
 337         struct chip_t *chip=(struct chip_t *)dev_id;
 338         struct msgobj_t *obj=chip->msgobj[0];
 339
 340         irq_register=can_read_reg(chip, SJAIR);
 341 //      DEBUGMSG("sja1000_irq_handler: SJAIR:%02x\n",irq_register);
 342 //      DEBUGMSG("sja1000_irq_handler: SJASR:%02x\n",
 343 //                                      can_read_reg(chip, SJASR));
 344
 345         if ((irq_register & (IR_WUI|IR_DOI|IR_EI|IR_TI|IR_RI)) == 0)
 346                 return CAN_IRQ_NONE;
 347
 348         if ((irq_register & IR_RI) != 0)
 349                 sja1000_irq_read_handler(chip, obj);
 350
 351         if ((irq_register & IR_TI) != 0) {
 352                 can_msgobj_set_fl(obj,TX_REQUEST);
 353                 while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)){
 354                         can_msgobj_clear_fl(obj,TX_REQUEST);
 355
 356                         if (can_read_reg(chip, SJASR) & SR_TBS)
 357                                 sja1000_irq_write_handler(chip, obj);
 358
 359                         can_msgobj_clear_fl(obj,TX_LOCK);
 360                         if(!can_msgobj_test_fl(obj,TX_REQUEST)) break;
 361                 }
 362         }
 363
 364         if ((irq_register & (IR_EI|IR_DOI)) != 0) {
 365                 // Some error happened
 366 // FIXME: chip should be brought to usable state. Transmission cancelled if in progress.
 367 // Reset flag set to 0 if chip is already off the bus. Full state report
 368                 CANMSG("Error: status register: 0x%x irq_register: 0x%02x\n",
 369                         can_read_reg(chip, SJASR), irq_register);
 370                 obj->ret=-1;
 371
 372                 if(obj->tx_slot){
 373                         canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_BUS);
 374                         /*canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
 375                         obj->tx_slot=NULL;*/
 376                 }
 377         }
 378
 379         return CAN_IRQ_HANDLED;
 380 }
 381
 382 void sja1000_irq_read_handler(struct chip_t *chip, struct msgobj_t *obj)
 383 {
 384         int i=0, id=0, len;
 385
 386         do {
 387                 id = can_read_reg(chip, SJARXID0) | (can_read_reg(chip, SJARXID1)<<8);
 388                 obj->rx_msg.length = len = id & 0x0f;
 389                 obj->rx_msg.flags = id&ID0_RTR ? MSG_RTR : 0;
 390                 obj->rx_msg.timestamp = 0;
 391                 obj->rx_msg.cob = 0;
 392                 obj->rx_msg.id = id>>5;
 393
 394                 if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
 395                 for (i=0; i<len; i++)
 396                         obj->rx_msg.data[i]=can_read_reg(chip, SJARXDAT0 + i);
 397
 398                 can_write_reg(chip, CMR_RRB, SJACMR);
 399
 400                 canque_filter_msg2edges(obj->qends, &obj->rx_msg);
 401         } while(can_read_reg(chip, SJASR) & SR_RBS);
 402 }
 403
 404 void sja1000_irq_write_handler(struct chip_t *chip, struct msgobj_t *obj)
 405 {
 406         int cmd;
 407
 408         if(obj->tx_slot){
 409                 /* Do local transmitted message distribution if enabled */
 410                 if (processlocal){
 411                         obj->tx_slot->msg.flags |= MSG_LOCAL;
 412                         canque_filter_msg2edges(obj->qends, &obj->tx_slot->msg);
 413                 }
 414                 /* Free transmitted slot */
 415                 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
 416                 obj->tx_slot=NULL;
 417         }
 418
 419         cmd=canque_test_outslot(obj->qends, &obj->tx_qedge, &obj->tx_slot);
 420         if(cmd<0)
 421                 return;
 422
 423         if (chip->chipspecops->pre_write_config(chip, obj, &obj->tx_slot->msg)) {
 424                 obj->ret = -1;
 425                 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_PREP);
 426                 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
 427                 obj->tx_slot=NULL;
 428                 return;
 429         }
 430         if (chip->chipspecops->send_msg(chip, obj, &obj->tx_slot->msg)) {
 431                 obj->ret = -1;
 432                 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_SEND);
 433                 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
 434                 obj->tx_slot=NULL;
 435                 return;
 436         }
 437 }
 438
 439 /**
 440  * sja1000_wakeup_tx: - wakeups TX processing
 441  * @chip: pointer to chip state structure
 442  * @obj: pointer to message object structure
 443  *
 444  * Return Value: negative value reports error.
 445  * File: src/sja1000.c
 446  */
 447 int sja1000_wakeup_tx(struct chip_t *chip, struct msgobj_t *obj)
 448 {
 449         can_preempt_disable();
 450
 451         can_msgobj_set_fl(obj,TX_REQUEST);
 452         while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)){
 453                 can_msgobj_clear_fl(obj,TX_REQUEST);
 454
 455                 if (can_read_reg(chip, SJASR) & SR_TBS)
 456                         sja1000_irq_write_handler(chip, obj);
 457
 458                 can_msgobj_clear_fl(obj,TX_LOCK);
 459                 if(!can_msgobj_test_fl(obj,TX_REQUEST)) break;
 460         }
 461
 462         can_preempt_enable();
 463         return 0;
 464 }
 465
 466 int sja1000_register(struct chipspecops_t *chipspecops)
 467 {
 468         chipspecops->chip_config = sja1000_chip_config;
 469         chipspecops->baud_rate = sja1000_baud_rate;
 470         chipspecops->standard_mask = sja1000_standard_mask;
 471         chipspecops->extended_mask = sja1000_extended_mask;
 472         chipspecops->message15_mask = sja1000_extended_mask;
 473         chipspecops->clear_objects = sja1000_clear_objects;
 474         chipspecops->config_irqs = sja1000_config_irqs;
 475         chipspecops->pre_read_config = sja1000_pre_read_config;
 476         chipspecops->pre_write_config = sja1000_pre_write_config;
 477         chipspecops->send_msg = sja1000_send_msg;
 478         chipspecops->check_tx_stat = sja1000_check_tx_stat;
 479         chipspecops->wakeup_tx=sja1000_wakeup_tx;
 480         chipspecops->remote_request = sja1000_remote_request;
 481         chipspecops->enable_configuration = sja1000_enable_configuration;
 482         chipspecops->disable_configuration = sja1000_disable_configuration;
 483         chipspecops->set_btregs = sja1000_set_btregs;
 484         chipspecops->start_chip = sja1000_start_chip;
 485         chipspecops->stop_chip = sja1000_stop_chip;
 486         chipspecops->irq_handler = sja1000_irq_handler;
 487         return 0;
 488 }