embedded/arch/arm/generic/defines/cpu_def.h

   1 #ifndef _ARM_CPU_DEF_H
   2 #define _ARM_CPU_DEF_H
   3
   4 #ifndef CODE
   5   #define CODE
   6 #endif
   7
   8 #ifndef XDATA
   9   #define XDATA
  10 #endif
  11
  12 #ifndef DATA
  13   #define DATA
  14 #endif
  15
  16 struct pt_regs {
  17         long uregs[18];
  18 };
  19
  20 #define ARM_cpsr        uregs[16]
  21 #define ARM_pc          uregs[15]
  22 #define ARM_lr          uregs[14]
  23 #define ARM_sp          uregs[13]
  24 #define ARM_ip          uregs[12]
  25 #define ARM_fp          uregs[11]
  26 #define ARM_r10         uregs[10]
  27 #define ARM_r9          uregs[9]
  28 #define ARM_r8          uregs[8]
  29 #define ARM_r7          uregs[7]
  30 #define ARM_r6          uregs[6]
  31 #define ARM_r5          uregs[5]
  32 #define ARM_r4          uregs[4]
  33 #define ARM_r3          uregs[3]
  34 #define ARM_r2          uregs[2]
  35 #define ARM_r1          uregs[1]
  36 #define ARM_r0          uregs[0]
  37 #define ARM_ORIG_r0     uregs[17]
  38
  39 struct undef_hook {
  40         struct undef_hook *next;
  41         unsigned long instr_mask;
  42         unsigned long instr_val;
  43         unsigned long cpsr_mask;
  44         unsigned long cpsr_val;
  45         int (*fn)(struct pt_regs *regs, unsigned int instr);
  46 };
  47
  48 int register_undef_hook(struct undef_hook *hook);
  49
  50 #define NR_IRQS 256
  51
  52 typedef struct irq_handler {
  53   void            (*handler)(int, void *, struct pt_regs *);
  54   unsigned long   flags;
  55   void            *dev_id;
  56   const char      *devname;
  57   struct irq_handler *next;
  58   short           vectno;
  59 } irq_handler_t;
  60
  61 #define IRQH_ON_LIST    0x100   /* handler is used */
  62
  63 extern irq_handler_t *irq_array[NR_IRQS];
  64 extern void          *irq_vec[NR_IRQS];
  65
  66 int add_irq_handler(int vectno,irq_handler_t *handler);
  67
  68 int del_irq_handler(int vectno,irq_handler_t *handler);
  69
  70 int test_irq_handler(int vectno,const irq_handler_t *handler);
  71
  72 void irq_redirect2vector(int vectno,struct pt_regs *regs);
  73
  74 /* IRQ handling code */
  75
  76 #define sti()                                                   \
  77         ({                                                      \
  78                 unsigned long temp;                             \
  79         __asm__ __volatile__(                                   \
  80         "mrs    %0, cpsr                @ sti\n"                \
  81 "       bic     %0, %0, #128\n"                                 \
  82 "       msr     cpsr_c, %0"                                     \
  83         : "=r" (temp)                                           \
  84         :                                                       \
  85         : "memory", "cc");                                      \
  86         })
  87
  88 #define cli()                                                   \
  89         ({                                                      \
  90                 unsigned long temp;                             \
  91         __asm__ __volatile__(                                   \
  92         "mrs    %0, cpsr                @ cli\n"                \
  93 "       orr     %0, %0, #128\n"                                 \
  94 "       msr     cpsr_c, %0"                                     \
  95         : "=r" (temp)                                           \
  96         :                                                       \
  97         : "memory", "cc");                                      \
  98         })
  99
 100 #define save_and_cli(flags)                                     \
 101         ({                                                      \
 102                 unsigned long temp;                             \
 103                 (void) (&temp == &flags);                       \
 104         __asm__ __volatile__(                                   \
 105         "mrs    %0, cpsr                @ save_and_cli\n"       \
 106 "       orr     %1, %0, #128\n"                                 \
 107 "       msr     cpsr_c, %1"                                     \
 108         : "=r" (flags), "=r" (temp)                             \
 109         :                                                       \
 110         : "memory", "cc");                                      \
 111         })
 112
 113 #define save_flags(flags)                                       \
 114         ({                                                      \
 115         __asm__ __volatile__(                                   \
 116         "mrs    %0, cpsr                @ save_flags\n"         \
 117         : "=r" (flags)                                          \
 118         :                                                       \
 119         : "memory", "cc");                                      \
 120         })
 121
 122 #define restore_flags(flags)                                    \
 123         __asm__ __volatile__(                                   \
 124         "msr    cpsr_c, %0              @ restore_flags\n"      \
 125         :                                                       \
 126         : "r" (flags)                                           \
 127         : "memory", "cc")
 128
 129
 130 /* FIQ handling code */
 131
 132 #define fiq_sti()                                                   \
 133         ({                                                      \
 134                 unsigned long temp;                             \
 135         __asm__ __volatile__(                                   \
 136         "mrs    %0, cpsr                @ sti\n"                \
 137 "       bic     %0, %0, #64\n"                                  \
 138 "       msr     cpsr_c, %0"                                     \
 139         : "=r" (temp)                                           \
 140         :                                                       \
 141         : "memory", "cc");                                      \
 142         })
 143
 144 #define fiq_cli()                                                   \
 145         ({                                                      \
 146                 unsigned long temp;                             \
 147         __asm__ __volatile__(                                   \
 148         "mrs    %0, cpsr                @ cli\n"                \
 149 "       orr     %0, %0, #64\n"                                  \
 150 "       msr     cpsr_c, %0"                                     \
 151         : "=r" (temp)                                           \
 152         :                                                       \
 153         : "memory", "cc");                                      \
 154         })
 155
 156 #define fiq_save_and_cli(flags)                                     \
 157         ({                                                      \
 158                 unsigned long temp;                             \
 159                 (void) (&temp == &flags);                       \
 160         __asm__ __volatile__(                                   \
 161         "mrs    %0, cpsr                @ save_and_cli\n"       \
 162 "       orr     %1, %0, #192\n"                                 \
 163 "       msr     cpsr_c, %1"                                     \
 164         : "=r" (flags), "=r" (temp)                             \
 165         :                                                       \
 166         : "memory", "cc");                                      \
 167         })
 168
 169 void __cpu_coherent_range(unsigned long start, unsigned long end);
 170
 171 static inline void flush_icache_range(unsigned long start, unsigned long end)
 172 {
 173         __cpu_coherent_range(start, end);
 174 }
 175
 176 /* atomic access routines */
 177
 178 //typedef unsigned long atomic_t;
 179
 180 static inline void atomic_clear_mask(unsigned long mask, volatile unsigned long *addr)
 181 {
 182         unsigned long flags;
 183
 184         save_and_cli(flags);
 185         *addr &= ~mask;
 186         restore_flags(flags);
 187 }
 188
 189 static inline void atomic_set_mask(unsigned long mask, volatile unsigned long *addr)
 190 {
 191         unsigned long flags;
 192
 193         save_and_cli(flags);
 194         *addr |= mask;
 195         restore_flags(flags);
 196 }
 197
 198 static inline void set_bit(int nr, volatile unsigned long *addr)
 199 {
 200         unsigned long flags;
 201
 202         save_and_cli(flags);
 203         *addr |= 1<<nr;
 204         restore_flags(flags);
 205 }
 206
 207 static inline void clear_bit(int nr, volatile unsigned long *addr)
 208 {
 209         unsigned long flags;
 210
 211         save_and_cli(flags);
 212         *addr &= ~(1<<nr);
 213         restore_flags(flags);
 214 }
 215
 216 static inline int test_bit(int nr, volatile unsigned long *addr)
 217 {
 218         return ((*addr) & (1<<nr))?1:0;
 219 }
 220
 221 static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
 222 {
 223         unsigned long flags;
 224         long m=(1<<nr);
 225         long r;
 226
 227         save_and_cli(flags);
 228         r=*addr;
 229         *addr=r|m;
 230         restore_flags(flags);
 231         return r&m?1:0;
 232 }
 233
 234 #define __memory_barrier() \
 235  __asm__ __volatile__("": : : "memory")
 236
 237 /*masked fields macros*/
 238
 239 #define __val2mfld(mask,val) (((mask)&~((mask)<<1))*(val)&(mask))
 240 #define __mfld2val(mask,val) (((val)&(mask))/((mask)&~((mask)<<1)))
 241
 242 static inline void outb(unsigned int port, int val) {
 243   *(volatile unsigned char *)(port)=val;
 244 }
 245
 246 static inline unsigned char inb(unsigned int port) {
 247   return *(volatile unsigned char *)(port);
 248 }
 249
 250 #endif /* _ARM_CPU_DEF_H */
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