2 * Header file for the Linux CAN-bus driver.
3 * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
4 * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
5 * email:pisa@cmp.felk.cvut.cz
6 * This software is released under the GPL-License.
7 * Version lincan-0.2 9 Jul 2003
12 #include <linux/version.h>
13 #include <linux/wait.h>
14 #include <linux/interrupt.h>
16 #include "./constants.h"
17 #include "./can_queue.h"
20 #define DEBUGMSG(fmt,args...) printk(KERN_ERR "can.o (debug): " fmt,\
23 #define DEBUGMSG(fmt,args...)
26 #define CANMSG(fmt,args...) printk(KERN_ERR "can.o: " fmt,##args)
28 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,7))
31 (MINOR(file->f_dentry->d_inode->i_rdev))
33 #else /* Linux kernel > 2.5.7 */
36 (minor(file->f_dentry->d_inode->i_rdev))
37 #endif /* Linux kernel > 2.5.7 */
39 #if ((LINUX_VERSION_CODE < KERNEL_VERSION(2,5,68)) && !defined(IRQ_RETVAL))
40 typedef void irqreturn_t;
46 struct canhardware_t {
48 struct rtr_id *rtr_queue;
50 struct candevice_t *candevice[MAX_HW_CARDS];
54 char *hwname; /* text board type */
55 int candev_idx; /* board index in canhardware_t.candevice[] */
56 unsigned long io_addr; /* IO/physical MEM address */
57 unsigned long res_addr; /* optional seset register port */
58 unsigned long dev_base_addr; /* CPU translated IO/virtual MEM address */
61 /* Hardware chip configuration. In case of multiple chips *chip
62 * is the first in an array of chip_t structures.
67 struct chip_t *chip[MAX_HW_CHIPS];
69 struct hwspecops_t *hwspecops;
71 struct canhardware_t *hosthardware_p;
76 int chip_idx; /* chip index in candevice_t.chip[] */
78 unsigned long chip_base_addr;
80 int clock; // Chip clock in Hz
82 /* This is copy of the chip->hostdevice->hwspecops->read_register
83 * and the chip->hostdevice->hwspecops->write_register.
84 * The pointers were added for performance reasons, and are initialized
85 * by init_chip_struct() from values given by hardware specific init_hwspecops().
87 void (*write_register)(unsigned char data,unsigned long address);
88 unsigned (*read_register)(unsigned long address);
90 /* sja_cdr_reg holds hardware specific options for the Clock Divider
91 * register. Options defined in the sja1000.h file:
92 * CDR_CLKOUT_MASK, CDR_CLK_OFF, CDR_RXINPEN, CDR_CBP, CDR_PELICAN
94 * sja_ocr_reg holds hardware specific options for the Output Control
95 * register. Options defined in the sja1000.h file:
96 * OCR_MODE_BIPHASE, OCR_MODE_TEST, OCR_MODE_NORMAL, OCR_MODE_CLOCK,
97 * OCR_TX0_LH, OCR_TX1_ZZ.
99 * int_clk_reg holds hardware specific options for the Clock Out
100 * register. Options defined in the i82527.h file:
101 * iCLK_CD0, iCLK_CD1, iCLK_CD2, iCLK_CD3, iCLK_SL0, iCLK_SL1.
103 * int_bus_reg holds hardware specific options for the Bus Configuration
104 * register. Options defined in the i82527.h file:
105 * iBUS_DR0, iBUS_DR1, iBUS_DT1, iBUS_POL, iBUS_CBY.
107 * int_cpu_reg holds hardware specific options for the CPU Interface
108 * register. Options defined in the i82527.h file:
109 * iCPU_CEN, iCPU_MUX, iCPU_SLP, iCPU_PWD, iCPU_DMC, iCPU_DSC, iCPU_RST.
111 unsigned short sja_cdr_reg; // sja1000 only!
112 unsigned short sja_ocr_reg; // sja1000 only!
113 unsigned short int_cpu_reg; // intel 82527 only!
114 unsigned short int_clk_reg; // intel 82527 only!
115 unsigned short int_bus_reg; // intel 82527 only!
117 struct msgobj_t *msgobj[MAX_MSGOBJS];
119 struct chipspecops_t *chipspecops;
121 struct candevice_t *hostdevice;
123 int max_objects; /* 1 for sja1000, 15 for */
127 unsigned long obj_base_addr;
128 unsigned int minor; /* associated device minor number */
129 unsigned int object; /* object number in chip_t +1 for debug printk */
133 struct canque_ends_t *qends;
134 struct canque_edge_t *tx_qedge;
135 struct canque_slot_t *tx_slot;
136 struct canmsg_t rx_msg;
138 struct chip_t *hostchip;
141 struct list_head obj_users;
144 #define CAN_USER_MAGIC 0x05402033
147 struct list_head peers;
148 struct canque_ends_t *qends;
149 struct file *file; /* back ptr to file */
150 struct msgobj_t *msgobj;
151 struct canque_edge_t *rx_edge0; /* simplifies IOCTL */
156 int (*request_io)(struct candevice_t *candev);
157 int (*release_io)(struct candevice_t *candev);
158 int (*reset)(struct candevice_t *candev);
159 int (*init_hw_data)(struct candevice_t *candev);
160 int (*init_chip_data)(struct candevice_t *candev, int chipnr);
161 int (*init_obj_data)(struct chip_t *chip, int objnr);
162 int (*program_irq)(struct candevice_t *candev);
163 void (*write_register)(unsigned char data,unsigned long address);
164 unsigned (*read_register)(unsigned long address);
167 struct chipspecops_t {
168 int (*chip_config)(struct chip_t *chip);
169 int (*baud_rate)(struct chip_t *chip, int rate, int clock, int sjw,
170 int sampl_pt, int flags);
171 int (*standard_mask)(struct chip_t *chip, unsigned short code,
172 unsigned short mask);
173 int (*extended_mask)(struct chip_t *chip, unsigned long code,
175 int (*message15_mask)(struct chip_t *chip, unsigned long code,
177 int (*clear_objects)(struct chip_t *chip);
178 int (*config_irqs)(struct chip_t *chip, short irqs);
179 int (*pre_read_config)(struct chip_t *chip, struct msgobj_t *obj);
180 int (*pre_write_config)(struct chip_t *chip, struct msgobj_t *obj,
181 struct canmsg_t *msg);
182 int (*send_msg)(struct chip_t *chip, struct msgobj_t *obj,
183 struct canmsg_t *msg);
184 int (*remote_request)(struct chip_t *chip, struct msgobj_t *obj);
185 int (*check_tx_stat)(struct chip_t *chip);
186 int (*wakeup_tx)(struct chip_t *chip, struct msgobj_t *obj);
187 int (*enable_configuration)(struct chip_t *chip);
188 int (*disable_configuration)(struct chip_t *chip);
189 int (*set_btregs)(struct chip_t *chip, unsigned short btr0,
190 unsigned short btr1);
191 int (*start_chip)(struct chip_t *chip);
192 int (*stop_chip)(struct chip_t *chip);
193 irqreturn_t (*irq_handler)(int irq, void *dev_id, struct pt_regs *regs);
198 struct mem_addr *next;
201 /* Structure for the RTR queue */
204 struct canmsg_t *rtr_message;
205 #if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,3,0))
206 struct wait_queue *rtr_wq;
208 struct __wait_queue_head rtr_wq;
214 extern int minor[MAX_TOT_CHIPS];
217 extern char *hw[MAX_HW_CARDS];
218 extern int irq[MAX_IRQ];
219 extern unsigned long io[MAX_HW_CARDS];
221 extern struct canhardware_t *hardware_p;
222 extern struct chip_t *chips_p[MAX_TOT_CHIPS];
223 extern struct msgobj_t *objects_p[MAX_TOT_MSGOBJS];
225 extern struct mem_addr *mem_head;
227 /* Inline function to write to the hardware registers. The argument address is
228 * relative to the memory map of the chip and not the absolute memory address.
230 extern inline void can_write_reg(const struct chip_t *chip, unsigned char data, unsigned address)
232 unsigned long address_to_write;
233 address_to_write = chip->chip_base_addr+address;
234 chip->write_register(data, address_to_write);
237 extern inline unsigned can_read_reg(const struct chip_t *chip, unsigned address)
239 unsigned long address_to_read;
240 address_to_read = chip->chip_base_addr+address;
241 return chip->read_register(address_to_read);
244 extern inline void canobj_write_reg(const struct chip_t *chip, const struct msgobj_t *obj,
245 unsigned char data, unsigned address)
247 unsigned long address_to_write;
248 address_to_write = obj->obj_base_addr+address;
249 chip->write_register(data, address_to_write);
252 extern inline unsigned canobj_read_reg(const struct chip_t *chip, const struct msgobj_t *obj,
255 unsigned long address_to_read;
256 address_to_read = obj->obj_base_addr+address;
257 return chip->read_register(address_to_read);
260 int can_base_addr_fixup(struct candevice_t *candev, unsigned long new_base);
261 int can_request_io_region(unsigned long start, unsigned long n, const char *name);
262 void can_release_io_region(unsigned long start, unsigned long n);
263 int can_request_mem_region(unsigned long start, unsigned long n, const char *name);
264 void can_release_mem_region(unsigned long start, unsigned long n);